* [PATCH 00/19] Add base device tree files for QDU1000/QRU1000
@ 2022-10-01 3:06 Melody Olvera
2022-10-01 3:06 ` [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
` (19 more replies)
0 siblings, 20 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
This series adds the base device tree files and DTS support for the
Qualcomm QDU1000 and QRU1000 IDP SoCs, including the clocks, tlmm, smmu,
regulators, mmc, interconnects, cpufreq, and qup.
This patchset is based off of [1] which adds support for the PMIC arb used
on these SoCs.
The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit
1000 are new SoCs meant for enabling Open RAN solutions. See more at
https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf
[1] https://lore.kernel.org/all/20220914165212.3705892-3-vkoul@kernel.org/
Melody Olvera (19):
arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
arm64: dts: qcom: qdru1000: Add tlmm nodes
arm64: dts: qcom: qdu1000: Add reserved memory nodes
arm64: dts: qcom: qru1000: Add reserved memory nodes
arm64: dts: qcom: qdru1000: Add smmu nodes
arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes
arm64: dts: qcom: qru1000-idp: Add RPMH regulators nodes
arm64: dts: qcom: qdru1000: Add interconnect nodes
arm64: dts: qcom: qdru1000: Add rpmhpd node
arm64: dts: qcom: qdru1000: Add spmi node
arm64: dts: qcom: qdu1000-idp: Include pmic file
arm64: dts: qcom: qru1000-idp: Include pmic file
arm64: dts: qcom: qdru1000: Add cpufreq support
arm64: dts: qcom: qdru1000: Add additional QUP nodes
arm64: dts: qcom: qdru1000: Add gpi_dma nodes
arm64: dts: qcom: qdru1000: Add I2C nodes for QUP
arm64: dts: qcom: qdru1000: Add SPI devices to QUP nodes
arm64: dts: qcom: qdru1000: Add additional UART instances
arch/arm64/boot/dts/qcom/Makefile | 2 +
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 1499 ++++++++++++++++++++++
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 231 ++++
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 160 +++
arch/arm64/boot/dts/qcom/qru1000-idp.dts | 231 ++++
arch/arm64/boot/dts/qcom/qru1000.dtsi | 155 +++
6 files changed, 2278 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
base-commit: 987a926c1d8a40e4256953b04771fbdb63bc7938
prerequisite-patch-id: 79eb132c9ff1a0feb653bef87e3e93f6841f81ee
prerequisite-patch-id: e25ad91d89a9d4a24f1081e5c03cb20678c6e94b
prerequisite-patch-id: e882ee6dbd8d55069a313e9c2b10a1ea7f6b80fb
prerequisite-patch-id: 85c1f1845b2e69ef50e7e8391426e6cab6c66381
prerequisite-patch-id: 5fd7e4f92a95a7dedc49fd39fdffd5e02c838190
prerequisite-patch-id: c8d9475d6bb2d24102e5bfee65f74d2c0365db68
prerequisite-patch-id: a03c3288ed927cbab6a42d3ad49df4347cfc9722
prerequisite-patch-id: aa7ddf85d2a1c02e4d649632425910e44f73a567
prerequisite-patch-id: 5e7a02607aecd3f5346a2f450982601cf6935e54
--
2.37.3
^ permalink raw reply [flat|nested] 46+ messages in thread
* [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 7:22 ` Dmitry Baryshkov
2022-10-01 9:12 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera
` (18 subsequent siblings)
19 siblings, 2 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
descriptions of CPUs, GCC, RPMHCC, UART, and interrupt-controller to
boot to shell with console on these SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 370 +++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 +
arch/arm64/boot/dts/qcom/qru1000.dtsi | 10 +
3 files changed, 390 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
new file mode 100644
index 000000000000..3610f94bef35
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: BSD-3-Clause-Clear
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-qdru1000.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen: chosen { };
+
+
+ clocks {
+ xo_board: xo_board {
+ compatible = "fixed-clock";
+ clock-frequency = <19200000>;
+ clock-output-names = "xo_board";
+ #clock-cells = <0>;
+ };
+
+ sleep_clk: sleep_clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ power-domain-names = "psci";
+ power-domains = <&CPU_PD0>;
+ next-level-cache = <&L2_0>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD1>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_100>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD2>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_200>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ power-domains = <&CPU_PD3>;
+ power-domain-names = "psci";
+ next-level-cache = <&L2_300>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ SILVER_OFF: silver-c4 { /* C4 */
+ compatible = "arm,idle-state";
+ idle-state-name = "rail-pc";
+ entry-latency-us = <274>;
+ exit-latency-us = <480>;
+ min-residency-us = <3934>;
+ arm,psci-suspend-param = <0x40000004>;
+ local-timer-stop;
+ };
+
+ CLUSTER_PWR_DN: cluster-d4 { /* D4 */
+ compatible = "domain-idle-state";
+ idle-state-name = "l3-off";
+ entry-latency-us = <584>;
+ exit-latency-us = <2332>;
+ min-residency-us = <6118>;
+ arm,psci-suspend-param = <0x41000044>;
+ };
+
+ APSS_OFF: cluster-e3 { /* E3 */
+ compatible = "domain-idle-state";
+ idle-state-name = "llcc-off";
+ entry-latency-us = <2893>;
+ exit-latency-us = <4023>;
+ min-residency-us = <9987>;
+ arm,psci-suspend-param = <0x41003344>;
+ };
+ };
+
+ firmware {
+ qcom_scm {
+ compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm";
+ #reset-cells = <1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+
+ CPU_PD0: cpu-pd0 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&SILVER_OFF>;
+ };
+
+ CPU_PD1: cpu-pd1 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&SILVER_OFF>;
+ };
+
+ CPU_PD2: cpu-pd2 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&SILVER_OFF>;
+ };
+
+ CPU_PD3: cpu-pd3 {
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ domain-idle-states = <&SILVER_OFF>;
+ };
+
+ CLUSTER_PD: cluster-pd {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
+ };
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ gcc: clock-controller@80000 {
+ compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon";
+ reg = <0x0 0x80000 0x0 0x1f4200>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
+ clock-names = "bi_tcxo", "sleep_clk";
+ };
+
+ qupv3_id_0: geniqup@9c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0x9c0000 0x0 0x2000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ uart7: serial@99c000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0x0 0x99c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x1f40000 0x0 0x20000>;
+ #hwlock-cells = <1>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,pdc";
+ reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
+ reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg";
+ qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
+ <94 609 31>, <125 63 1>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ intc: interrupt-controller@17200000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #redistributor-regions = <1>;
+ redistributor-stride = <0x0 0x20000>;
+ reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
+ <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ timer@17420000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ reg = <0x0 0x17420000 0x0 0x1000>;
+ clock-frequency = <19200000>;
+
+ frame@17421000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17421000 0x0 0x1000>,
+ <0x0 0x17422000 0x0 0x1000>;
+ };
+
+ frame@17423000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17423000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17425000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17425000 0x0 0x1000>,
+ <0x0 0x17426000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17427000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17427000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17429000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17429000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@1742b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x1742b000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@1742d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x1742d000 0x0 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@17a00000 {
+ label = "apps_rsc";
+ compatible = "qcom,rpmh-rsc";
+ reg = <0x0 0x17a00000 0x0 0x10000>,
+ <0x0 0x17a10000 0x0 0x10000>,
+ <0x0 0x17a20000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
+ <WAKE_TCS 3>, <CONTROL_TCS 0>;
+
+ apps_bcm_voter: bcm_voter {
+ compatible = "qcom,bcm-voter";
+ };
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
+ };
+
+ arch_timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ clock-frequency = <19200000>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
new file mode 100644
index 000000000000..ba195e7ffc38
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: BSD-3-Clause-Clear
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "qdru1000.dtsi"
+
+/ {
+ qcom,msm-id = <545 0x10000>, <587 0x10000>;
+};
diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi
new file mode 100644
index 000000000000..1639a4b3c1fb
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: BSD-3-Clause-Clear
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include "qdru1000.dtsi"
+
+/ {
+ qcom,msm-id = <539 0x10000>, <588 0x10000>, <589 0x10000>, <590 0x10000>;
+};
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
2022-10-01 3:06 ` [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 7:28 ` Dmitry Baryshkov
2022-10-01 9:12 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes Melody Olvera
` (17 subsequent siblings)
19 siblings, 2 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000
SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/Makefile | 2 ++
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 30 ++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/qru1000-idp.dts | 30 ++++++++++++++++++++++++
3 files changed, 62 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 1d86a33de528..398920c530b0 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -152,3 +152,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
+dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
new file mode 100644
index 000000000000..0ecf9a7c41ec
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: BSD-3-Clause-Clear
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "qdu1000.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QDU1000 IDP";
+ compatible = "qcom,qdu1000-idp", "qcom,qdu1000";
+ qcom,board-id = <0x22 0x0>;
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
new file mode 100644
index 000000000000..ddb4ea17f7d2
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: BSD-3-Clause-Clear
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "qru1000.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. QRU1000 IDP";
+ compatible = "qcom,qru1000-idp", "qcom,qru1000";
+ qcom,board-id = <0x22 0x0>;
+
+ aliases {
+ serial0 = &uart7;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&qupv3_id_0 {
+ status = "okay";
+};
+
+&uart7 {
+ status = "okay";
+};
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
2022-10-01 3:06 ` [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
2022-10-01 3:06 ` [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 7:26 ` Dmitry Baryshkov
2022-10-01 9:14 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 04/19] arm64: dts: qcom: qdu1000: Add reserved memory nodes Melody Olvera
` (16 subsequent siblings)
19 siblings, 2 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
configuration.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 3610f94bef35..39b9a00d3ad8 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -235,6 +235,8 @@ uart7: serial@99c000 {
reg = <0x0 0x99c000 0x0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
@@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ tlmm: pinctrl@f000000 {
+ compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
+ reg = <0x0 0xf000000 0x0 0x1000000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 151>;
+ wakeup-parent = <&pdc>;
+
+ qup_uart7_default: qup-uart7-default {
+ tx {
+ pins = "gpio134";
+ function = "qup0_se7_l2";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ rx {
+ pins = "gpio135";
+ function = "qup0_se7_l3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,pdc";
reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 04/19] arm64: dts: qcom: qdu1000: Add reserved memory nodes
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (2 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 9:14 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 05/19] arm64: dts: qcom: qru1000: " Melody Olvera
` (15 subsequent siblings)
19 siblings, 1 reply; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add reserved memory nodes for QDU1000 SoCs based on downstream
documentation.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdu1000.dtsi | 150 ++++++++++++++++++++++++++
1 file changed, 150 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
index ba195e7ffc38..e836b2c1b8df 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
@@ -7,4 +7,154 @@
/ {
qcom,msm-id = <545 0x10000>, <587 0x10000>;
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@80000000 {
+ no-map;
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ };
+
+ xbl_dt_log_mem: memory@80600000 {
+ no-map;
+ reg = <0x0 0x80600000 0x0 0x40000>;
+ };
+
+ xbl_ramdump_mem: memory@80640000 {
+ no-map;
+ reg = <0x0 0x80640000 0x0 0x1c0000>;
+ };
+
+ aop_image_mem: memory@80800000 {
+ no-map;
+ reg = <0x0 0x80800000 0x0 0x60000>;
+ };
+
+ aop_cmd_db_mem: memory@80860000 {
+ compatible = "qcom,cmd-db";
+ no-map;
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ };
+
+ aop_config_mem: memory@80880000 {
+ no-map;
+ reg = <0x0 0x80880000 0x0 0x20000>;
+ };
+
+ tme_crash_dump_mem: memory@808a0000 {
+ no-map;
+ reg = <0x0 0x808a0000 0x0 0x40000>;
+ };
+
+ tme_log_mem: memory@808e0000 {
+ no-map;
+ reg = <0x0 0x808e0000 0x0 0x4000>;
+ };
+
+ uefi_log_mem: memory@808e4000 {
+ no-map;
+ reg = <0x0 0x808e4000 0x0 0x10000>;
+ };
+
+ /* secdata region can be reused by apps */
+
+ smem_mem: memory@80900000 {
+ compatible = "qcom,smem";
+ no-map;
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ cpucp_fw_mem: memory@80b00000 {
+ no-map;
+ reg = <0x0 0x80b00000 0x0 0x100000>;
+ };
+
+ xbl_sc_mem: memory@80c00000 {
+ no-map;
+ reg = <0x0 0x80c00000 0x0 0x40000>;
+ };
+
+ /* uefi region can be reused by apps */
+
+ tz_stat_mem: memory@81d00000 {
+ no-map;
+ reg = <0x0 0x81d00000 0x0 0x100000>;
+ };
+
+ tags_mem: memory@81e00000 {
+ no-map;
+ reg = <0x0 0x81e00000 0x0 0x500000>;
+ };
+
+ qtee_mem: memory@82300000 {
+ no-map;
+ reg = <0x0 0x82300000 0x0 0x500000>;
+ };
+
+ ta_mem: memory@82800000 {
+ no-map;
+ reg = <0x0 0x82800000 0x0 0xa00000>;
+ };
+
+ fs1_mem: memory@83200000 {
+ no-map;
+ reg = <0x0 0x83200000 0x0 0x400000>;
+ };
+
+ fs2_mem: memory@83600000 {
+ no-map;
+ reg = <0x0 0x83600000 0x0 0x400000>;
+ };
+
+ fs3_mem: memory@83a00000 {
+ no-map;
+ reg = <0x0 0x83a00000 0x0 0x400000>;
+ };
+
+ /* Linux kernel image is loaded at 0x83e00000 */
+
+ ipa_fw_mem: memory@8be00000 {
+ no-map;
+ reg = <0x0 0x8be00000 0x0 0x10000>;
+ };
+
+ ipa_gsi_mem: memory@8be10000 {
+ no-map;
+ reg = <0x0 0x8be10000 0x0 0x14000>;
+ };
+
+ mpss_mem: memory@8c000000 {
+ no-map;
+ reg = <0x0 0x8c000000 0x0 0x12c00000>;
+ };
+
+ q6_mpss_dtb_mem: memory@9ec00000 {
+ no-map;
+ reg = <0x0 0x9ec00000 0x0 0x80000>;
+ };
+
+ tenx_mem: memory@a0000000 {
+ no-map;
+ reg = <0x0 0xa0000000 0x0 0x19600000>;
+ };
+
+ oem_tenx_mem: memory@b9600000 {
+ no-map;
+ reg = <0x0 0xb9600000 0x0 0x6a00000>;
+ };
+
+ tenx_q6_buffer_mem: memory@c0000000 {
+ no-map;
+ reg = <0x0 0xc0000000 0x0 0x3200000>;
+ };
+
+ ipa_buffer_mem: memory@c3200000 {
+ no-map;
+ reg = <0x0 0xc3200000 0x0 0x12c00000>;
+ };
+ };
};
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 05/19] arm64: dts: qcom: qru1000: Add reserved memory nodes
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (3 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 04/19] arm64: dts: qcom: qdu1000: Add reserved memory nodes Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 06/19] arm64: dts: qcom: qdru1000: Add smmu nodes Melody Olvera
` (14 subsequent siblings)
19 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add reserved memory nodes for QRU1000 SoCs based on downstream
documentation.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qru1000.dtsi | 145 ++++++++++++++++++++++++++
1 file changed, 145 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi
index 1639a4b3c1fb..be74be4bee4b 100644
--- a/arch/arm64/boot/dts/qcom/qru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi
@@ -7,4 +7,149 @@
/ {
qcom,msm-id = <539 0x10000>, <588 0x10000>, <589 0x10000>, <590 0x10000>;
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@80000000 {
+ no-map;
+ reg = <0x0 0x80000000 0x0 0x600000>;
+ };
+
+ xbl_dt_log_mem: memory@80600000 {
+ no-map;
+ reg = <0x0 0x80600000 0x0 0x40000>;
+ };
+
+ xbl_ramdump_mem: memory@80640000 {
+ no-map;
+ reg = <0x0 0x80640000 0x0 0x1c0000>;
+ };
+
+ aop_image_mem: memory@80800000 {
+ no-map;
+ reg = <0x0 0x80800000 0x0 0x60000>;
+ };
+
+ aop_cmd_db_mem: memory@80860000 {
+ compatible = "qcom,cmd-db";
+ no-map;
+ reg = <0x0 0x80860000 0x0 0x20000>;
+ };
+
+ aop_config_mem: memory@80880000 {
+ no-map;
+ reg = <0x0 0x80880000 0x0 0x20000>;
+ };
+
+ tme_crash_dump_mem: memory@808a0000 {
+ no-map;
+ reg = <0x0 0x808a0000 0x0 0x40000>;
+ };
+
+ tme_log_mem: memory@808e0000 {
+ no-map;
+ reg = <0x0 0x808e0000 0x0 0x4000>;
+ };
+
+ uefi_log_mem: memory@808e4000 {
+ no-map;
+ reg = <0x0 0x808e4000 0x0 0x10000>;
+ };
+
+ /* secdata region can be reused by apps */
+
+ smem_mem: memory@80900000 {
+ compatible = "qcom,smem";
+ no-map;
+ reg = <0x0 0x80900000 0x0 0x200000>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ cpucp_fw_mem: memory@80b00000 {
+ no-map;
+ reg = <0x0 0x80b00000 0x0 0x100000>;
+ };
+
+ xbl_sc_mem: memory@80c00000 {
+ no-map;
+ reg = <0x0 0x80c00000 0x0 0x40000>;
+ };
+
+ /* uefi region can be reused by apps */
+
+ tz_stat_mem: memory@81d00000 {
+ no-map;
+ reg = <0x0 0x81d00000 0x0 0x100000>;
+ };
+
+ tags_mem: memory@81e00000 {
+ no-map;
+ reg = <0x0 0x81e00000 0x0 0x500000>;
+ };
+
+ qtee_mem: memory@82300000 {
+ no-map;
+ reg = <0x0 0x82300000 0x0 0x500000>;
+ };
+
+ truested_apps_mem: memory@82800000 {
+ no-map;
+ reg = <0x0 0x82800000 0x0 0xa00000>;
+ };
+
+ fs1_mem: memory@83200000 {
+ no-map;
+ reg = <0x0 0x83200000 0x0 0x400000>;
+ };
+
+ fs2_mem: memory@83600000 {
+ no-map;
+ reg = <0x0 0x83600000 0x0 0x400000>;
+ };
+
+ fs3_mem: memory@83a00000 {
+ no-map;
+ reg = <0x0 0x83a00000 0x0 0x400000>;
+ };
+
+ /* Linux kernel image is loaded at 0x83e00000 */
+
+ ipa_fw_mem: memory@8be00000 {
+ no-map;
+ reg = <0x0 0x8be00000 0x0 0x10000>;
+ };
+
+ ipa_gsi_mem: memory@8be10000 {
+ no-map;
+ reg = <0x0 0x8be10000 0x0 0x14000>;
+ };
+
+ mpss_mem: memory@8c000000 {
+ no-map;
+ reg = <0x0 0x8c000000 0x0 0x12c00000>;
+ };
+
+ q6_mpss_dtb_mem: memory@9ec00000 {
+ no-map;
+ reg = <0x0 0x9ec00000 0x0 0x80000>;
+ };
+
+ oem_tenx_mem: memory@a0000000 {
+ no-map;
+ reg = <0x0 0xa0000000 0x0 0x6400000>;
+ };
+
+ mpss_diag_buffer_mem: memory@aea00000 {
+ no-map;
+ reg = <0x0 0xaea00000 0x0 0x6400000>;
+ };
+
+ tenx_q6_buffer_mem: memory@b4e00000 {
+ no-map;
+ reg = <0x0 0xb4e00000 0x0 0x3200000>;
+ };
+ };
};
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 06/19] arm64: dts: qcom: qdru1000: Add smmu nodes
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (4 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 05/19] arm64: dts: qcom: qru1000: " Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 7:23 ` Dmitry Baryshkov
2022-10-01 3:06 ` [PATCH 07/19] arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes Melody Olvera
` (13 subsequent siblings)
19 siblings, 1 reply; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add smmu nodes for the QDU1000 and QRU1000 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 57 ++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 39b9a00d3ad8..8c2af08b8329 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -396,5 +396,62 @@ arch_timer: timer {
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
+
+ apps_smmu: apps-smmu@15000000 {
+ compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500",
+ "arm,mmu-500";
+ reg = <0x0 0x15000000 0x0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <2>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
};
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 07/19] arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (5 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 06/19] arm64: dts: qcom: qdru1000: Add smmu nodes Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 9:15 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 08/19] arm64: dts: qcom: qru1000-idp: " Melody Olvera
` (12 subsequent siblings)
19 siblings, 1 reply; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add RPMH regulators for the QDU1000 IDP platform.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 200 +++++++++++++++++++++++
1 file changed, 200 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
index 0ecf9a7c41ec..654b50220c2e 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "qdu1000.dtsi"
/ {
@@ -19,6 +20,205 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ ppvar_sys: ppvar-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "ppvar_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&ppvar_sys>;
+ };
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vph_pwr>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>;
+ vdd-l6-l9-supply = <&vreg_s6a_0p9>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>;
+ vdd-l13-l16-l17-supply = <&vph_pwr>;
+
+ vreg_s2a_0p5: smps2 {
+ regulator-name = "vreg_s2a_0p5";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <570000>;
+ };
+
+ vreg_s3a_1p05: smps3 {
+ regulator-name = "vreg_s3a_1p05";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1170000>;
+ };
+
+ vreg_s4a_1p8: smps4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_s5a_2p0: smps5 {
+ regulator-name = "vreg_s5a_2p0";
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-name = "vreg_s6a_0p9";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_s7a_1p2: smps7 {
+ regulator-name = "vreg_s7a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_s8a_1p3: smps8 {
+ regulator-name = "vreg_s8a_1p3";
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_l1a_0p91: ldo1 {
+ regulator-name = "vreg_l1a_0p91";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l2a_2p3: ldo2 {
+ regulator-name = "vreg_l2a_2p3";
+ regulator-min-microvolt = <2970000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l3a_1p2: ldo3 {
+ regulator-name = "vreg_l3a_1p2";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l5a_0p8: ldo5 {
+ regulator-name = "vreg_l5a_0p8";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l6a_0p91: ldo6 {
+ regulator-name = "vreg_l6a_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-name = "vreg_l7a_1p8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+
+ };
+
+ vreg_l8a_0p91: ldo8 {
+ regulator-name = "vreg_l8a_0p91";
+ regulator-min-microvolt = <888000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l9a_0p91: ldo9 {
+ regulator-name = "vreg_l8a_0p91";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l10a_2p95: ldo10 {
+ regulator-name = "vreg_l10a_2p95";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l11a_0p91: ldo11 {
+ regulator-name = "vreg_l11a_0p91";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-name = "vreg_l14a_1p8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l15a_1p8: ldo15 {
+ regulator-name = "vreg_l15a_1p8";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l16a_1p8: ldo16 {
+ regulator-name = "vreg_l16a_1p8";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l17a_3p3: ldo17 {
+ regulator-name = "vreg_l17a_3p3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l18a_1p2: ldo18 {
+ regulator-name = "vreg_l18a_1p2";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
};
&qupv3_id_0 {
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 08/19] arm64: dts: qcom: qru1000-idp: Add RPMH regulators nodes
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (6 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 07/19] arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 9:15 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 09/19] arm64: dts: qcom: qdru1000: Add interconnect nodes Melody Olvera
` (11 subsequent siblings)
19 siblings, 1 reply; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add RPMH regulators for the QRU1000 IDP platform.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qru1000-idp.dts | 200 +++++++++++++++++++++++
1 file changed, 200 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
index ddb4ea17f7d2..8d27923dc470 100644
--- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "qru1000.dtsi"
/ {
@@ -19,6 +20,205 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ ppvar_sys: ppvar-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "ppvar_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+
+ regulator-always-on;
+ regulator-boot-on;
+
+ vin-supply = <&ppvar_sys>;
+ };
+};
+
+&apps_rsc {
+ pm8150-rpmh-regulators {
+ compatible = "qcom,pm8150-rpmh-regulators";
+ qcom,pmic-id = "a";
+
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s2-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s4-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+
+ vdd-l1-l8-l11-supply = <&vreg_s6a_0p9>;
+ vdd-l2-l10-supply = <&vph_pwr>;
+ vdd-l3-l4-l5-l18-supply = <&vreg_s5a_2p0>;
+ vdd-l6-l9-supply = <&vreg_s6a_0p9>;
+ vdd-l7-l12-l14-l15-supply = <&vreg_s4a_1p8>;
+ vdd-l13-l16-l17-supply = <&vph_pwr>;
+
+ vreg_s2a_0p5: smps2 {
+ regulator-name = "vreg_s2a_0p5";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <570000>;
+ };
+
+ vreg_s3a_1p05: smps3 {
+ regulator-name = "vreg_s3a_1p05";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1170000>;
+ };
+
+ vreg_s4a_1p8: smps4 {
+ regulator-name = "vreg_s4a_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vreg_s5a_2p0: smps5 {
+ regulator-name = "vreg_s5a_2p0";
+ regulator-min-microvolt = <1904000>;
+ regulator-max-microvolt = <2000000>;
+ };
+
+ vreg_s6a_0p9: smps6 {
+ regulator-name = "vreg_s6a_0p9";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1128000>;
+ };
+
+ vreg_s7a_1p2: smps7 {
+ regulator-name = "vreg_s7a_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ vreg_s8a_1p3: smps8 {
+ regulator-name = "vreg_s8a_1p3";
+ regulator-min-microvolt = <1352000>;
+ regulator-max-microvolt = <1352000>;
+ };
+
+ vreg_l1a_0p91: ldo1 {
+ regulator-name = "vreg_l1a_0p91";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l2a_2p3: ldo2 {
+ regulator-name = "vreg_l2a_2p3";
+ regulator-min-microvolt = <2970000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l3a_1p2: ldo3 {
+ regulator-name = "vreg_l3a_1p2";
+ regulator-min-microvolt = <920000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l5a_0p8: ldo5 {
+ regulator-name = "vreg_l5a_0p8";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l6a_0p91: ldo6 {
+ regulator-name = "vreg_l6a_0p91";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l7a_1p8: ldo7 {
+ regulator-name = "vreg_l7a_1p8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+
+ };
+
+ vreg_l8a_0p91: ldo8 {
+ regulator-name = "vreg_l8a_0p91";
+ regulator-min-microvolt = <888000>;
+ regulator-max-microvolt = <925000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l9a_0p91: ldo9 {
+ regulator-name = "vreg_l8a_0p91";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l10a_2p95: ldo10 {
+ regulator-name = "vreg_l10a_2p95";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l11a_0p91: ldo11 {
+ regulator-name = "vreg_l11a_0p91";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l12a_1p8: ldo12 {
+ regulator-name = "vreg_l12a_1p8";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <1504000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l14a_1p8: ldo14 {
+ regulator-name = "vreg_l14a_1p8";
+ regulator-min-microvolt = <1650000>;
+ regulator-max-microvolt = <1950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l15a_1p8: ldo15 {
+ regulator-name = "vreg_l15a_1p8";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l16a_1p8: ldo16 {
+ regulator-name = "vreg_l16a_1p8";
+ regulator-min-microvolt = <1710000>;
+ regulator-max-microvolt = <1890000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l17a_3p3: ldo17 {
+ regulator-name = "vreg_l17a_3p3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+
+ vreg_l18a_1p2: ldo18 {
+ regulator-name = "vreg_l18a_1p2";
+ regulator-min-microvolt = <312000>;
+ regulator-max-microvolt = <1304000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_LPM>;
+ };
+ };
};
&qupv3_id_0 {
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 09/19] arm64: dts: qcom: qdru1000: Add interconnect nodes
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (7 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 08/19] arm64: dts: qcom: qru1000-idp: " Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 9:16 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 10/19] arm64: dts: qcom: qdru1000: Add rpmhpd node Melody Olvera
` (10 subsequent siblings)
19 siblings, 1 reply; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add interconnect nodes for the QDU1000 and QRU1000 platforms.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 27 ++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 8c2af08b8329..b85ffd8baf4b 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-qdru1000.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,qdru1000.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -453,5 +454,31 @@ apps_smmu: apps-smmu@15000000 {
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ clk_virt: interconnect-0 {
+ compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ mc_virt: interconnect-1{
+ compatible = "qcom,qdu1000-mc-virt", "qcom,qru1000-mc-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ system_noc: interconnect@1640000 {
+ reg = <0x0 0x1640000 0x0 0x45080>;
+ compatible = "qcom,qdu1000-system-noc", "qcom,qru1000-system-noc";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
+ gem_noc: interconnect@19100000 {
+ reg = <0x0 0x19100000 0x0 0xB8080>;
+ compatible = "qcom,qdu1000-gem-noc", "qcom,qru1000-gem-noc";
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
};
};
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 10/19] arm64: dts: qcom: qdru1000: Add rpmhpd node
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (8 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 09/19] arm64: dts: qcom: qdru1000: Add interconnect nodes Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 11/19] arm64: dts: qcom: qdru1000: Add spmi node Melody Olvera
` (9 subsequent siblings)
19 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add rpmhpd node and opps for QDU1000 and QRU1000 platforms.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 51 ++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index b85ffd8baf4b..c5acdc447074 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,gcc-qdru1000.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,qdru1000.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -386,6 +387,56 @@ rpmhcc: clock-controller {
clock-names = "xo";
clocks = <&xo_board>;
};
+
+ rpmhpd: power-controller {
+ compatible = "qcom,qdu1000-rpmhpd", "qcom,qru1000-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
};
arch_timer: timer {
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 11/19] arm64: dts: qcom: qdru1000: Add spmi node
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (9 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 10/19] arm64: dts: qcom: qdru1000: Add rpmhpd node Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 12/19] arm64: dts: qcom: qdu1000-idp: Include pmic file Melody Olvera
` (8 subsequent siblings)
19 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add the spmi bus for the QDU1000 and QRU1000 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index c5acdc447074..62a6a6e8ca59 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -252,6 +252,24 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ spmi_bus: spmi@c400000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x0 0xc400000 0x0 0x3000>,
+ <0x0 0xc500000 0x0 0x400000>,
+ <0x0 0xc440000 0x0 0x80000>,
+ <0x0 0xc4c0000 0x0 0x10000>,
+ <0x0 0xc42d000 0x0 0x4000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
tlmm: pinctrl@f000000 {
compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
reg = <0x0 0xf000000 0x0 0x1000000>;
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 12/19] arm64: dts: qcom: qdu1000-idp: Include pmic file
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (10 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 11/19] arm64: dts: qcom: qdru1000: Add spmi node Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 9:16 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 13/19] arm64: dts: qcom: qru1000-idp: " Melody Olvera
` (7 subsequent siblings)
19 siblings, 1 reply; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Include the pmic file for the QDU1000 IDP platform.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
index 654b50220c2e..847ed8cc7be0 100644
--- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
@@ -7,6 +7,7 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "qdu1000.dtsi"
+#include "pm8150.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QDU1000 IDP";
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 13/19] arm64: dts: qcom: qru1000-idp: Include pmic file
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (11 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 12/19] arm64: dts: qcom: qdu1000-idp: Include pmic file Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 14/19] arm64: dts: qcom: qdru1000: Add cpufreq support Melody Olvera
` (6 subsequent siblings)
19 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Include the pmic file for the QRU1000 IDP platform.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qru1000-idp.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
index 8d27923dc470..c32211e3963d 100644
--- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts
+++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
@@ -7,6 +7,7 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "qru1000.dtsi"
+#include "pm8150.dtsi"
/ {
model = "Qualcomm Technologies, Inc. QRU1000 IDP";
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 14/19] arm64: dts: qcom: qdru1000: Add cpufreq support
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (12 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 13/19] arm64: dts: qcom: qru1000-idp: " Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 15/19] arm64: dts: qcom: qdru1000: Add additional QUP nodes Melody Olvera
` (5 subsequent siblings)
19 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add cpufreq-epss node for the QDU1000 and QRU1000 SoCs
and add references to it from the cpu nodes.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 62a6a6e8ca59..2fd449df3706 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -45,6 +45,7 @@ CPU0: cpu@0 {
enable-method = "psci";
power-domain-names = "psci";
power-domains = <&CPU_PD0>;
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
@@ -62,6 +63,7 @@ CPU1: cpu@100 {
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
@@ -77,6 +79,7 @@ CPU2: cpu@200 {
enable-method = "psci";
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
@@ -91,6 +94,7 @@ CPU3: cpu@300 {
enable-method = "psci";
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
+ qcom,freq-domains = <&cpufreq_hw 0>;
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
@@ -246,6 +250,18 @@ uart7: serial@99c000 {
};
};
+ cpufreq_hw: cpufreq@17d91000 {
+ compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss",
+ "qcom,cpufreq-epss";
+ reg = <0x0 0x17d91000 0x0 0x1000>;
+ reg-names = "freq-domain0";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dcvsh0_int";
+ #freq-domain-cells = <1>;
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x1f40000 0x0 0x20000>;
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 15/19] arm64: dts: qcom: qdru1000: Add additional QUP nodes
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (13 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 14/19] arm64: dts: qcom: qdru1000: Add cpufreq support Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 16/19] arm64: dts: qcom: qdru1000: Add gpi_dma nodes Melody Olvera
` (4 subsequent siblings)
19 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add additional QUP nodes and update previous nodes with
approrpiate interconnects and iommus.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 2fd449df3706..5d3932ad67a1 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -231,6 +231,15 @@ qupv3_id_0: geniqup@9c0000 {
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ iommus = <&apps_smmu 0xe3 0x0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0
+ &clk_virt SLAVE_QUP_CORE_0 0>;
+ interconnect-names = "qup-core";
+ qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+ qcom,iommu-geometry = <0x40000000 0x10000000>;
+ qcom,iommu-dma = "fastmap";
+ dma-coherent;
+
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -250,6 +259,21 @@ uart7: serial@99c000 {
};
};
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x0 0xac0000 0x0 0x2000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ iommus = <&apps_smmu 0x103 0x0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clock-names = "m-ahb", "s-ahb";
+
+ ranges;
+ status = "disabled";
+ };
+
+
cpufreq_hw: cpufreq@17d91000 {
compatible = "qcom, qdu1000-cpufreq-epss", "qcom, qru1000-cpufreq-epss",
"qcom,cpufreq-epss";
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 16/19] arm64: dts: qcom: qdru1000: Add gpi_dma nodes
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (14 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 15/19] arm64: dts: qcom: qdru1000: Add additional QUP nodes Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 17/19] arm64: dts: qcom: qdru1000: Add I2C nodes for QUP Melody Olvera
` (3 subsequent siblings)
19 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
GPI DMA is used tof DMA operations for QUP devices, so add the two
gpi_dma instances on the QDU1000 and QRU1000 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 45 ++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 5d3932ad67a1..c105bc15995b 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-qdru1000.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,qdru1000.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -225,6 +226,50 @@ gcc: clock-controller@80000 {
clock-names = "bi_tcxo", "sleep_clk";
};
+ gpi_dma0: dma-controller@900000 {
+ compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma";
+ #dma-cells = <5>;
+ reg = <0x0 0x900000 0x0 0x60000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0x3f>;
+ iommus = <&apps_smmu 0xf6 0x0>;
+ status = "ok";
+ };
+
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,qdu1000-gpi-dma", "qcom,qru1000-gpi-dma";
+ #dma-cells = <5>;
+ reg = <0x0 0xa00000 0x0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0x3f>;
+ iommus = <&apps_smmu 0x116 0x0>;
+ status = "ok";
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x9c0000 0x0 0x2000>;
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 17/19] arm64: dts: qcom: qdru1000: Add I2C nodes for QUP
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (15 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 16/19] arm64: dts: qcom: qdru1000: Add gpi_dma nodes Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 7:30 ` Dmitry Baryshkov
2022-10-01 3:06 ` [PATCH 18/19] arm64: dts: qcom: qdru1000: Add SPI devices to QUP nodes Melody Olvera
` (2 subsequent siblings)
19 siblings, 1 reply; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add I2C nodes to the QUP along with pinconf for these nodes.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 365 +++++++++++++++++++++++++
1 file changed, 365 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index c105bc15995b..40d7cc4c1f3d 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -302,6 +302,132 @@ uart7: serial@99c000 {
#size-cells = <0>;
status = "disabled";
};
+
+ i2c1: i2c@984000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x984000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ dmas = <&gpi_dma0 0 1 3 64 0>,
+ <&gpi_dma0 1 1 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x988000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ dmas = <&gpi_dma0 0 2 3 64 0>,
+ <&gpi_dma0 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@98c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x98c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ dmas = <&gpi_dma0 0 3 3 64 0>,
+ <&gpi_dma0 1 3 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@990000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x990000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ dmas = <&gpi_dma0 0 4 3 64 0>,
+ <&gpi_dma0 1 4 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@994000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x994000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ dmas = <&gpi_dma0 0 5 3 64 0>,
+ <&gpi_dma0 1 5 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@998000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x998000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ dmas = <&gpi_dma0 0 6 3 64 0>,
+ <&gpi_dma0 1 6 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
qupv3_id_1: geniqup@ac0000 {
@@ -316,6 +442,153 @@ qupv3_id_1: geniqup@ac0000 {
ranges;
status = "disabled";
+
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa84000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ dmas = <&gpi_dma1 0 1 3 64 0>,
+ <&gpi_dma1 1 1 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa88000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ dmas = <&gpi_dma1 0 2 3 64 0>,
+ <&gpi_dma1 1 2 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,i2c-geni";
+ reg = <0x0 0xa8c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ dmas = <&gpi_dma1 0 3 3 64 0>,
+ <&gpi_dma1 1 3 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa90000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ dmas = <&gpi_dma1 0 4 3 64 0>,
+ <&gpi_dma1 1 4 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa94000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ dmas = <&gpi_dma1 0 5 3 64 0>,
+ <&gpi_dma1 1 5 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa98000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ dmas = <&gpi_dma1 0 6 3 64 0>,
+ <&gpi_dma1 1 6 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0xa9c000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ dmas = <&gpi_dma1 0 7 3 64 0>,
+ <&gpi_dma1 1 7 3 64 0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
@@ -381,6 +654,98 @@ rx {
bias-disable;
};
};
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk {
+ pins = "gpio10", "gpio11";
+ function = "qup0_se1_l0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk {
+ pins = "gpio12", "gpio13";
+ function = "qup0_se2_l0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk {
+ pins = "gpio14", "gpio15";
+ function = "qup0_se3_l0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk {
+ pins = "gpio16", "gpio17";
+ function = "qup0_se4_l0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk {
+ pins = "gpio130", "gpio131";
+ function = "qup0_se5_l0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk {
+ pins = "gpio132", "gpio133";
+ function = "qup0_se6_l0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk {
+ pins = "gpio22", "gpio23";
+ function = "qup1_se1_l0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk {
+ pins = "gpio24", "gpio25";
+ function = "qup1_se2_l0";
+ drive-strength = <2>;
+ bias-pulll-up;
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk {
+ pins = "gpio26", "gpio27";
+ function = "qup1_se3_l0";
+ drive-strength = <2>;
+ bias-pulll-up;
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk {
+ pins = "gpio28", "gpio29";
+ function = "qup1_se4_l0";
+ drive-strength = <2>;
+ bias-pulll-up;
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk {
+ pins = "gpio30", "gpio31";
+ function = "qup1_se5_l0";
+ drive-strength = <2>;
+ bias-pulll-up;
+ };
+
+ qup_i2c14_data_clk: qup-i2c14-data-clk {
+ pins = "gpio34", "gpio35";
+ function = "qup1_se6_l0";
+ drive-strength = <2>;
+ bias-pulll-up;
+ };
+
+ qup_i2c15_data_clk: qup-i2c15-data-clk {
+ pins = "gpio40", "gpio41";
+ function = "qup1_se7_l0";
+ drive-strength = <2>;
+ bias-pulll-up;
+ };
+
};
pdc: interrupt-controller@b220000 {
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 18/19] arm64: dts: qcom: qdru1000: Add SPI devices to QUP nodes
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (16 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 17/19] arm64: dts: qcom: qdru1000: Add I2C nodes for QUP Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 19/19] arm64: dts: qcom: qdru1000: Add additional UART instances Melody Olvera
2022-10-01 7:32 ` [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Dmitry Baryshkov
19 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add SPI devices to the QUP nodes for the QDU1000 and QRU1000 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 441 +++++++++++++++++++++++++
1 file changed, 441 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 40d7cc4c1f3d..930bb8c8ba5b 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -428,6 +428,132 @@ i2c6: i2c@998000 {
#size-cells = <0>;
status = "disabled";
};
+
+ spi1: spi@984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x984000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ dmas = <&gpi_dma0 0 1 1 64 0>,
+ <&gpi_dma0 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi2: spi@988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x988000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ dmas = <&gpi_dma0 0 2 1 64 0>,
+ <&gpi_dma0 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi3: spi@98c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x98c000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ dmas = <&gpi_dma0 0 3 1 64 0>,
+ <&gpi_dma0 1 3 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi4: spi@990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x990000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ dmas = <&gpi_dma0 0 4 1 64 0>,
+ <&gpi_dma0 1 4 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi5: spi@994000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x994000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ dmas = <&gpi_dma0 0 5 1 64 0>,
+ <&gpi_dma0 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi6: spi@998000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x998000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
+ <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ dmas = <&gpi_dma0 0 6 1 64 0>,
+ <&gpi_dma0 1 6 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
};
qupv3_id_1: geniqup@ac0000 {
@@ -589,6 +715,153 @@ i2c15: i2c@a9c000 {
#size-cells = <0>;
status = "disabled";
};
+
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa84000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ dmas = <&gpi_dma1 0 1 1 64 0>,
+ <&gpi_dma1 1 1 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa88000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ dmas = <&gpi_dma1 0 2 1 64 0>,
+ <&gpi_dma1 1 2 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa8c000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ dmas = <&gpi_dma1 0 3 1 64 0>,
+ <&gpi_dma1 1 3 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa90000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+ dmas = <&gpi_dma1 0 4 1 64 0>,
+ <&gpi_dma1 1 4 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa94000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+ dmas = <&gpi_dma1 0 5 1 64 0>,
+ <&gpi_dma1 1 5 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi14: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa98000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
+ dmas = <&gpi_dma1 0 6 1 64 0>,
+ <&gpi_dma1 1 6 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ spi15: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0xa9c000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ interconnect-names = "qup-core", "qup-config", "qup-memory";
+ interconnects =
+ <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_1 0>,
+ <&system_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ dmas = <&gpi_dma1 0 7 1 64 0>,
+ <&gpi_dma1 1 7 1 64 0>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
};
@@ -746,6 +1019,174 @@ qup_i2c15_data_clk: qup-i2c15-data-clk {
bias-pulll-up;
};
+ qup_spi1_data_clk: qup-spi1-data-clk {
+ pins = "gpio10", "gpio11", "gpio12";
+ function = "qup0_se1_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi1_cs: qup-spi1-cs {
+ pins = "gpio13";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk {
+ pins = "gpio12", "gpio13", "gpio10";
+ function = "qup0_se2_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs {
+ pins = "gpio11";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk {
+ pins = "gpio14", "gpio15", "gpio16";
+ function = "qup0_se3_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi3_cs: qup-spi3-cs {
+ pins = "gpio17";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk {
+ pins = "gpio16", "gpio17", "gpio14";
+ function = "qup0_se4_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi4_cs: qup-spi4-cs {
+ pins = "gpio15";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk {
+ pins = "gpio130", "gpio131", "gpio132";
+ function = "qup0_se5_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs {
+ pins = "gpio133";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk {
+ pins = "gpio132", "gpio133", "gpio130";
+ function = "qup0_se6_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs {
+ pins = "gpio131";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk {
+ pins = "gpio22", "gpio23", "gpio24";
+ function = "qup1_se1_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi9_cs: qup-spi9-cs {
+ pins = "gpio25";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk {
+ pins = "gpio24", "gpio25", "gpio22";
+ function = "qup1_se2_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi10_cs: qup-spi10-cs {
+ pins = "gpio23";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk {
+ pins = "gpio26", "gpio27", "gpio28";
+ function = "qup1_se3_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi11_cs: qup-spi11-cs {
+ pins = "gpio29";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk {
+ pins = "gpio28", "gpio29", "gpio26";
+ function = "qup1_se4_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi12_cs: qup-spi12-cs {
+ pins = "gpio27";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk {
+ pins = "gpio30", "gpio31", "gpio32";
+ function = "qup1_se5_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi13_cs: qup-spi13-cs {
+ pins = "gpio33";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk {
+ pins = "gpio34", "gpio35", "gpio36";
+ function = "qup1_se6_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi14_cs: qup-spi14-cs {
+ pins = "gpio37", "gpio38";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk {
+ pins = "gpio40", "gpio41", "gpio30";
+ function = "qup1_se7_l0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi15_cs: qup-spi15-cs {
+ pins = "gpio31";
+ drive-strength = <6>;
+ bias-disable;
+ };
};
pdc: interrupt-controller@b220000 {
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* [PATCH 19/19] arm64: dts: qcom: qdru1000: Add additional UART instances
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (17 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 18/19] arm64: dts: qcom: qdru1000: Add SPI devices to QUP nodes Melody Olvera
@ 2022-10-01 3:06 ` Melody Olvera
2022-10-01 7:32 ` [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Dmitry Baryshkov
19 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-01 3:06 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Melody Olvera
Add remaining UART instances to the QUP nodes for the QDU1000
and QRU1000 SoCs.
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
---
arch/arm64/boot/dts/qcom/qdru1000.dtsi | 57 +++++++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
index 930bb8c8ba5b..21938e3a613e 100644
--- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
+++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
@@ -290,6 +290,19 @@ qupv3_id_0: geniqup@9c0000 {
ranges;
status = "disabled";
+ uart0: serial@980000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x980000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart0_default>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart7: serial@99c000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x99c000 0x0 0x4000>;
@@ -569,6 +582,33 @@ qupv3_id_1: geniqup@ac0000 {
ranges;
status = "disabled";
+ uart8: serial@a80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0xa80000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart8_default>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart13: serial@a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0xa94000 0x0 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart13_default>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0xa84000 0x0 0x4000>;
@@ -912,7 +952,12 @@ tlmm: pinctrl@f000000 {
gpio-ranges = <&tlmm 0 0 151>;
wakeup-parent = <&pdc>;
- qup_uart7_default: qup-uart7-default {
+ qup_uart0_default: qup-uart0-default {
+ pins = "gpio6", "gpio7", "gpio8", "gpio9";
+ function = "qup0_se0_l0";
+ };
+
+ qup_uart7_default: qup-uart3-default {
tx {
pins = "gpio134";
function = "qup0_se7_l2";
@@ -928,6 +973,16 @@ rx {
};
};
+ qup_uart8_default: qup-uart8-default {
+ pins = "gpio18", "gpio19", "gpio20", "gpio21";
+ function = "qup1_se0_l0";
+ };
+
+ qup_uart13_default: qup-uart13-default {
+ pins = "gpio30", "gpio31", "gpio32", "gpio33";
+ function = "qup1_se5_l0";
+ };
+
qup_i2c1_data_clk: qup-i2c1-data-clk {
pins = "gpio10", "gpio11";
function = "qup0_se1_l0";
--
2.37.3
^ permalink raw reply related [flat|nested] 46+ messages in thread
* Re: [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-01 3:06 ` [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
@ 2022-10-01 7:22 ` Dmitry Baryshkov
2022-10-11 18:21 ` Melody Olvera
2022-10-01 9:12 ` Krzysztof Kozlowski
1 sibling, 1 reply; 46+ messages in thread
From: Dmitry Baryshkov @ 2022-10-01 7:22 UTC (permalink / raw)
To: Melody Olvera
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
linux-arm-msm, devicetree, linux-kernel
On Sat, 1 Oct 2022 at 06:09, Melody Olvera <quic_molvera@quicinc.com> wrote:
>
> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
> descriptions of CPUs, GCC, RPMHCC, UART, and interrupt-controller to
> boot to shell with console on these SoCs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 370 +++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 +
> arch/arm64/boot/dts/qcom/qru1000.dtsi | 10 +
> 3 files changed, 390 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> new file mode 100644
> index 000000000000..3610f94bef35
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -0,0 +1,370 @@
> +// SPDX-License-Identifier: BSD-3-Clause-Clear
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-qdru1000.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen: chosen { };
> +
> +
> + clocks {
> + xo_board: xo_board {
No underscores in node names. Use dash instead. Nobody should be
binding these clocks via the system name, so it should not matter.
> + compatible = "fixed-clock";
> + clock-frequency = <19200000>;
> + clock-output-names = "xo_board";
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + power-domain-names = "psci";
> + power-domains = <&CPU_PD0>;
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
> + compatible = "cache";
> + };
> + };
> + };
> +
> + CPU1: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD1>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_100>;
> + L2_100: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> +
> + };
> +
> + CPU2: cpu@200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0 0x200>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD2>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_200>;
> + L2_200: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> + };
> +
> + CPU3: cpu@300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a55";
> + reg = <0x0 0x300>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD3>;
> + power-domain-names = "psci";
> + next-level-cache = <&L2_300>;
> + L2_300: l2-cache {
> + compatible = "cache";
> + next-level-cache = <&L3_0>;
> + };
> +
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> + };
> + };
> + };
> +
> + idle-states {
> + entry-method = "psci";
> +
> + SILVER_OFF: silver-c4 { /* C4 */
If this is silver, where is gold?
With the lack of gold/silver distinction, it might be better to just
use CPU/cpu here instead of silver.
> + compatible = "arm,idle-state";
> + idle-state-name = "rail-pc";
> + entry-latency-us = <274>;
> + exit-latency-us = <480>;
> + min-residency-us = <3934>;
> + arm,psci-suspend-param = <0x40000004>;
> + local-timer-stop;
> + };
> +
> + CLUSTER_PWR_DN: cluster-d4 { /* D4 */
domain idle states go to separate domain-idle-states node.
> + compatible = "domain-idle-state";
> + idle-state-name = "l3-off";
> + entry-latency-us = <584>;
> + exit-latency-us = <2332>;
> + min-residency-us = <6118>;
> + arm,psci-suspend-param = <0x41000044>;
> + };
> +
> + APSS_OFF: cluster-e3 { /* E3 */
> + compatible = "domain-idle-state";
> + idle-state-name = "llcc-off";
> + entry-latency-us = <2893>;
> + exit-latency-us = <4023>;
> + min-residency-us = <9987>;
> + arm,psci-suspend-param = <0x41003344>;
> + };
> + };
> +
> + firmware {
> + qcom_scm {
> + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm";
> + #reset-cells = <1>;
> + };
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + /* We expect the bootloader to fill in the size */
> + reg = <0x0 0x80000000 0x0 0x0>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> +
> + CPU_PD0: cpu-pd0 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&SILVER_OFF>;
> + };
> +
> + CPU_PD1: cpu-pd1 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&SILVER_OFF>;
> + };
> +
> + CPU_PD2: cpu-pd2 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&SILVER_OFF>;
> + };
> +
> + CPU_PD3: cpu-pd3 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&SILVER_OFF>;
> + };
> +
> + CLUSTER_PD: cluster-pd {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
> + };
> + };
> +
> + soc: soc@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@80000 {
> + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon";
> + reg = <0x0 0x80000 0x0 0x1f4200>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
> + clock-names = "bi_tcxo", "sleep_clk";
> + };
> +
> + qupv3_id_0: geniqup@9c0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0x0 0x9c0000 0x0 0x2000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + uart7: serial@99c000 {
> + compatible = "qcom,geni-debug-uart";
> + reg = <0x0 0x99c000 0x0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + };
> +
> + tcsr_mutex: hwlock@1f40000 {
> + compatible = "qcom,tcsr-mutex";
> + reg = <0x0 0x1f40000 0x0 0x20000>;
> + #hwlock-cells = <1>;
> + };
> +
> + pdc: interrupt-controller@b220000 {
> + compatible = "qcom,pdc";
> + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
> + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg";
> + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
> + <94 609 31>, <125 63 1>;
> + #interrupt-cells = <2>;
> + interrupt-parent = <&intc>;
> + interrupt-controller;
> + };
Sort the devices according to the address please.
> +
> + intc: interrupt-controller@17200000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + #redistributor-regions = <1>;
> + redistributor-stride = <0x0 0x20000>;
> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
> + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + timer@17420000 {
> + compatible = "arm,armv7-timer-mem";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + reg = <0x0 0x17420000 0x0 0x1000>;
> + clock-frequency = <19200000>;
> +
> + frame@17421000 {
> + frame-number = <0>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x17421000 0x0 0x1000>,
> + <0x0 0x17422000 0x0 0x1000>;
> + };
> +
> + frame@17423000 {
> + frame-number = <1>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x17423000 0x0 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17425000 {
> + frame-number = <2>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x17425000 0x0 0x1000>,
> + <0x0 0x17426000 0x0 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17427000 {
> + frame-number = <3>;
> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x17427000 0x0 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@17429000 {
> + frame-number = <4>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x17429000 0x0 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@1742b000 {
> + frame-number = <5>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x1742b000 0x0 0x1000>;
> + status = "disabled";
> + };
> +
> + frame@1742d000 {
> + frame-number = <6>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + reg = <0x0 0x1742d000 0x0 0x1000>;
> + status = "disabled";
> + };
> + };
> +
> + apps_rsc: rsc@17a00000 {
> + label = "apps_rsc";
> + compatible = "qcom,rpmh-rsc";
> + reg = <0x0 0x17a00000 0x0 0x10000>,
> + <0x0 0x17a10000 0x0 0x10000>,
> + <0x0 0x17a20000 0x0 0x10000>;
> + reg-names = "drv-0", "drv-1", "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
> + <WAKE_TCS 3>, <CONTROL_TCS 0>;
> +
> + apps_bcm_voter: bcm_voter {
> + compatible = "qcom,bcm-voter";
> + };
> +
> + rpmhcc: clock-controller {
> + compatible = "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk";
> + #clock-cells = <1>;
> + clock-names = "xo";
> + clocks = <&xo_board>;
> + };
> + };
> +
> + arch_timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <19200000>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> new file mode 100644
> index 000000000000..ba195e7ffc38
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: BSD-3-Clause-Clear
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include "qdru1000.dtsi"
> +
> +/ {
> + qcom,msm-id = <545 0x10000>, <587 0x10000>;
Ugh. If this is the only difference between chips, I'd suggest merging
qdru1000 in one of the includes and then overriding msm-id in the
second one.
> +};
> diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi
> new file mode 100644
> index 000000000000..1639a4b3c1fb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: BSD-3-Clause-Clear
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include "qdru1000.dtsi"
> +
> +/ {
> + qcom,msm-id = <539 0x10000>, <588 0x10000>, <589 0x10000>, <590 0x10000>;
> +};
> --
> 2.37.3
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 06/19] arm64: dts: qcom: qdru1000: Add smmu nodes
2022-10-01 3:06 ` [PATCH 06/19] arm64: dts: qcom: qdru1000: Add smmu nodes Melody Olvera
@ 2022-10-01 7:23 ` Dmitry Baryshkov
0 siblings, 0 replies; 46+ messages in thread
From: Dmitry Baryshkov @ 2022-10-01 7:23 UTC (permalink / raw)
To: Melody Olvera
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
linux-arm-msm, devicetree, linux-kernel
On Sat, 1 Oct 2022 at 06:09, Melody Olvera <quic_molvera@quicinc.com> wrote:
>
> Add smmu nodes for the QDU1000 and QRU1000 SoCs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 57 ++++++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> index 39b9a00d3ad8..8c2af08b8329 100644
> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -396,5 +396,62 @@ arch_timer: timer {
> <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> clock-frequency = <19200000>;
> };
> +
> + apps_smmu: apps-smmu@15000000 {
Please insert the node according to its address.
> + compatible = "qcom,qdu1000-smmu-500", "qcom,qru1000-smmu-500",
> + "arm,mmu-500";
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes
2022-10-01 3:06 ` [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes Melody Olvera
@ 2022-10-01 7:26 ` Dmitry Baryshkov
2022-10-11 18:40 ` Melody Olvera
2022-10-01 9:14 ` Krzysztof Kozlowski
1 sibling, 1 reply; 46+ messages in thread
From: Dmitry Baryshkov @ 2022-10-01 7:26 UTC (permalink / raw)
To: Melody Olvera
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
linux-arm-msm, devicetree, linux-kernel
On Sat, 1 Oct 2022 at 06:09, Melody Olvera <quic_molvera@quicinc.com> wrote:
>
> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
> configuration.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> index 3610f94bef35..39b9a00d3ad8 100644
> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -235,6 +235,8 @@ uart7: serial@99c000 {
> reg = <0x0 0x99c000 0x0 0x4000>;
> clock-names = "se";
> clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart7_default>;
> interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
> #hwlock-cells = <1>;
> };
>
> + tlmm: pinctrl@f000000 {
> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
> + reg = <0x0 0xf000000 0x0 0x1000000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 151>;
> + wakeup-parent = <&pdc>;
> +
> + qup_uart7_default: qup-uart7-default {
> + tx {
> + pins = "gpio134";
> + function = "qup0_se7_l2";
This looks strange. Usually we'd have a single 'qup7' function here.
I'd go back to the interconnect driver. Maybe the functions are not
correctly defined there.
> + drive-strength = <2>;
> + bias-disable;
'drive-strength' and 'bias-disable' are to be patched in in the board dts file.
> + };
> +
> + rx {
> + pins = "gpio135";
> + function = "qup0_se7_l3";
> + drive-strength = <2>;
> + bias-disable;
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,pdc";
> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
> --
> 2.37.3
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
2022-10-01 3:06 ` [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera
@ 2022-10-01 7:28 ` Dmitry Baryshkov
2022-10-11 18:29 ` Melody Olvera
2022-10-01 9:12 ` Krzysztof Kozlowski
1 sibling, 1 reply; 46+ messages in thread
From: Dmitry Baryshkov @ 2022-10-01 7:28 UTC (permalink / raw)
To: Melody Olvera
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
linux-arm-msm, devicetree, linux-kernel
On Sat, 1 Oct 2022 at 06:09, Melody Olvera <quic_molvera@quicinc.com> wrote:
>
> Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000
> SoCs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 2 ++
> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 30 ++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 30 ++++++++++++++++++++++++
> 3 files changed, 62 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 1d86a33de528..398920c530b0 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -152,3 +152,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
These two lines stand out. Please fix the indentation and move them to
the proper place.
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> new file mode 100644
> index 000000000000..0ecf9a7c41ec
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: BSD-3-Clause-Clear
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "qdu1000.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. QDU1000 IDP";
> + compatible = "qcom,qdu1000-idp", "qcom,qdu1000";
> + qcom,board-id = <0x22 0x0>;
> +
> + aliases {
> + serial0 = &uart7;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&uart7 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
> new file mode 100644
> index 000000000000..ddb4ea17f7d2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: BSD-3-Clause-Clear
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "qru1000.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. QRU1000 IDP";
> + compatible = "qcom,qru1000-idp", "qcom,qru1000";
> + qcom,board-id = <0x22 0x0>;
> +
> + aliases {
> + serial0 = &uart7;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&uart7 {
> + status = "okay";
> +};
> --
> 2.37.3
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 17/19] arm64: dts: qcom: qdru1000: Add I2C nodes for QUP
2022-10-01 3:06 ` [PATCH 17/19] arm64: dts: qcom: qdru1000: Add I2C nodes for QUP Melody Olvera
@ 2022-10-01 7:30 ` Dmitry Baryshkov
0 siblings, 0 replies; 46+ messages in thread
From: Dmitry Baryshkov @ 2022-10-01 7:30 UTC (permalink / raw)
To: Melody Olvera
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
linux-arm-msm, devicetree, linux-kernel
On Sat, 1 Oct 2022 at 06:09, Melody Olvera <quic_molvera@quicinc.com> wrote:
>
> Add I2C nodes to the QUP along with pinconf for these nodes.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 365 +++++++++++++++++++++++++
> 1 file changed, 365 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> index c105bc15995b..40d7cc4c1f3d 100644
> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -302,6 +302,132 @@ uart7: serial@99c000 {
> #size-cells = <0>;
> status = "disabled";
> };
> +
> + i2c1: i2c@984000 {
Sort according to the address.
> + compatible = "qcom,geni-i2c";
> + reg = <0x0 0x984000 0x0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
> + interconnect-names = "qup-core", "qup-config", "qup-memory";
> + interconnects =
> + <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_QUP_0 0>,
> + <&system_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_i2c1_data_clk>;
> + dmas = <&gpi_dma0 0 1 3 64 0>,
> + <&gpi_dma0 1 1 3 64 0>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> @@ -381,6 +654,98 @@ rx {
> bias-disable;
> };
> };
> +
> + qup_i2c1_data_clk: qup-i2c1-data-clk {
> + pins = "gpio10", "gpio11";
> + function = "qup0_se1_l0";
> + drive-strength = <2>;
> + bias-pull-up;
No 'drive-strength' and 'bias-pull-up' here please.
> + };
> +
> + qup_i2c2_data_clk: qup-i2c2-data-clk {
> + pins = "gpio12", "gpio13";
> + function = "qup0_se2_l0";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c3_data_clk: qup-i2c3-data-clk {
> + pins = "gpio14", "gpio15";
> + function = "qup0_se3_l0";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c4_data_clk: qup-i2c4-data-clk {
> + pins = "gpio16", "gpio17";
> + function = "qup0_se4_l0";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c5_data_clk: qup-i2c5-data-clk {
> + pins = "gpio130", "gpio131";
> + function = "qup0_se5_l0";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c6_data_clk: qup-i2c6-data-clk {
> + pins = "gpio132", "gpio133";
> + function = "qup0_se6_l0";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c9_data_clk: qup-i2c9-data-clk {
> + pins = "gpio22", "gpio23";
> + function = "qup1_se1_l0";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + qup_i2c10_data_clk: qup-i2c10-data-clk {
> + pins = "gpio24", "gpio25";
> + function = "qup1_se2_l0";
> + drive-strength = <2>;
> + bias-pulll-up;
> + };
> +
> + qup_i2c11_data_clk: qup-i2c11-data-clk {
> + pins = "gpio26", "gpio27";
> + function = "qup1_se3_l0";
> + drive-strength = <2>;
> + bias-pulll-up;
> + };
> +
> + qup_i2c12_data_clk: qup-i2c12-data-clk {
> + pins = "gpio28", "gpio29";
> + function = "qup1_se4_l0";
> + drive-strength = <2>;
> + bias-pulll-up;
> + };
> +
> + qup_i2c13_data_clk: qup-i2c13-data-clk {
> + pins = "gpio30", "gpio31";
> + function = "qup1_se5_l0";
> + drive-strength = <2>;
> + bias-pulll-up;
> + };
> +
> + qup_i2c14_data_clk: qup-i2c14-data-clk {
> + pins = "gpio34", "gpio35";
> + function = "qup1_se6_l0";
> + drive-strength = <2>;
> + bias-pulll-up;
> + };
> +
> + qup_i2c15_data_clk: qup-i2c15-data-clk {
> + pins = "gpio40", "gpio41";
> + function = "qup1_se7_l0";
> + drive-strength = <2>;
> + bias-pulll-up;
> + };
> +
> };
>
> pdc: interrupt-controller@b220000 {
> --
> 2.37.3
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 00/19] Add base device tree files for QDU1000/QRU1000
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
` (18 preceding siblings ...)
2022-10-01 3:06 ` [PATCH 19/19] arm64: dts: qcom: qdru1000: Add additional UART instances Melody Olvera
@ 2022-10-01 7:32 ` Dmitry Baryshkov
19 siblings, 0 replies; 46+ messages in thread
From: Dmitry Baryshkov @ 2022-10-01 7:32 UTC (permalink / raw)
To: Melody Olvera
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
linux-arm-msm, devicetree, linux-kernel
On Sat, 1 Oct 2022 at 06:09, Melody Olvera <quic_molvera@quicinc.com> wrote:
>
> This series adds the base device tree files and DTS support for the
> Qualcomm QDU1000 and QRU1000 IDP SoCs, including the clocks, tlmm, smmu,
> regulators, mmc, interconnects, cpufreq, and qup.
>
> This patchset is based off of [1] which adds support for the PMIC arb used
> on these SoCs.
>
> The Qualcomm Technologies, Inc. Distributed Unit 1000 and Radio Unit
> 1000 are new SoCs meant for enabling Open RAN solutions. See more at
> https://www.qualcomm.com/content/dam/qcomm-martech/dm-assets/documents/qualcomm_5g_ran_platforms_product_brief.pdf
>
> [1] https://lore.kernel.org/all/20220914165212.3705892-3-vkoul@kernel.org/
>
> Melody Olvera (19):
> arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
> arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
No need to split IDT commits too much. Splitting the main DT is fine
for me, it eases review. For IDT, I'd just squash them together.
> arm64: dts: qcom: qdru1000: Add tlmm nodes
> arm64: dts: qcom: qdu1000: Add reserved memory nodes
> arm64: dts: qcom: qru1000: Add reserved memory nodes
> arm64: dts: qcom: qdru1000: Add smmu nodes
> arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes
> arm64: dts: qcom: qru1000-idp: Add RPMH regulators nodes
> arm64: dts: qcom: qdru1000: Add interconnect nodes
> arm64: dts: qcom: qdru1000: Add rpmhpd node
> arm64: dts: qcom: qdru1000: Add spmi node
> arm64: dts: qcom: qdu1000-idp: Include pmic file
> arm64: dts: qcom: qru1000-idp: Include pmic file
> arm64: dts: qcom: qdru1000: Add cpufreq support
> arm64: dts: qcom: qdru1000: Add additional QUP nodes
> arm64: dts: qcom: qdru1000: Add gpi_dma nodes
> arm64: dts: qcom: qdru1000: Add I2C nodes for QUP
> arm64: dts: qcom: qdru1000: Add SPI devices to QUP nodes
> arm64: dts: qcom: qdru1000: Add additional UART instances
>
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 1499 ++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 231 ++++
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 160 +++
> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 231 ++++
> arch/arm64/boot/dts/qcom/qru1000.dtsi | 155 +++
> 6 files changed, 2278 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>
>
> base-commit: 987a926c1d8a40e4256953b04771fbdb63bc7938
> prerequisite-patch-id: 79eb132c9ff1a0feb653bef87e3e93f6841f81ee
> prerequisite-patch-id: e25ad91d89a9d4a24f1081e5c03cb20678c6e94b
> prerequisite-patch-id: e882ee6dbd8d55069a313e9c2b10a1ea7f6b80fb
> prerequisite-patch-id: 85c1f1845b2e69ef50e7e8391426e6cab6c66381
> prerequisite-patch-id: 5fd7e4f92a95a7dedc49fd39fdffd5e02c838190
> prerequisite-patch-id: c8d9475d6bb2d24102e5bfee65f74d2c0365db68
> prerequisite-patch-id: a03c3288ed927cbab6a42d3ad49df4347cfc9722
> prerequisite-patch-id: aa7ddf85d2a1c02e4d649632425910e44f73a567
> prerequisite-patch-id: 5e7a02607aecd3f5346a2f450982601cf6935e54
> --
> 2.37.3
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-01 3:06 ` [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
2022-10-01 7:22 ` Dmitry Baryshkov
@ 2022-10-01 9:12 ` Krzysztof Kozlowski
2022-10-11 18:22 ` Melody Olvera
1 sibling, 1 reply; 46+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-01 9:12 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 01/10/2022 05:06, Melody Olvera wrote:
> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
> descriptions of CPUs, GCC, RPMHCC, UART, and interrupt-controller to
> boot to shell with console on these SoCs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 370 +++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 +
> arch/arm64/boot/dts/qcom/qru1000.dtsi | 10 +
> 3 files changed, 390 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> new file mode 100644
> index 000000000000..3610f94bef35
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -0,0 +1,370 @@
> +// SPDX-License-Identifier: BSD-3-Clause-Clear
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-qdru1000.h>
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen: chosen { };
> +
> +
No need for double blank line.
> + clocks {
> + xo_board: xo_board {
> + compatible = "fixed-clock";
> + clock-frequency = <19200000>;
> + clock-output-names = "xo_board";
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep_clk {
> + compatible = "fixed-clock";
> + clock-frequency = <32000>;
> + #clock-cells = <0>;
> + };
> + };
> +
(...)
> + CPU_PD3: cpu-pd3 {
> + #power-domain-cells = <0>;
> + power-domains = <&CLUSTER_PD>;
> + domain-idle-states = <&SILVER_OFF>;
> + };
> +
> + CLUSTER_PD: cluster-pd {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
> + };
> + };
> +
> + soc: soc@0 {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0 0x10 0>;
> + dma-ranges = <0 0 0 0 0x10 0>;
> + compatible = "simple-bus";
> +
> + gcc: clock-controller@80000 {
> + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon";
Did you document the compatibles?
> + reg = <0x0 0x80000 0x0 0x1f4200>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
> + clock-names = "bi_tcxo", "sleep_clk";
> + };
> +
> + qupv3_id_0: geniqup@9c0000 {
> + compatible = "qcom,geni-se-qup";
> + reg = <0x0 0x9c0000 0x0 0x2000>;
> + clock-names = "m-ahb", "s-ahb";
> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + status = "disabled";
> +
> + uart7: serial@99c000 {
> + compatible = "qcom,geni-debug-uart";
> + reg = <0x0 0x99c000 0x0 0x4000>;
> + clock-names = "se";
> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> + };
> +
(...)
> + arch_timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <19200000>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> new file mode 100644
> index 000000000000..ba195e7ffc38
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: BSD-3-Clause-Clear
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include "qdru1000.dtsi"
> +
> +/ {
> + qcom,msm-id = <545 0x10000>, <587 0x10000>;
NAK.
> +};
> diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi
> new file mode 100644
> index 000000000000..1639a4b3c1fb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi
> @@ -0,0 +1,10 @@
> +// SPDX-License-Identifier: BSD-3-Clause-Clear
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include "qdru1000.dtsi"
> +
> +/ {
> + qcom,msm-id = <539 0x10000>, <588 0x10000>, <589 0x10000>, <590 0x10000>;
Nope, property is not documented and not accepted. Efforts in
documenting this property were apparently also not accepted, therefore I
am not agreeing in bringing DTS with these.
> +};
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
2022-10-01 3:06 ` [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera
2022-10-01 7:28 ` Dmitry Baryshkov
@ 2022-10-01 9:12 ` Krzysztof Kozlowski
2022-10-11 18:31 ` Melody Olvera
1 sibling, 1 reply; 46+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-01 9:12 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 01/10/2022 05:06, Melody Olvera wrote:
> Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000
> SoCs.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 2 ++
> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 30 ++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 30 ++++++++++++++++++++++++
> 3 files changed, 62 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 1d86a33de528..398920c530b0 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -152,3 +152,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
List is ordered by name.
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> new file mode 100644
> index 000000000000..0ecf9a7c41ec
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: BSD-3-Clause-Clear
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "qdu1000.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. QDU1000 IDP";
> + compatible = "qcom,qdu1000-idp", "qcom,qdu1000";
Undocumented compatibles. You need bindings for these.
> + qcom,board-id = <0x22 0x0>;
> +
> + aliases {
> + serial0 = &uart7;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&qupv3_id_0 {
> + status = "okay";
> +};
> +
> +&uart7 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
> new file mode 100644
> index 000000000000..ddb4ea17f7d2
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: BSD-3-Clause-Clear
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "qru1000.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. QRU1000 IDP";
> + compatible = "qcom,qru1000-idp", "qcom,qru1000";
Same problem.
> + qcom,board-id = <0x22 0x0>;
Undocumented compatible. Drop it.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes
2022-10-01 3:06 ` [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes Melody Olvera
2022-10-01 7:26 ` Dmitry Baryshkov
@ 2022-10-01 9:14 ` Krzysztof Kozlowski
2022-10-11 18:48 ` Melody Olvera
1 sibling, 1 reply; 46+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-01 9:14 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 01/10/2022 05:06, Melody Olvera wrote:
> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
> configuration.
The patchset should be squashed with previous. There is no point in
bringing support piece by piece. You can bring support in steps if you
submissions are separate in time. But if you have everything ready -
your patch must be complete and bisectable.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> index 3610f94bef35..39b9a00d3ad8 100644
> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -235,6 +235,8 @@ uart7: serial@99c000 {
> reg = <0x0 0x99c000 0x0 0x4000>;
> clock-names = "se";
> clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&qup_uart7_default>;
> interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
> #hwlock-cells = <1>;
> };
>
> + tlmm: pinctrl@f000000 {
> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
> + reg = <0x0 0xf000000 0x0 0x1000000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + gpio-ranges = <&tlmm 0 0 151>;
> + wakeup-parent = <&pdc>;
> +
> + qup_uart7_default: qup-uart7-default {
Suffix "-state"
> + tx {
Suffix "-pins"
> + pins = "gpio134";
> + function = "qup0_se7_l2";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + rx {
Suffix "-pins"
> + pins = "gpio135";
> + function = "qup0_se7_l3";
> + drive-strength = <2>;
> + bias-disable;
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,pdc";
> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 04/19] arm64: dts: qcom: qdu1000: Add reserved memory nodes
2022-10-01 3:06 ` [PATCH 04/19] arm64: dts: qcom: qdu1000: Add reserved memory nodes Melody Olvera
@ 2022-10-01 9:14 ` Krzysztof Kozlowski
0 siblings, 0 replies; 46+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-01 9:14 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 01/10/2022 05:06, Melody Olvera wrote:
> Add reserved memory nodes for QDU1000 SoCs based on downstream
> documentation.
Patch on its own does not make any sense.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 07/19] arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes
2022-10-01 3:06 ` [PATCH 07/19] arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes Melody Olvera
@ 2022-10-01 9:15 ` Krzysztof Kozlowski
2022-10-11 21:08 ` Melody Olvera
0 siblings, 1 reply; 46+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-01 9:15 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 01/10/2022 05:06, Melody Olvera wrote:
> Add RPMH regulators for the QDU1000 IDP platform.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 200 +++++++++++++++++++++++
> 1 file changed, 200 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> index 0ecf9a7c41ec..654b50220c2e 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
> @@ -5,6 +5,7 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> #include "qdu1000.dtsi"
>
> / {
> @@ -19,6 +20,205 @@ aliases {
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + ppvar_sys: ppvar-sys-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "ppvar_sys";
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&ppvar_sys>;
> + };
> +};
> +
> +&apps_rsc {
> + pm8150-rpmh-regulators {
regulators
> + compatible = "qcom,pm8150-rpmh-regulators";
> + qcom,pmic-id = "a";
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 08/19] arm64: dts: qcom: qru1000-idp: Add RPMH regulators nodes
2022-10-01 3:06 ` [PATCH 08/19] arm64: dts: qcom: qru1000-idp: " Melody Olvera
@ 2022-10-01 9:15 ` Krzysztof Kozlowski
2022-10-11 21:08 ` Melody Olvera
0 siblings, 1 reply; 46+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-01 9:15 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 01/10/2022 05:06, Melody Olvera wrote:
> Add RPMH regulators for the QRU1000 IDP platform.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 200 +++++++++++++++++++++++
> 1 file changed, 200 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
> index ddb4ea17f7d2..8d27923dc470 100644
> --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
> @@ -5,6 +5,7 @@
>
> /dts-v1/;
>
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> #include "qru1000.dtsi"
>
> / {
> @@ -19,6 +20,205 @@ aliases {
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + ppvar_sys: ppvar-sys-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "ppvar_sys";
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&ppvar_sys>;
> + };
> +};
> +
> +&apps_rsc {
> + pm8150-rpmh-regulators {
regulators
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 09/19] arm64: dts: qcom: qdru1000: Add interconnect nodes
2022-10-01 3:06 ` [PATCH 09/19] arm64: dts: qcom: qdru1000: Add interconnect nodes Melody Olvera
@ 2022-10-01 9:16 ` Krzysztof Kozlowski
0 siblings, 0 replies; 46+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-01 9:16 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 01/10/2022 05:06, Melody Olvera wrote:
> Add interconnect nodes for the QDU1000 and QRU1000 platforms.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 27 ++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> index 8c2af08b8329..b85ffd8baf4b 100644
> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
> @@ -6,6 +6,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/clock/qcom,gcc-qdru1000.h>
> #include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/interconnect/qcom,qdru1000.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>
> / {
> @@ -453,5 +454,31 @@ apps_smmu: apps-smmu@15000000 {
> <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
> };
> +
> + clk_virt: interconnect-0 {
> + compatible = "qcom,qdu1000-clk-virt", "qcom,qru1000-clk-virt";
> + #interconnect-cells = <2>;
> + qcom,bcm-voters = <&apps_bcm_voter>;
> + };
> +
> + mc_virt: interconnect-1{
Missing space.
Patchset should be squashed with initial submission. Splitting it does
not make sense in initial work.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 12/19] arm64: dts: qcom: qdu1000-idp: Include pmic file
2022-10-01 3:06 ` [PATCH 12/19] arm64: dts: qcom: qdu1000-idp: Include pmic file Melody Olvera
@ 2022-10-01 9:16 ` Krzysztof Kozlowski
0 siblings, 0 replies; 46+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-01 9:16 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 01/10/2022 05:06, Melody Olvera wrote:
> Include the pmic file for the QDU1000 IDP platform.
>
> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 1 +
No, this must be squashed and on its own does not make any sense.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-01 7:22 ` Dmitry Baryshkov
@ 2022-10-11 18:21 ` Melody Olvera
0 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-11 18:21 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
linux-arm-msm, devicetree, linux-kernel
On 10/1/2022 12:22 AM, Dmitry Baryshkov wrote:
> On Sat, 1 Oct 2022 at 06:09, Melody Olvera <quic_molvera@quicinc.com> wrote:
>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>> descriptions of CPUs, GCC, RPMHCC, UART, and interrupt-controller to
>> boot to shell with console on these SoCs.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 370 +++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 +
>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 10 +
>> 3 files changed, 390 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> new file mode 100644
>> index 000000000000..3610f94bef35
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> @@ -0,0 +1,370 @@
>> +// SPDX-License-Identifier: BSD-3-Clause-Clear
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-qdru1000.h>
>> +#include <dt-bindings/clock/qcom,rpmh.h>
>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen: chosen { };
>> +
>> +
>> + clocks {
>> + xo_board: xo_board {
> No underscores in node names. Use dash instead. Nobody should be
> binding these clocks via the system name, so it should not matter.
Got it.
>
>> + compatible = "fixed-clock";
>> + clock-frequency = <19200000>;
>> + clock-output-names = "xo_board";
>> + #clock-cells = <0>;
>> + };
>> +
>> + sleep_clk: sleep_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <32000>;
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> +
>> + CPU0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a55";
>> + reg = <0x0 0x0>;
>> + enable-method = "psci";
>> + power-domain-names = "psci";
>> + power-domains = <&CPU_PD0>;
>> + next-level-cache = <&L2_0>;
>> + L2_0: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + L3_0: l3-cache {
>> + compatible = "cache";
>> + };
>> + };
>> + };
>> +
>> + CPU1: cpu@100 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a55";
>> + reg = <0x0 0x100>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD1>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_100>;
>> + L2_100: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + };
>> +
>> + };
>> +
>> + CPU2: cpu@200 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a55";
>> + reg = <0x0 0x200>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD2>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_200>;
>> + L2_200: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + };
>> + };
>> +
>> + CPU3: cpu@300 {
>> + device_type = "cpu";
>> + compatible = "arm,cortex-a55";
>> + reg = <0x0 0x300>;
>> + enable-method = "psci";
>> + power-domains = <&CPU_PD3>;
>> + power-domain-names = "psci";
>> + next-level-cache = <&L2_300>;
>> + L2_300: l2-cache {
>> + compatible = "cache";
>> + next-level-cache = <&L3_0>;
>> + };
>> +
>> + };
>> +
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&CPU0>;
>> + };
>> +
>> + core1 {
>> + cpu = <&CPU1>;
>> + };
>> +
>> + core2 {
>> + cpu = <&CPU2>;
>> + };
>> +
>> + core3 {
>> + cpu = <&CPU3>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + idle-states {
>> + entry-method = "psci";
>> +
>> + SILVER_OFF: silver-c4 { /* C4 */
> If this is silver, where is gold?
> With the lack of gold/silver distinction, it might be better to just
> use CPU/cpu here instead of silver.
Sure thing.
>
>> + compatible = "arm,idle-state";
>> + idle-state-name = "rail-pc";
>> + entry-latency-us = <274>;
>> + exit-latency-us = <480>;
>> + min-residency-us = <3934>;
>> + arm,psci-suspend-param = <0x40000004>;
>> + local-timer-stop;
>> + };
>> +
>> + CLUSTER_PWR_DN: cluster-d4 { /* D4 */
> domain idle states go to separate domain-idle-states node.
>
>> + compatible = "domain-idle-state";
>> + idle-state-name = "l3-off";
>> + entry-latency-us = <584>;
>> + exit-latency-us = <2332>;
>> + min-residency-us = <6118>;
>> + arm,psci-suspend-param = <0x41000044>;
>> + };
>> +
>> + APSS_OFF: cluster-e3 { /* E3 */
>> + compatible = "domain-idle-state";
>> + idle-state-name = "llcc-off";
>> + entry-latency-us = <2893>;
>> + exit-latency-us = <4023>;
>> + min-residency-us = <9987>;
>> + arm,psci-suspend-param = <0x41003344>;
>> + };
>> + };
>> +
>> + firmware {
>> + qcom_scm {
>> + compatible = "qcom,scm-qdu100", "qcom.scm-qru1000", "qcom,scm";
>> + #reset-cells = <1>;
>> + };
>> + };
>> +
>> + memory@80000000 {
>> + device_type = "memory";
>> + /* We expect the bootloader to fill in the size */
>> + reg = <0x0 0x80000000 0x0 0x0>;
>> + };
>> +
>> + pmu {
>> + compatible = "arm,armv8-pmuv3";
>> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + psci {
>> + compatible = "arm,psci-1.0";
>> + method = "smc";
>> +
>> + CPU_PD0: cpu-pd0 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&SILVER_OFF>;
>> + };
>> +
>> + CPU_PD1: cpu-pd1 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&SILVER_OFF>;
>> + };
>> +
>> + CPU_PD2: cpu-pd2 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&SILVER_OFF>;
>> + };
>> +
>> + CPU_PD3: cpu-pd3 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&SILVER_OFF>;
>> + };
>> +
>> + CLUSTER_PD: cluster-pd {
>> + #power-domain-cells = <0>;
>> + domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
>> + };
>> + };
>> +
>> + soc: soc@0 {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0 0 0 0x10 0>;
>> + dma-ranges = <0 0 0 0 0x10 0>;
>> + compatible = "simple-bus";
>> +
>> + gcc: clock-controller@80000 {
>> + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon";
>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>> + clock-names = "bi_tcxo", "sleep_clk";
>> + };
>> +
>> + qupv3_id_0: geniqup@9c0000 {
>> + compatible = "qcom,geni-se-qup";
>> + reg = <0x0 0x9c0000 0x0 0x2000>;
>> + clock-names = "m-ahb", "s-ahb";
>> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
>> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + status = "disabled";
>> +
>> + uart7: serial@99c000 {
>> + compatible = "qcom,geni-debug-uart";
>> + reg = <0x0 0x99c000 0x0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>> + };
>> +
>> + tcsr_mutex: hwlock@1f40000 {
>> + compatible = "qcom,tcsr-mutex";
>> + reg = <0x0 0x1f40000 0x0 0x20000>;
>> + #hwlock-cells = <1>;
>> + };
>> +
>> + pdc: interrupt-controller@b220000 {
>> + compatible = "qcom,pdc";
>> + reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
>> + reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg";
>> + qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
>> + <94 609 31>, <125 63 1>;
>> + #interrupt-cells = <2>;
>> + interrupt-parent = <&intc>;
>> + interrupt-controller;
>> + };
> Sort the devices according to the address please.
Will do.
>
>> +
>> + intc: interrupt-controller@17200000 {
>> + compatible = "arm,gic-v3";
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + #redistributor-regions = <1>;
>> + redistributor-stride = <0x0 0x20000>;
>> + reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */
>> + <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
>> + };
>> +
>> + timer@17420000 {
>> + compatible = "arm,armv7-timer-mem";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + reg = <0x0 0x17420000 0x0 0x1000>;
>> + clock-frequency = <19200000>;
>> +
>> + frame@17421000 {
>> + frame-number = <0>;
>> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0 0x17421000 0x0 0x1000>,
>> + <0x0 0x17422000 0x0 0x1000>;
>> + };
>> +
>> + frame@17423000 {
>> + frame-number = <1>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0 0x17423000 0x0 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@17425000 {
>> + frame-number = <2>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0 0x17425000 0x0 0x1000>,
>> + <0x0 0x17426000 0x0 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@17427000 {
>> + frame-number = <3>;
>> + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0 0x17427000 0x0 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@17429000 {
>> + frame-number = <4>;
>> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0 0x17429000 0x0 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@1742b000 {
>> + frame-number = <5>;
>> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0 0x1742b000 0x0 0x1000>;
>> + status = "disabled";
>> + };
>> +
>> + frame@1742d000 {
>> + frame-number = <6>;
>> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> + reg = <0x0 0x1742d000 0x0 0x1000>;
>> + status = "disabled";
>> + };
>> + };
>> +
>> + apps_rsc: rsc@17a00000 {
>> + label = "apps_rsc";
>> + compatible = "qcom,rpmh-rsc";
>> + reg = <0x0 0x17a00000 0x0 0x10000>,
>> + <0x0 0x17a10000 0x0 0x10000>,
>> + <0x0 0x17a20000 0x0 0x10000>;
>> + reg-names = "drv-0", "drv-1", "drv-2";
>> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
>> + qcom,tcs-offset = <0xd00>;
>> + qcom,drv-id = <2>;
>> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
>> + <WAKE_TCS 3>, <CONTROL_TCS 0>;
>> +
>> + apps_bcm_voter: bcm_voter {
>> + compatible = "qcom,bcm-voter";
>> + };
>> +
>> + rpmhcc: clock-controller {
>> + compatible = "qcom,qdu1000-rpmh-clk", "qcom,qru1000-rpmh-clk";
>> + #clock-cells = <1>;
>> + clock-names = "xo";
>> + clocks = <&xo_board>;
>> + };
>> + };
>> +
>> + arch_timer: timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <19200000>;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> new file mode 100644
>> index 000000000000..ba195e7ffc38
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> @@ -0,0 +1,10 @@
>> +// SPDX-License-Identifier: BSD-3-Clause-Clear
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include "qdru1000.dtsi"
>> +
>> +/ {
>> + qcom,msm-id = <545 0x10000>, <587 0x10000>;
> Ugh. If this is the only difference between chips, I'd suggest merging
> qdru1000 in one of the includes and then overriding msm-id in the
> second one.
Yeah per our other conversation, I'll be merging qdru and qdu into one dtsi file then overriding any
differences in the qru dtsi. Also, will be removing msm-id since it's not accepted upstream anyways.
>
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi
>> new file mode 100644
>> index 000000000000..1639a4b3c1fb
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi
>> @@ -0,0 +1,10 @@
>> +// SPDX-License-Identifier: BSD-3-Clause-Clear
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include "qdru1000.dtsi"
>> +
>> +/ {
>> + qcom,msm-id = <539 0x10000>, <588 0x10000>, <589 0x10000>, <590 0x10000>;
>> +};
>> --
>> 2.37.3
>>
>
Thanks,
Melody
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs
2022-10-01 9:12 ` Krzysztof Kozlowski
@ 2022-10-11 18:22 ` Melody Olvera
0 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-11 18:22 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/1/2022 2:12 AM, Krzysztof Kozlowski wrote:
> On 01/10/2022 05:06, Melody Olvera wrote:
>> Add the base DTSI files for QDU1000 and QRU1000 SoCs, including base
>> descriptions of CPUs, GCC, RPMHCC, UART, and interrupt-controller to
>> boot to shell with console on these SoCs.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 370 +++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 10 +
>> arch/arm64/boot/dts/qcom/qru1000.dtsi | 10 +
>> 3 files changed, 390 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> new file mode 100644
>> index 000000000000..3610f94bef35
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> @@ -0,0 +1,370 @@
>> +// SPDX-License-Identifier: BSD-3-Clause-Clear
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-qdru1000.h>
>> +#include <dt-bindings/clock/qcom,rpmh.h>
>> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +
>> +/ {
>> + interrupt-parent = <&intc>;
>> +
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + chosen: chosen { };
>> +
>> +
> No need for double blank line.
Ack.
>
>> + clocks {
>> + xo_board: xo_board {
>> + compatible = "fixed-clock";
>> + clock-frequency = <19200000>;
>> + clock-output-names = "xo_board";
>> + #clock-cells = <0>;
>> + };
>> +
>> + sleep_clk: sleep_clk {
>> + compatible = "fixed-clock";
>> + clock-frequency = <32000>;
>> + #clock-cells = <0>;
>> + };
>> + };
>> +
> (...)
>
>> + CPU_PD3: cpu-pd3 {
>> + #power-domain-cells = <0>;
>> + power-domains = <&CLUSTER_PD>;
>> + domain-idle-states = <&SILVER_OFF>;
>> + };
>> +
>> + CLUSTER_PD: cluster-pd {
>> + #power-domain-cells = <0>;
>> + domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
>> + };
>> + };
>> +
>> + soc: soc@0 {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0 0 0 0x10 0>;
>> + dma-ranges = <0 0 0 0 0x10 0>;
>> + compatible = "simple-bus";
>> +
>> + gcc: clock-controller@80000 {
>> + compatible = "qcom,gcc-qdu1000", "qcom,gcc-qru1000", "syscon";
> Did you document the compatibles?
Yes; see the clocks patch set.
>
>> + reg = <0x0 0x80000 0x0 0x1f4200>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
>> + clock-names = "bi_tcxo", "sleep_clk";
>> + };
>> +
>> + qupv3_id_0: geniqup@9c0000 {
>> + compatible = "qcom,geni-se-qup";
>> + reg = <0x0 0x9c0000 0x0 0x2000>;
>> + clock-names = "m-ahb", "s-ahb";
>> + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
>> + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + status = "disabled";
>> +
>> + uart7: serial@99c000 {
>> + compatible = "qcom,geni-debug-uart";
>> + reg = <0x0 0x99c000 0x0 0x4000>;
>> + clock-names = "se";
>> + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> + interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + status = "disabled";
>> + };
>> + };
>> +
> (...)
>
>> + arch_timer: timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>> + clock-frequency = <19200000>;
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> new file mode 100644
>> index 000000000000..ba195e7ffc38
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
>> @@ -0,0 +1,10 @@
>> +// SPDX-License-Identifier: BSD-3-Clause-Clear
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include "qdru1000.dtsi"
>> +
>> +/ {
>> + qcom,msm-id = <545 0x10000>, <587 0x10000>;
> NAK.
Will remove.
>
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/qru1000.dtsi b/arch/arm64/boot/dts/qcom/qru1000.dtsi
>> new file mode 100644
>> index 000000000000..1639a4b3c1fb
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qru1000.dtsi
>> @@ -0,0 +1,10 @@
>> +// SPDX-License-Identifier: BSD-3-Clause-Clear
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include "qdru1000.dtsi"
>> +
>> +/ {
>> + qcom,msm-id = <539 0x10000>, <588 0x10000>, <589 0x10000>, <590 0x10000>;
> Nope, property is not documented and not accepted. Efforts in
> documenting this property were apparently also not accepted, therefore I
> am not agreeing in bringing DTS with these.
Will remove.
>
>> +};
> Best regards,
> Krzysztof
>
Thanks,
Melody
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
2022-10-01 7:28 ` Dmitry Baryshkov
@ 2022-10-11 18:29 ` Melody Olvera
0 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-11 18:29 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
linux-arm-msm, devicetree, linux-kernel
On 10/1/2022 12:28 AM, Dmitry Baryshkov wrote:
> On Sat, 1 Oct 2022 at 06:09, Melody Olvera <quic_molvera@quicinc.com> wrote:
>> Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000
>> SoCs.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 2 ++
>> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 30 ++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 30 ++++++++++++++++++++++++
>> 3 files changed, 62 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 1d86a33de528..398920c530b0 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -152,3 +152,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
> These two lines stand out. Please fix the indentation and move them to
> the proper place.
Ack.
>
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> new file mode 100644
>> index 000000000000..0ecf9a7c41ec
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: BSD-3-Clause-Clear
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "qdu1000.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. QDU1000 IDP";
>> + compatible = "qcom,qdu1000-idp", "qcom,qdu1000";
>> + qcom,board-id = <0x22 0x0>;
>> +
>> + aliases {
>> + serial0 = &uart7;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +};
>> +
>> +&qupv3_id_0 {
>> + status = "okay";
>> +};
>> +
>> +&uart7 {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
>> new file mode 100644
>> index 000000000000..ddb4ea17f7d2
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: BSD-3-Clause-Clear
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "qru1000.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. QRU1000 IDP";
>> + compatible = "qcom,qru1000-idp", "qcom,qru1000";
>> + qcom,board-id = <0x22 0x0>;
>> +
>> + aliases {
>> + serial0 = &uart7;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +};
>> +
>> +&qupv3_id_0 {
>> + status = "okay";
>> +};
>> +
>> +&uart7 {
>> + status = "okay";
>> +};
>> --
>> 2.37.3
>>
Thanks,
Melody
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs
2022-10-01 9:12 ` Krzysztof Kozlowski
@ 2022-10-11 18:31 ` Melody Olvera
0 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-11 18:31 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/1/2022 2:12 AM, Krzysztof Kozlowski wrote:
> On 01/10/2022 05:06, Melody Olvera wrote:
>> Add DTs for Qualcomm IDP platforms using the QDU1000 and QRU1000
>> SoCs.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/Makefile | 2 ++
>> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 30 ++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 30 ++++++++++++++++++++++++
>> 3 files changed, 62 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/qru1000-idp.dts
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 1d86a33de528..398920c530b0 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -152,3 +152,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
>> dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb
>> +dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
> List is ordered by name.
>
>
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> new file mode 100644
>> index 000000000000..0ecf9a7c41ec
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: BSD-3-Clause-Clear
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "qdu1000.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. QDU1000 IDP";
>> + compatible = "qcom,qdu1000-idp", "qcom,qdu1000";
> Undocumented compatibles. You need bindings for these.
Will make sure these are documented.
>
>> + qcom,board-id = <0x22 0x0>;
>> +
>> + aliases {
>> + serial0 = &uart7;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +};
>> +
>> +&qupv3_id_0 {
>> + status = "okay";
>> +};
>> +
>> +&uart7 {
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
>> new file mode 100644
>> index 000000000000..ddb4ea17f7d2
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
>> @@ -0,0 +1,30 @@
>> +// SPDX-License-Identifier: BSD-3-Clause-Clear
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "qru1000.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. QRU1000 IDP";
>> + compatible = "qcom,qru1000-idp", "qcom,qru1000";
> Same problem.
Ack.
>
>> + qcom,board-id = <0x22 0x0>;
> Undocumented compatible. Drop it.
Will drop.
>
> Best regards,
> Krzysztof
>
Thanks,
Melody
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes
2022-10-01 7:26 ` Dmitry Baryshkov
@ 2022-10-11 18:40 ` Melody Olvera
0 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-11 18:40 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
linux-arm-msm, devicetree, linux-kernel
On 10/1/2022 12:26 AM, Dmitry Baryshkov wrote:
> On Sat, 1 Oct 2022 at 06:09, Melody Olvera <quic_molvera@quicinc.com> wrote:
>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>> configuration.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
>> 1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> index 3610f94bef35..39b9a00d3ad8 100644
>> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> @@ -235,6 +235,8 @@ uart7: serial@99c000 {
>> reg = <0x0 0x99c000 0x0 0x4000>;
>> clock-names = "se";
>> clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart7_default>;
>> interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>> #address-cells = <1>;
>> #size-cells = <0>;
>> @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
>> #hwlock-cells = <1>;
>> };
>>
>> + tlmm: pinctrl@f000000 {
>> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 151>;
>> + wakeup-parent = <&pdc>;
>> +
>> + qup_uart7_default: qup-uart7-default {
>> + tx {
>> + pins = "gpio134";
>> + function = "qup0_se7_l2";
> This looks strange. Usually we'd have a single 'qup7' function here.
> I'd go back to the interconnect driver. Maybe the functions are not
> correctly defined there.
Yeah; will correct. Pinctrl driver was not in line with upstream standards.
>
>> + drive-strength = <2>;
>> + bias-disable;
> 'drive-strength' and 'bias-disable' are to be patched in in the board dts file.
Really? Looking at sm8450.dtsi and sm8350.dtsi I see them defined in the dtsi file instead of the
dts file. Is this new?
>
>> + };
>> +
>> + rx {
>> + pins = "gpio135";
>> + function = "qup0_se7_l3";
>> + drive-strength = <2>;
>> + bias-disable;
>> + };
>> + };
>> + };
>> +
>> pdc: interrupt-controller@b220000 {
>> compatible = "qcom,pdc";
>> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
>> --
>> 2.37.3
>>
>
Thanks,
Melody
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes
2022-10-01 9:14 ` Krzysztof Kozlowski
@ 2022-10-11 18:48 ` Melody Olvera
2022-10-11 18:57 ` Krzysztof Kozlowski
0 siblings, 1 reply; 46+ messages in thread
From: Melody Olvera @ 2022-10-11 18:48 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/1/2022 2:14 AM, Krzysztof Kozlowski wrote:
> On 01/10/2022 05:06, Melody Olvera wrote:
>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>> configuration.
> The patchset should be squashed with previous. There is no point in
> bringing support piece by piece. You can bring support in steps if you
> submissions are separate in time. But if you have everything ready -
> your patch must be complete and bisectable.
To be clear, does it make more sense to submit the base dt first, then submit each
driver with all the dt changes as one patchset?
>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qdru1000.dtsi | 30 ++++++++++++++++++++++++++
>> 1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdru1000.dtsi b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> index 3610f94bef35..39b9a00d3ad8 100644
>> --- a/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qdru1000.dtsi
>> @@ -235,6 +235,8 @@ uart7: serial@99c000 {
>> reg = <0x0 0x99c000 0x0 0x4000>;
>> clock-names = "se";
>> clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&qup_uart7_default>;
>> interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
>> #address-cells = <1>;
>> #size-cells = <0>;
>> @@ -248,6 +250,34 @@ tcsr_mutex: hwlock@1f40000 {
>> #hwlock-cells = <1>;
>> };
>>
>> + tlmm: pinctrl@f000000 {
>> + compatible = "qcom,qdu1000-tlmm", "qcom,qru1000-tlmm";
>> + reg = <0x0 0xf000000 0x0 0x1000000>;
>> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + gpio-ranges = <&tlmm 0 0 151>;
>> + wakeup-parent = <&pdc>;
>> +
>> + qup_uart7_default: qup-uart7-default {
> Suffix "-state"
Ack.
>
>> + tx {
> Suffix "-pins"
Ack.
>
>> + pins = "gpio134";
>> + function = "qup0_se7_l2";
>> + drive-strength = <2>;
>> + bias-disable;
>> + };
>> +
>> + rx {
> Suffix "-pins"
Ack.
>
>
>> + pins = "gpio135";
>> + function = "qup0_se7_l3";
>> + drive-strength = <2>;
>> + bias-disable;
>> + };
>> + };
>> + };
>> +
>> pdc: interrupt-controller@b220000 {
>> compatible = "qcom,pdc";
>> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
> Best regards,
> Krzysztof
>
Thanks,
Melody
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes
2022-10-11 18:48 ` Melody Olvera
@ 2022-10-11 18:57 ` Krzysztof Kozlowski
2022-10-11 19:05 ` Melody Olvera
0 siblings, 1 reply; 46+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-11 18:57 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 11/10/2022 14:48, Melody Olvera wrote:
>
>
> On 10/1/2022 2:14 AM, Krzysztof Kozlowski wrote:
>> On 01/10/2022 05:06, Melody Olvera wrote:
>>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>>> configuration.
>> The patchset should be squashed with previous. There is no point in
>> bringing support piece by piece. You can bring support in steps if you
>> submissions are separate in time. But if you have everything ready -
>> your patch must be complete and bisectable.
> To be clear, does it make more sense to submit the base dt first, then submit each
> driver with all the dt changes as one patchset?
No, because you have DTS ready. There is no incremental work here.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes
2022-10-11 18:57 ` Krzysztof Kozlowski
@ 2022-10-11 19:05 ` Melody Olvera
2022-10-11 19:19 ` Krzysztof Kozlowski
0 siblings, 1 reply; 46+ messages in thread
From: Melody Olvera @ 2022-10-11 19:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/11/2022 11:57 AM, Krzysztof Kozlowski wrote:
> On 11/10/2022 14:48, Melody Olvera wrote:
>>
>> On 10/1/2022 2:14 AM, Krzysztof Kozlowski wrote:
>>> On 01/10/2022 05:06, Melody Olvera wrote:
>>>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>>>> configuration.
>>> The patchset should be squashed with previous. There is no point in
>>> bringing support piece by piece. You can bring support in steps if you
>>> submissions are separate in time. But if you have everything ready -
>>> your patch must be complete and bisectable.
>> To be clear, does it make more sense to submit the base dt first, then submit each
>> driver with all the dt changes as one patchset?
> No, because you have DTS ready. There is no incremental work here.
Ah ok so just squash all these commits into one and submit.
>
> Best regards,
> Krzysztof
>
Thanks,
Melody
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes
2022-10-11 19:05 ` Melody Olvera
@ 2022-10-11 19:19 ` Krzysztof Kozlowski
2022-10-11 20:01 ` Melody Olvera
0 siblings, 1 reply; 46+ messages in thread
From: Krzysztof Kozlowski @ 2022-10-11 19:19 UTC (permalink / raw)
To: Melody Olvera, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 11/10/2022 15:05, Melody Olvera wrote:
>
>
> On 10/11/2022 11:57 AM, Krzysztof Kozlowski wrote:
>> On 11/10/2022 14:48, Melody Olvera wrote:
>>>
>>> On 10/1/2022 2:14 AM, Krzysztof Kozlowski wrote:
>>>> On 01/10/2022 05:06, Melody Olvera wrote:
>>>>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>>>>> configuration.
>>>> The patchset should be squashed with previous. There is no point in
>>>> bringing support piece by piece. You can bring support in steps if you
>>>> submissions are separate in time. But if you have everything ready -
>>>> your patch must be complete and bisectable.
>>> To be clear, does it make more sense to submit the base dt first, then submit each
>>> driver with all the dt changes as one patchset?
>> No, because you have DTS ready. There is no incremental work here.
> Ah ok so just squash all these commits into one and submit.
Except the board DTS. Other bigger, self-contained pieces of work can be
also kept separate, but such work is not "add a DMA". Such work could be
- add display (with clocks, DMA, GPU, power domains) or sound (again
multiple separate devices added).
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes
2022-10-11 19:19 ` Krzysztof Kozlowski
@ 2022-10-11 20:01 ` Melody Olvera
0 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-11 20:01 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/11/2022 12:19 PM, Krzysztof Kozlowski wrote:
> On 11/10/2022 15:05, Melody Olvera wrote:
>>
>> On 10/11/2022 11:57 AM, Krzysztof Kozlowski wrote:
>>> On 11/10/2022 14:48, Melody Olvera wrote:
>>>> On 10/1/2022 2:14 AM, Krzysztof Kozlowski wrote:
>>>>> On 01/10/2022 05:06, Melody Olvera wrote:
>>>>>> Add tlmm node for the QDU1000 and QRU1000 SoCs and the uart pin
>>>>>> configuration.
>>>>> The patchset should be squashed with previous. There is no point in
>>>>> bringing support piece by piece. You can bring support in steps if you
>>>>> submissions are separate in time. But if you have everything ready -
>>>>> your patch must be complete and bisectable.
>>>> To be clear, does it make more sense to submit the base dt first, then submit each
>>>> driver with all the dt changes as one patchset?
>>> No, because you have DTS ready. There is no incremental work here.
>> Ah ok so just squash all these commits into one and submit.
> Except the board DTS. Other bigger, self-contained pieces of work can be
> also kept separate, but such work is not "add a DMA". Such work could be
> - add display (with clocks, DMA, GPU, power domains) or sound (again
> multiple separate devices added).
Understood. Yeah I figured leave the dts files as a separate commit, but do one big commit
for the dtsi file, and one for the dts files.
>
> Best regards,
> Krzysztof
>
Thanks,
Melody
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 07/19] arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes
2022-10-01 9:15 ` Krzysztof Kozlowski
@ 2022-10-11 21:08 ` Melody Olvera
0 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-11 21:08 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/1/2022 2:15 AM, Krzysztof Kozlowski wrote:
> On 01/10/2022 05:06, Melody Olvera wrote:
>> Add RPMH regulators for the QDU1000 IDP platform.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qdu1000-idp.dts | 200 +++++++++++++++++++++++
>> 1 file changed, 200 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> index 0ecf9a7c41ec..654b50220c2e 100644
>> --- a/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> +++ b/arch/arm64/boot/dts/qcom/qdu1000-idp.dts
>> @@ -5,6 +5,7 @@
>>
>> /dts-v1/;
>>
>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> #include "qdu1000.dtsi"
>>
>> / {
>> @@ -19,6 +20,205 @@ aliases {
>> chosen {
>> stdout-path = "serial0:115200n8";
>> };
>> +
>> + ppvar_sys: ppvar-sys-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "ppvar_sys";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vph_pwr: vph-pwr-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vph_pwr";
>> + regulator-min-microvolt = <3700000>;
>> + regulator-max-microvolt = <3700000>;
>> +
>> + regulator-always-on;
>> + regulator-boot-on;
>> +
>> + vin-supply = <&ppvar_sys>;
>> + };
>> +};
>> +
>> +&apps_rsc {
>> + pm8150-rpmh-regulators {
> regulators
Will fix.
>> + compatible = "qcom,pm8150-rpmh-regulators";
>> + qcom,pmic-id = "a";
>> +
> Best regards,
> Krzysztof
>
Thanks,
Melody
^ permalink raw reply [flat|nested] 46+ messages in thread
* Re: [PATCH 08/19] arm64: dts: qcom: qru1000-idp: Add RPMH regulators nodes
2022-10-01 9:15 ` Krzysztof Kozlowski
@ 2022-10-11 21:08 ` Melody Olvera
0 siblings, 0 replies; 46+ messages in thread
From: Melody Olvera @ 2022-10-11 21:08 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/1/2022 2:15 AM, Krzysztof Kozlowski wrote:
> On 01/10/2022 05:06, Melody Olvera wrote:
>> Add RPMH regulators for the QRU1000 IDP platform.
>>
>> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/qru1000-idp.dts | 200 +++++++++++++++++++++++
>> 1 file changed, 200 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qru1000-idp.dts b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
>> index ddb4ea17f7d2..8d27923dc470 100644
>> --- a/arch/arm64/boot/dts/qcom/qru1000-idp.dts
>> +++ b/arch/arm64/boot/dts/qcom/qru1000-idp.dts
>> @@ -5,6 +5,7 @@
>>
>> /dts-v1/;
>>
>> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
>> #include "qru1000.dtsi"
>>
>> / {
>> @@ -19,6 +20,205 @@ aliases {
>> chosen {
>> stdout-path = "serial0:115200n8";
>> };
>> +
>> + ppvar_sys: ppvar-sys-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "ppvar_sys";
>> + regulator-always-on;
>> + regulator-boot-on;
>> + };
>> +
>> + vph_pwr: vph-pwr-regulator {
>> + compatible = "regulator-fixed";
>> + regulator-name = "vph_pwr";
>> + regulator-min-microvolt = <3700000>;
>> + regulator-max-microvolt = <3700000>;
>> +
>> + regulator-always-on;
>> + regulator-boot-on;
>> +
>> + vin-supply = <&ppvar_sys>;
>> + };
>> +};
>> +
>> +&apps_rsc {
>> + pm8150-rpmh-regulators {
> regulators
Will Fix.
>
> Best regards,
> Krzysztof
>
Thanks,
Melody
^ permalink raw reply [flat|nested] 46+ messages in thread
end of thread, other threads:[~2022-10-11 21:09 UTC | newest]
Thread overview: 46+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-10-01 3:06 [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Melody Olvera
2022-10-01 3:06 ` [PATCH 01/19] arm64: dts: qcom: Add base QDU1000/QRU1000 DTSIs Melody Olvera
2022-10-01 7:22 ` Dmitry Baryshkov
2022-10-11 18:21 ` Melody Olvera
2022-10-01 9:12 ` Krzysztof Kozlowski
2022-10-11 18:22 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 02/19] arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs Melody Olvera
2022-10-01 7:28 ` Dmitry Baryshkov
2022-10-11 18:29 ` Melody Olvera
2022-10-01 9:12 ` Krzysztof Kozlowski
2022-10-11 18:31 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 03/19] arm64: dts: qcom: qdru1000: Add tlmm nodes Melody Olvera
2022-10-01 7:26 ` Dmitry Baryshkov
2022-10-11 18:40 ` Melody Olvera
2022-10-01 9:14 ` Krzysztof Kozlowski
2022-10-11 18:48 ` Melody Olvera
2022-10-11 18:57 ` Krzysztof Kozlowski
2022-10-11 19:05 ` Melody Olvera
2022-10-11 19:19 ` Krzysztof Kozlowski
2022-10-11 20:01 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 04/19] arm64: dts: qcom: qdu1000: Add reserved memory nodes Melody Olvera
2022-10-01 9:14 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 05/19] arm64: dts: qcom: qru1000: " Melody Olvera
2022-10-01 3:06 ` [PATCH 06/19] arm64: dts: qcom: qdru1000: Add smmu nodes Melody Olvera
2022-10-01 7:23 ` Dmitry Baryshkov
2022-10-01 3:06 ` [PATCH 07/19] arm64: dts: qcom: qdu1000-idp: Add RPMH regulators nodes Melody Olvera
2022-10-01 9:15 ` Krzysztof Kozlowski
2022-10-11 21:08 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 08/19] arm64: dts: qcom: qru1000-idp: " Melody Olvera
2022-10-01 9:15 ` Krzysztof Kozlowski
2022-10-11 21:08 ` Melody Olvera
2022-10-01 3:06 ` [PATCH 09/19] arm64: dts: qcom: qdru1000: Add interconnect nodes Melody Olvera
2022-10-01 9:16 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 10/19] arm64: dts: qcom: qdru1000: Add rpmhpd node Melody Olvera
2022-10-01 3:06 ` [PATCH 11/19] arm64: dts: qcom: qdru1000: Add spmi node Melody Olvera
2022-10-01 3:06 ` [PATCH 12/19] arm64: dts: qcom: qdu1000-idp: Include pmic file Melody Olvera
2022-10-01 9:16 ` Krzysztof Kozlowski
2022-10-01 3:06 ` [PATCH 13/19] arm64: dts: qcom: qru1000-idp: " Melody Olvera
2022-10-01 3:06 ` [PATCH 14/19] arm64: dts: qcom: qdru1000: Add cpufreq support Melody Olvera
2022-10-01 3:06 ` [PATCH 15/19] arm64: dts: qcom: qdru1000: Add additional QUP nodes Melody Olvera
2022-10-01 3:06 ` [PATCH 16/19] arm64: dts: qcom: qdru1000: Add gpi_dma nodes Melody Olvera
2022-10-01 3:06 ` [PATCH 17/19] arm64: dts: qcom: qdru1000: Add I2C nodes for QUP Melody Olvera
2022-10-01 7:30 ` Dmitry Baryshkov
2022-10-01 3:06 ` [PATCH 18/19] arm64: dts: qcom: qdru1000: Add SPI devices to QUP nodes Melody Olvera
2022-10-01 3:06 ` [PATCH 19/19] arm64: dts: qcom: qdru1000: Add additional UART instances Melody Olvera
2022-10-01 7:32 ` [PATCH 00/19] Add base device tree files for QDU1000/QRU1000 Dmitry Baryshkov
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