Re: [PATCH v7 14/21] iommu/mediatek: Add mmu1 support

[Tomasz Figa <tfiga@google.com>]

On Tue, Jun 18, 2019 at 9:09 PM Yong Wu <yong.wu@mediatek.com> wrote:
>
> On Tue, 2019-06-18 at 15:19 +0900, Tomasz Figa wrote:
> > On Mon, Jun 10, 2019 at 9:21 PM Yong Wu <yong.wu@mediatek.com> wrote:
> > >
> > > Normally the M4U HW connect EMI with smi. the diagram is like below:
> > >               EMI
> > >                |
> > >               M4U
> > >                |
> > >             smi-common
> > >                |
> > >        -----------------
> > >        |    |    |     |    ...
> > >     larb0 larb1  larb2 larb3
> > >
> > > Actually there are 2 mmu cells in the M4U HW, like this diagram:
> > >
> > >               EMI
> > >            ---------
> > >             |     |
> > >            mmu0  mmu1     <- M4U
> > >             |     |
> > >            ---------
> > >                |
> > >             smi-common
> > >                |
> > >        -----------------
> > >        |    |    |     |    ...
> > >     larb0 larb1  larb2 larb3
> > >
> > > This patch add support for mmu1. In order to get better performance,
> > > we could adjust some larbs go to mmu1 while the others still go to
> > > mmu0. This is controlled by a SMI COMMON register SMI_BUS_SEL(0x220).
> > >
> > > mt2712, mt8173 and mt8183 M4U HW all have 2 mmu cells. the default
> > > value of that register is 0 which means all the larbs go to mmu0
> > > defaultly.
> > >
> > > This is a preparing patch for adjusting SMI_BUS_SEL for mt8183.
> > >
> > > Signed-off-by: Yong Wu <yong.wu@mediatek.com>
> > > Reviewed-by: Evan Green <evgreen@chromium.org>
> > > ---
> > >  drivers/iommu/mtk_iommu.c | 46 +++++++++++++++++++++++++++++-----------------
> > >  1 file changed, 29 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> > > index 3a14301..ec4ce74 100644
> > > --- a/drivers/iommu/mtk_iommu.c
> > > +++ b/drivers/iommu/mtk_iommu.c
> > > @@ -72,26 +72,32 @@
> > >  #define F_INT_CLR_BIT                          BIT(12)
> > >
> > >  #define REG_MMU_INT_MAIN_CONTROL               0x124
> > > -#define F_INT_TRANSLATION_FAULT                        BIT(0)
> > > -#define F_INT_MAIN_MULTI_HIT_FAULT             BIT(1)
> > > -#define F_INT_INVALID_PA_FAULT                 BIT(2)
> > > -#define F_INT_ENTRY_REPLACEMENT_FAULT          BIT(3)
> > > -#define F_INT_TLB_MISS_FAULT                   BIT(4)
> > > -#define F_INT_MISS_TRANSACTION_FIFO_FAULT      BIT(5)
> > > -#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT   BIT(6)
> > > +                                               /* mmu0 | mmu1 */
> > > +#define F_INT_TRANSLATION_FAULT                        (BIT(0) | BIT(7))
> > > +#define F_INT_MAIN_MULTI_HIT_FAULT             (BIT(1) | BIT(8))
> > > +#define F_INT_INVALID_PA_FAULT                 (BIT(2) | BIT(9))
> > > +#define F_INT_ENTRY_REPLACEMENT_FAULT          (BIT(3) | BIT(10))
> > > +#define F_INT_TLB_MISS_FAULT                   (BIT(4) | BIT(11))
> > > +#define F_INT_MISS_TRANSACTION_FIFO_FAULT      (BIT(5) | BIT(12))
> > > +#define F_INT_PRETETCH_TRANSATION_FIFO_FAULT   (BIT(6) | BIT(13))
> >
> > If there are two IOMMUs, shouldn't we have two driver instances handle
> > them, instead of making the driver combine them two internally?
>
> Actually it means only one IOMMU(M4U) HW here. Each a M4U HW has two
> small iommu cells which have independent MTLB. As the diagram above, M4U
> contain mmu0 and mmu1.
>
> MT8173 and MT8183 have only one M4U HW while MT2712 have 2 M4U HWs(two
> driver instances).
>
> >
> > And, what is even more important from security point of view actually,
> > have two separate page tables (aka IOMMU groups) for them?
>
> Each a IOMMU(M4U) have its own pagetable, thus, mt8183 have only one
> pagetable while mt2712 have two.

I see, thanks for clarifying.

Best regards,
Tomasz