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* [PATCH] perf/x86: Fix LLC-* and node-* events on Intel SandyBridge
@ 2012-07-17  9:27 Yan, Zheng
  2012-07-20 16:48 ` Peter Zijlstra
  2012-07-26 15:12 ` [tip:perf/core] " tip-bot for Yan, Zheng
  0 siblings, 2 replies; 5+ messages in thread
From: Yan, Zheng @ 2012-07-17  9:27 UTC (permalink / raw)
  To: a.p.zijlstra, mingo, andi, linux-kernel; +Cc: Yan, Zheng

From: "Yan, Zheng" <zheng.z.yan@intel.com>

LLC-* and node-* events require using the OFFCORE_RESPONSE events
on SandyBridge, but the hw_cache_extra_regs is left uninitialized.
This patch adds the missing extra register configure table for
SandyBridge.

Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
---
 arch/x86/kernel/cpu/perf_event_intel.c |   92 +++++++++++++++++++++++++++++---
 1 file changed, 86 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 7a8b9d0..3823669 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -138,6 +138,84 @@ static u64 intel_pmu_event_map(int hw_event)
 	return intel_perfmon_event_map[hw_event];
 }
 
+#define SNB_DMND_DATA_RD	(1ULL << 0)
+#define SNB_DMND_RFO		(1ULL << 1)
+#define SNB_DMND_IFETCH		(1ULL << 2)
+#define SNB_DMND_WB		(1ULL << 3)
+#define SNB_PF_DATA_RD		(1ULL << 4)
+#define SNB_PF_RFO		(1ULL << 5)
+#define SNB_PF_IFETCH		(1ULL << 6)
+#define SNB_LLC_DATA_RD		(1ULL << 7)
+#define SNB_LLC_RFO		(1ULL << 8)
+#define SNB_LLC_IFETCH		(1ULL << 9)
+#define SNB_BUS_LOCKS		(1ULL << 10)
+#define SNB_STRM_ST		(1ULL << 11)
+#define SNB_OTHER		(1ULL << 15)
+#define SNB_RESP_ANY		(1ULL << 16)
+#define SNB_NO_SUPP		(1ULL << 17)
+#define SNB_LLC_HITM		(1ULL << 18)
+#define SNB_LLC_HITE		(1ULL << 19)
+#define SNB_LLC_HITS		(1ULL << 20)
+#define SNB_LLC_HITF		(1ULL << 21)
+#define SNB_LOCAL		(1ULL << 22)
+#define SNB_REMOTE		(0xffULL << 23)
+#define SNB_SNP_NONE		(1ULL << 31)
+#define SNB_SNP_NOT_NEEDED	(1ULL << 32)
+#define SNB_SNP_MISS		(1ULL << 33)
+#define SNB_NO_FWD		(1ULL << 34)
+#define SNB_SNP_FWD		(1ULL << 35)
+#define SNB_HITM		(1ULL << 36)
+#define SNB_NON_DRAM		(1ULL << 37)
+
+#define SNB_DMND_READ		(SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
+#define SNB_DMND_WRITE		(SNB_DMND_RFO|SNB_LLC_RFO)
+#define SNB_DMND_PREFETCH	(SNB_PF_DATA_RD|SNB_PF_RFO)
+
+#define SNB_SNP_ANY		(SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
+				 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
+				 SNB_HITM)
+
+#define SNB_DRAM_ANY		(SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
+#define SNB_DRAM_REMOTE		(SNB_REMOTE|SNB_SNP_ANY)
+
+#define SNB_L3_ACCESS		SNB_RESP_ANY
+#define SNB_L3_MISS		(SNB_DRAM_ANY|SNB_NON_DRAM)
+
+static __initconst const u64 snb_hw_cache_extra_regs
+				[PERF_COUNT_HW_CACHE_MAX]
+				[PERF_COUNT_HW_CACHE_OP_MAX]
+				[PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(LL  ) ] = {
+	[ C(OP_READ) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
+		[ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
+	},
+	[ C(OP_WRITE) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
+		[ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
+	},
+	[ C(OP_PREFETCH) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
+		[ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
+	},
+ },
+ [ C(NODE) ] = {
+	[ C(OP_READ) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
+		[ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
+	},
+	[ C(OP_WRITE) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
+		[ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
+	},
+	[ C(OP_PREFETCH) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
+		[ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
+	},
+ },
+};
+
 static __initconst const u64 snb_hw_cache_event_ids
 				[PERF_COUNT_HW_CACHE_MAX]
 				[PERF_COUNT_HW_CACHE_OP_MAX]
@@ -235,16 +313,16 @@ static __initconst const u64 snb_hw_cache_event_ids
  },
  [ C(NODE) ] = {
 	[ C(OP_READ) ] = {
-		[ C(RESULT_ACCESS) ] = -1,
-		[ C(RESULT_MISS)   ] = -1,
+		[ C(RESULT_ACCESS) ] = 0x01b7,
+		[ C(RESULT_MISS)   ] = 0x01b7,
 	},
 	[ C(OP_WRITE) ] = {
-		[ C(RESULT_ACCESS) ] = -1,
-		[ C(RESULT_MISS)   ] = -1,
+		[ C(RESULT_ACCESS) ] = 0x01b7,
+		[ C(RESULT_MISS)   ] = 0x01b7,
 	},
 	[ C(OP_PREFETCH) ] = {
-		[ C(RESULT_ACCESS) ] = -1,
-		[ C(RESULT_MISS)   ] = -1,
+		[ C(RESULT_ACCESS) ] = 0x01b7,
+		[ C(RESULT_MISS)   ] = 0x01b7,
 	},
  },
 
@@ -1964,6 +2042,8 @@ __init int intel_pmu_init(void)
 	case 58: /* IvyBridge */
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
+		memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
+		       sizeof(hw_cache_extra_regs));
 
 		intel_pmu_lbr_init_snb();
 
-- 
1.7.10.4


^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH] perf/x86: Fix LLC-* and node-* events on Intel SandyBridge
  2012-07-17  9:27 [PATCH] perf/x86: Fix LLC-* and node-* events on Intel SandyBridge Yan, Zheng
@ 2012-07-20 16:48 ` Peter Zijlstra
  2012-07-22 11:43   ` Yan, Zheng 
  2012-07-26 15:12 ` [tip:perf/core] " tip-bot for Yan, Zheng
  1 sibling, 1 reply; 5+ messages in thread
From: Peter Zijlstra @ 2012-07-20 16:48 UTC (permalink / raw)
  To: Yan, Zheng; +Cc: mingo, andi, linux-kernel, Stephane Eranian

On Tue, 2012-07-17 at 17:27 +0800, Yan, Zheng wrote:
> From: "Yan, Zheng" <zheng.z.yan@intel.com>
> 
> LLC-* and node-* events require using the OFFCORE_RESPONSE events
> on SandyBridge, but the hw_cache_extra_regs is left uninitialized.
> This patch adds the missing extra register configure table for
> SandyBridge. 

Last time I tried this I couldn't get sane numbers out of it..

Does these encodings work, if so, do explain them.

Also:

> +#define SNB_REMOTE             (0xffULL << 23)

I guess I can take this as an 'official' publication of this fact?

(I knew those bits meant this, but I never got a response if I could
publish that information.)

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] perf/x86: Fix LLC-* and node-* events on Intel SandyBridge
  2012-07-20 16:48 ` Peter Zijlstra
@ 2012-07-22 11:43   ` Yan, Zheng 
  2012-07-23 12:22     ` Peter Zijlstra
  0 siblings, 1 reply; 5+ messages in thread
From: Yan, Zheng  @ 2012-07-22 11:43 UTC (permalink / raw)
  To: Peter Zijlstra; +Cc: Yan, Zheng, mingo, andi, linux-kernel, Stephane Eranian

On Sat, Jul 21, 2012 at 12:48 AM, Peter Zijlstra <a.p.zijlstra@chello.nl> wrote:
> On Tue, 2012-07-17 at 17:27 +0800, Yan, Zheng wrote:
>> From: "Yan, Zheng" <zheng.z.yan@intel.com>
>>
>> LLC-* and node-* events require using the OFFCORE_RESPONSE events
>> on SandyBridge, but the hw_cache_extra_regs is left uninitialized.
>> This patch adds the missing extra register configure table for
>> SandyBridge.
>
> Last time I tried this I couldn't get sane numbers out of it..
>
> Does these encodings work, if so, do explain them.
>

I have tested them and compared the results with Nehalme. I think
they do work.

>> +#define SNB_DMND_READ          (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
normal LLC reads + LLC reads generated by L2 prefetcher

>> +#define SNB_DMND_WRITE         (SNB_DMND_RFO|SNB_LLC_RFO)
normal RFO requests + RFO requests generated by L2 prefetcher

>> +#define SNB_DMND_PREFETCH      (SNB_PF_DATA_RD|SNB_PF_RFO)
>> +
>> +#define SNB_SNP_ANY            (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
>> +                                SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
>> +                                SNB_HITM)
SNB_SNP_ANY contains all snoop related bits, because we don't care the snoop
information.

>> +
>> +#define SNB_DRAM_ANY           (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
>> +#define SNB_DRAM_REMOTE                (SNB_REMOTE|SNB_SNP_ANY)
>> +
>> +#define SNB_L3_ACCESS          SNB_RESP_ANY
For LLC access, we don't care the supplier and snoop information.

>> +#define SNB_L3_MISS            (SNB_DRAM_ANY|SNB_NON_DRAM)
If the supplier is DRAM, we consider it as LLC miss.

> Also:
>
>> +#define SNB_REMOTE             (0xffULL << 23)
>
> I guess I can take this as an 'official' publication of this fact?
>
> (I knew those bits meant this, but I never got a response if I could
> publish that information.)
>
See chapter 18.8.7 of Intel 64 SDM Volume 3 (Order Number 325384)

Regards
Yan, Zheng

^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] perf/x86: Fix LLC-* and node-* events on Intel SandyBridge
  2012-07-22 11:43   ` Yan, Zheng 
@ 2012-07-23 12:22     ` Peter Zijlstra
  0 siblings, 0 replies; 5+ messages in thread
From: Peter Zijlstra @ 2012-07-23 12:22 UTC (permalink / raw)
  To: Yan, Zheng; +Cc: Yan, Zheng, mingo, andi, linux-kernel, Stephane Eranian

On Sun, 2012-07-22 at 19:43 +0800, Yan, Zheng wrote:
> On Sat, Jul 21, 2012 at 12:48 AM, Peter Zijlstra <a.p.zijlstra@chello.nl> wrote:
> > On Tue, 2012-07-17 at 17:27 +0800, Yan, Zheng wrote:
> >> From: "Yan, Zheng" <zheng.z.yan@intel.com>
> >>
> >> LLC-* and node-* events require using the OFFCORE_RESPONSE events
> >> on SandyBridge, but the hw_cache_extra_regs is left uninitialized.
> >> This patch adds the missing extra register configure table for
> >> SandyBridge.
> >
> > Last time I tried this I couldn't get sane numbers out of it..
> >
> > Does these encodings work, if so, do explain them.
> >
> 
> I have tested them and compared the results with Nehalme. I think
> they do work.

OK, great, thanks!

> > I guess I can take this as an 'official' publication of this fact?
> >
> > (I knew those bits meant this, but I never got a response if I could
> > publish that information.)
> >
> See chapter 18.8.7 of Intel 64 SDM Volume 3 (Order Number 325384)

D'0h, that's confusing.. I was staring at 18.8.5..

^ permalink raw reply	[flat|nested] 5+ messages in thread
* [tip:perf/core] perf/x86: Fix LLC-* and node-* events on Intel SandyBridge
  2012-07-17  9:27 [PATCH] perf/x86: Fix LLC-* and node-* events on Intel SandyBridge Yan, Zheng
  2012-07-20 16:48 ` Peter Zijlstra
@ 2012-07-26 15:12 ` tip-bot for Yan, Zheng
  1 sibling, 0 replies; 5+ messages in thread
From: tip-bot for Yan, Zheng @ 2012-07-26 15:12 UTC (permalink / raw)
  To: linux-tip-commits
  Cc: linux-kernel, hpa, mingo, a.p.zijlstra, zheng.z.yan, tglx

Commit-ID:  74e6543fdc4e7553f572f7898ade649a09d85049
Gitweb:     http://git.kernel.org/tip/74e6543fdc4e7553f572f7898ade649a09d85049
Author:     Yan, Zheng <zheng.z.yan@intel.com>
AuthorDate: Tue, 17 Jul 2012 17:27:55 +0800
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 26 Jul 2012 12:23:12 +0200

perf/x86: Fix LLC-* and node-* events on Intel SandyBridge

LLC-* and node-* events require using the OFFCORE_RESPONSE events
on SandyBridge, but the hw_cache_extra_regs is left uninitialized.
This patch adds the missing extra register configure table for
SandyBridge.

Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Link: http://lkml.kernel.org/r/1342517275-2875-1-git-send-email-zheng.z.yan@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/kernel/cpu/perf_event_intel.c |   92 +++++++++++++++++++++++++++++--
 1 files changed, 86 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 7a8b9d0..3823669 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -138,6 +138,84 @@ static u64 intel_pmu_event_map(int hw_event)
 	return intel_perfmon_event_map[hw_event];
 }
 
+#define SNB_DMND_DATA_RD	(1ULL << 0)
+#define SNB_DMND_RFO		(1ULL << 1)
+#define SNB_DMND_IFETCH		(1ULL << 2)
+#define SNB_DMND_WB		(1ULL << 3)
+#define SNB_PF_DATA_RD		(1ULL << 4)
+#define SNB_PF_RFO		(1ULL << 5)
+#define SNB_PF_IFETCH		(1ULL << 6)
+#define SNB_LLC_DATA_RD		(1ULL << 7)
+#define SNB_LLC_RFO		(1ULL << 8)
+#define SNB_LLC_IFETCH		(1ULL << 9)
+#define SNB_BUS_LOCKS		(1ULL << 10)
+#define SNB_STRM_ST		(1ULL << 11)
+#define SNB_OTHER		(1ULL << 15)
+#define SNB_RESP_ANY		(1ULL << 16)
+#define SNB_NO_SUPP		(1ULL << 17)
+#define SNB_LLC_HITM		(1ULL << 18)
+#define SNB_LLC_HITE		(1ULL << 19)
+#define SNB_LLC_HITS		(1ULL << 20)
+#define SNB_LLC_HITF		(1ULL << 21)
+#define SNB_LOCAL		(1ULL << 22)
+#define SNB_REMOTE		(0xffULL << 23)
+#define SNB_SNP_NONE		(1ULL << 31)
+#define SNB_SNP_NOT_NEEDED	(1ULL << 32)
+#define SNB_SNP_MISS		(1ULL << 33)
+#define SNB_NO_FWD		(1ULL << 34)
+#define SNB_SNP_FWD		(1ULL << 35)
+#define SNB_HITM		(1ULL << 36)
+#define SNB_NON_DRAM		(1ULL << 37)
+
+#define SNB_DMND_READ		(SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
+#define SNB_DMND_WRITE		(SNB_DMND_RFO|SNB_LLC_RFO)
+#define SNB_DMND_PREFETCH	(SNB_PF_DATA_RD|SNB_PF_RFO)
+
+#define SNB_SNP_ANY		(SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
+				 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
+				 SNB_HITM)
+
+#define SNB_DRAM_ANY		(SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
+#define SNB_DRAM_REMOTE		(SNB_REMOTE|SNB_SNP_ANY)
+
+#define SNB_L3_ACCESS		SNB_RESP_ANY
+#define SNB_L3_MISS		(SNB_DRAM_ANY|SNB_NON_DRAM)
+
+static __initconst const u64 snb_hw_cache_extra_regs
+				[PERF_COUNT_HW_CACHE_MAX]
+				[PERF_COUNT_HW_CACHE_OP_MAX]
+				[PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [ C(LL  ) ] = {
+	[ C(OP_READ) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
+		[ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_L3_MISS,
+	},
+	[ C(OP_WRITE) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
+		[ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_L3_MISS,
+	},
+	[ C(OP_PREFETCH) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
+		[ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
+	},
+ },
+ [ C(NODE) ] = {
+	[ C(OP_READ) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
+		[ C(RESULT_MISS)   ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
+	},
+	[ C(OP_WRITE) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
+		[ C(RESULT_MISS)   ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
+	},
+	[ C(OP_PREFETCH) ] = {
+		[ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
+		[ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
+	},
+ },
+};
+
 static __initconst const u64 snb_hw_cache_event_ids
 				[PERF_COUNT_HW_CACHE_MAX]
 				[PERF_COUNT_HW_CACHE_OP_MAX]
@@ -235,16 +313,16 @@ static __initconst const u64 snb_hw_cache_event_ids
  },
  [ C(NODE) ] = {
 	[ C(OP_READ) ] = {
-		[ C(RESULT_ACCESS) ] = -1,
-		[ C(RESULT_MISS)   ] = -1,
+		[ C(RESULT_ACCESS) ] = 0x01b7,
+		[ C(RESULT_MISS)   ] = 0x01b7,
 	},
 	[ C(OP_WRITE) ] = {
-		[ C(RESULT_ACCESS) ] = -1,
-		[ C(RESULT_MISS)   ] = -1,
+		[ C(RESULT_ACCESS) ] = 0x01b7,
+		[ C(RESULT_MISS)   ] = 0x01b7,
 	},
 	[ C(OP_PREFETCH) ] = {
-		[ C(RESULT_ACCESS) ] = -1,
-		[ C(RESULT_MISS)   ] = -1,
+		[ C(RESULT_ACCESS) ] = 0x01b7,
+		[ C(RESULT_MISS)   ] = 0x01b7,
 	},
  },
 
@@ -1964,6 +2042,8 @@ __init int intel_pmu_init(void)
 	case 58: /* IvyBridge */
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
+		memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
+		       sizeof(hw_cache_extra_regs));
 
 		intel_pmu_lbr_init_snb();
 

^ permalink raw reply related	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2012-07-26 15:13 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2012-07-17  9:27 [PATCH] perf/x86: Fix LLC-* and node-* events on Intel SandyBridge Yan, Zheng
2012-07-20 16:48 ` Peter Zijlstra
2012-07-22 11:43   ` Yan, Zheng 
2012-07-23 12:22     ` Peter Zijlstra
2012-07-26 15:12 ` [tip:perf/core] " tip-bot for Yan, Zheng

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