* [PATCH v1, 1/4] soc: mediatek: mmsys: Add mt8186 mmsys routing table
2022-01-28 12:07 [PATCH v1, 0/4] add display support for mediatek SOC MT8186 Yongqiang Niu
@ 2022-01-28 12:07 ` Yongqiang Niu
2022-01-28 16:16 ` Chun-Kuang Hu
2022-01-28 12:07 ` [PATCH v1, 2/4] soc: mediatek: add mtk mutex support for MT8186 Yongqiang Niu
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Yongqiang Niu @ 2022-01-28 12:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
mt8186 routing registers is different with other Soc
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mt8186-mmsys.h | 113 ++++++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 +++
2 files changed, 124 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8186-mmsys.h
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
new file mode 100644
index 000000000000..7de329f2d729
--- /dev/null
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
+#define __SOC_MEDIATEK_MT8186_MMSYS_H
+
+#define MT8186_MMSYS_OVL_CON 0xF04
+#define MT8186_MMSYS_OVL0_CON_MASK 0x3
+#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
+#define MT8186_OVL0_GO_BLEND BIT(0)
+#define MT8186_OVL0_GO_BG BIT(1)
+#define MT8186_OVL0_2L_GO_BLEND BIT(2)
+#define MT8186_OVL0_2L_GO_BG BIT(3)
+#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C
+#define MT8186_RDMA0_SOUT_SEL_MASK 0xF
+#define MT8186_RDMA0_SOUT_TO_DSI0 (0)
+#define MT8186_RDMA0_SOUT_TO_COLOR0 (1)
+#define MT8186_RDMA0_SOUT_TO_DPI0 (2)
+#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14
+#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF
+#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0)
+#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3)
+#define MT8186_DISP_OVL0_MOUT_EN 0xF18
+#define MT8186_OVL0_MOUT_EN_MASK 0xF
+#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0)
+#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3)
+#define MT8186_DISP_DITHER0_MOUT_EN 0xF20
+#define MT8186_DITHER0_MOUT_EN_MASK 0xF
+#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0)
+#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2)
+#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3)
+#define MT8186_DISP_RDMA0_SEL_IN 0xF28
+#define MT8186_RDMA0_SEL_IN_MASK 0xF
+#define MT8186_RDMA0_FROM_OVL0 0
+#define MT8186_RDMA0_FROM_OVL0_2L 2
+#define MT8186_DISP_DSI0_SEL_IN 0xF30
+#define MT8186_DSI0_SEL_IN_MASK 0xF
+#define MT8186_DSI0_FROM_RDMA0 0
+#define MT8186_DSI0_FROM_DITHER0 1
+#define MT8186_DSI0_FROM_RDMA1 2
+#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C
+#define MT8186_RDMA1_MOUT_EN_MASK 0xF
+#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0)
+#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2)
+#define MT8186_DISP_RDMA1_SEL_IN 0xF40
+#define MT8186_RDMA1_SEL_IN_MASK 0xF
+#define MT8186_RDMA1_FROM_OVL0 0
+#define MT8186_RDMA1_FROM_OVL0_2L 2
+#define MT8186_RDMA1_FROM_DITHER0 3
+#define MT8186_DISP_DPI0_SEL_IN 0xF44
+#define MT8186_DPI0_SEL_IN_MASK 0xF
+#define MT8186_DPI0_FROM_RDMA1 0
+#define MT8186_DPI0_FROM_DITHER0 1
+#define MT8186_DPI0_FROM_RDMA0 2
+
+static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
+ MT8186_OVL0_MOUT_TO_RDMA0
+ },
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
+ MT8186_RDMA0_FROM_OVL0
+ },
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
+ MT8186_OVL0_GO_BLEND
+ },
+ {
+ DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
+ MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
+ MT8186_RDMA0_SOUT_TO_COLOR0
+ },
+ {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
+ MT8186_DITHER0_MOUT_TO_DSI0,
+ },
+ {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
+ MT8186_DSI0_FROM_DITHER0
+ },
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
+ MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
+ MT8186_OVL0_2L_MOUT_TO_RDMA1
+ },
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
+ MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
+ MT8186_RDMA1_FROM_OVL0_2L
+ },
+ {
+ DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
+ MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
+ MT8186_OVL0_2L_GO_BLEND
+ },
+ {
+ DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
+ MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
+ MT8186_RDMA1_MOUT_TO_DPI0_SEL
+ },
+ {
+ DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
+ MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
+ MT8186_DPI0_FROM_RDMA1
+ },
+};
+
+#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 1e448f1ffefb..0da25069ffb3 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -15,6 +15,7 @@
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
#include "mt8183-mmsys.h"
+#include "mt8186-mmsys.h"
#include "mt8192-mmsys.h"
#include "mt8365-mmsys.h"
@@ -56,6 +57,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
+ .clk_driver = "clk-mt8186-mm",
+ .routes = mmsys_mt8186_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.clk_driver = "clk-mt8192-mm",
.routes = mmsys_mt8192_routing_table,
@@ -242,6 +249,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8186-mmsys",
+ .data = &mt8186_mmsys_driver_data,
+ },
{
.compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data,
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v1, 1/4] soc: mediatek: mmsys: Add mt8186 mmsys routing table
2022-01-28 12:07 ` [PATCH v1, 1/4] soc: mediatek: mmsys: Add mt8186 mmsys routing table Yongqiang Niu
@ 2022-01-28 16:16 ` Chun-Kuang Hu
0 siblings, 0 replies; 9+ messages in thread
From: Chun-Kuang Hu @ 2022-01-28 16:16 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel,
David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent,
Dennis YC Hsieh, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2022年1月28日 週五 下午8:07寫道：
>
> mt8186 routing registers is different with other Soc
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mt8186-mmsys.h | 113 ++++++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 11 +++
> 2 files changed, 124 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8186-mmsys.h
>
> diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
> new file mode 100644
> index 000000000000..7de329f2d729
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8186-mmsys.h
> @@ -0,0 +1,113 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +
> +#ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
> +#define __SOC_MEDIATEK_MT8186_MMSYS_H
> +
> +#define MT8186_MMSYS_OVL_CON 0xF04
> +#define MT8186_MMSYS_OVL0_CON_MASK 0x3
> +#define MT8186_MMSYS_OVL0_2L_CON_MASK 0xC
> +#define MT8186_OVL0_GO_BLEND BIT(0)
> +#define MT8186_OVL0_GO_BG BIT(1)
> +#define MT8186_OVL0_2L_GO_BLEND BIT(2)
> +#define MT8186_OVL0_2L_GO_BG BIT(3)
> +#define MT8186_DISP_RDMA0_SOUT_SEL 0xF0C
> +#define MT8186_RDMA0_SOUT_SEL_MASK 0xF
> +#define MT8186_RDMA0_SOUT_TO_DSI0 (0)
> +#define MT8186_RDMA0_SOUT_TO_COLOR0 (1)
> +#define MT8186_RDMA0_SOUT_TO_DPI0 (2)
> +#define MT8186_DISP_OVL0_2L_MOUT_EN 0xF14
> +#define MT8186_OVL0_2L_MOUT_EN_MASK 0xF
> +#define MT8186_OVL0_2L_MOUT_TO_RDMA0 BIT(0)
> +#define MT8186_OVL0_2L_MOUT_TO_RDMA1 BIT(3)
> +#define MT8186_DISP_OVL0_MOUT_EN 0xF18
> +#define MT8186_OVL0_MOUT_EN_MASK 0xF
> +#define MT8186_OVL0_MOUT_TO_RDMA0 BIT(0)
> +#define MT8186_OVL0_MOUT_TO_RDMA1 BIT(3)
> +#define MT8186_DISP_DITHER0_MOUT_EN 0xF20
> +#define MT8186_DITHER0_MOUT_EN_MASK 0xF
> +#define MT8186_DITHER0_MOUT_TO_DSI0 BIT(0)
> +#define MT8186_DITHER0_MOUT_TO_RDMA1 BIT(2)
> +#define MT8186_DITHER0_MOUT_TO_DPI0 BIT(3)
> +#define MT8186_DISP_RDMA0_SEL_IN 0xF28
> +#define MT8186_RDMA0_SEL_IN_MASK 0xF
> +#define MT8186_RDMA0_FROM_OVL0 0
> +#define MT8186_RDMA0_FROM_OVL0_2L 2
> +#define MT8186_DISP_DSI0_SEL_IN 0xF30
> +#define MT8186_DSI0_SEL_IN_MASK 0xF
> +#define MT8186_DSI0_FROM_RDMA0 0
> +#define MT8186_DSI0_FROM_DITHER0 1
> +#define MT8186_DSI0_FROM_RDMA1 2
> +#define MT8186_DISP_RDMA1_MOUT_EN 0xF3C
> +#define MT8186_RDMA1_MOUT_EN_MASK 0xF
> +#define MT8186_RDMA1_MOUT_TO_DPI0_SEL BIT(0)
> +#define MT8186_RDMA1_MOUT_TO_DSI0_SEL BIT(2)
> +#define MT8186_DISP_RDMA1_SEL_IN 0xF40
> +#define MT8186_RDMA1_SEL_IN_MASK 0xF
> +#define MT8186_RDMA1_FROM_OVL0 0
> +#define MT8186_RDMA1_FROM_OVL0_2L 2
> +#define MT8186_RDMA1_FROM_DITHER0 3
> +#define MT8186_DISP_DPI0_SEL_IN 0xF44
> +#define MT8186_DPI0_SEL_IN_MASK 0xF
> +#define MT8186_DPI0_FROM_RDMA1 0
> +#define MT8186_DPI0_FROM_DITHER0 1
> +#define MT8186_DPI0_FROM_RDMA0 2
> +
> +static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
> + MT8186_OVL0_MOUT_TO_RDMA0
> + },
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
> + MT8186_RDMA0_FROM_OVL0
> + },
> + {
> + DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
> + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
> + MT8186_OVL0_GO_BLEND
> + },
> + {
> + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
> + MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
> + MT8186_RDMA0_SOUT_TO_COLOR0
> + },
> + {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
> + MT8186_DITHER0_MOUT_TO_DSI0,
> + },
> + {
> + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
> + MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
> + MT8186_DSI0_FROM_DITHER0
> + },
> + {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
> + MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
> + MT8186_OVL0_2L_MOUT_TO_RDMA1
> + },
> + {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
> + MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
> + MT8186_RDMA1_FROM_OVL0_2L
> + },
> + {
> + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
> + MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
> + MT8186_OVL0_2L_GO_BLEND
> + },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
> + MT8186_RDMA1_MOUT_TO_DPI0_SEL
> + },
> + {
> + DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
> + MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
> + MT8186_DPI0_FROM_RDMA1
> + },
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 1e448f1ffefb..0da25069ffb3 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -15,6 +15,7 @@
> #include "mtk-mmsys.h"
> #include "mt8167-mmsys.h"
> #include "mt8183-mmsys.h"
> +#include "mt8186-mmsys.h"
> #include "mt8192-mmsys.h"
> #include "mt8365-mmsys.h"
>
> @@ -56,6 +57,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> };
>
> +static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> + .clk_driver = "clk-mt8186-mm",
> + .routes = mmsys_mt8186_routing_table,
> + .num_routes = ARRAY_SIZE(mmsys_mt8186_routing_table),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .clk_driver = "clk-mt8192-mm",
> .routes = mmsys_mt8192_routing_table,
> @@ -242,6 +249,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data,
> },
> + {
> + .compatible = "mediatek,mt8186-mmsys",
Add "mediatek,mt8186-mmsys" to binding document.
Regards,
Chun-Kuang.
> + .data = &mt8186_mmsys_driver_data,
> + },
> {
> .compatible = "mediatek,mt8192-mmsys",
> .data = &mt8192_mmsys_driver_data,
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1, 2/4] soc: mediatek: add mtk mutex support for MT8186
2022-01-28 12:07 [PATCH v1, 0/4] add display support for mediatek SOC MT8186 Yongqiang Niu
2022-01-28 12:07 ` [PATCH v1, 1/4] soc: mediatek: mmsys: Add mt8186 mmsys routing table Yongqiang Niu
@ 2022-01-28 12:07 ` Yongqiang Niu
2022-01-28 16:17 ` Chun-Kuang Hu
2022-01-28 12:07 ` [PATCH v1, 3/4] drm/mediatek: split postmask component Yongqiang Niu
2022-01-28 12:07 ` [PATCH v1, 4/4] drm/mediatek: add mt8186 display support Yongqiang Niu
3 siblings, 1 reply; 9+ messages in thread
From: Yongqiang Niu @ 2022-01-28 12:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
Add mtk mutex support for MT8186 SoC.
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 45 ++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2ca55bb5a8be..ebd95fd0f36e 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -26,6 +26,23 @@
#define INT_MUTEX BIT(1)
+#define MT8186_MUTEX_MOD_DISP_OVL0 0
+#define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
+#define MT8186_MUTEX_MOD_DISP_RDMA0 2
+#define MT8186_MUTEX_MOD_DISP_COLOR0 4
+#define MT8186_MUTEX_MOD_DISP_CCORR0 5
+#define MT8186_MUTEX_MOD_DISP_AAL0 7
+#define MT8186_MUTEX_MOD_DISP_GAMMA0 8
+#define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
+#define MT8186_MUTEX_MOD_DISP_DITHER0 10
+#define MT8186_MUTEX_MOD_DISP_RDMA1 17
+
+#define MT8186_MUTEX_SOF_SINGLE_MODE 0
+#define MT8186_MUTEX_SOF_DSI0 1
+#define MT8186_MUTEX_SOF_DPI0 2
+#define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
+#define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
+
#define MT8167_MUTEX_MOD_DISP_PWM 1
#define MT8167_MUTEX_MOD_DISP_OVL0 6
#define MT8167_MUTEX_MOD_DISP_OVL1 7
@@ -226,6 +243,19 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
+static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
+ [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
+ [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
+};
+
static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
@@ -264,6 +294,12 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
};
+static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -301,6 +337,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.no_clk = true,
};
+static const struct mtk_mutex_data mt8186_mutex_driver_data = {
+ .mutex_mod = mt8186_mutex_mod,
+ .mutex_sof = mt8186_mutex_sof,
+ .mutex_mod_reg = MT8183_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8183_MUTEX0_SOF0,
+};
+
static const struct mtk_mutex_data mt8192_mutex_driver_data = {
.mutex_mod = mt8192_mutex_mod,
.mutex_sof = mt8183_mutex_sof,
@@ -540,6 +583,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8173_mutex_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_mutex_driver_data},
+ { .compatible = "mediatek,mt8186-disp-mutex",
+ .data = &mt8186_mutex_driver_data},
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = &mt8192_mutex_driver_data},
{},
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v1, 2/4] soc: mediatek: add mtk mutex support for MT8186
2022-01-28 12:07 ` [PATCH v1, 2/4] soc: mediatek: add mtk mutex support for MT8186 Yongqiang Niu
@ 2022-01-28 16:17 ` Chun-Kuang Hu
0 siblings, 0 replies; 9+ messages in thread
From: Chun-Kuang Hu @ 2022-01-28 16:17 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel,
David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent,
Dennis YC Hsieh, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2022年1月28日 週五 下午8:07寫道：
>
> Add mtk mutex support for MT8186 SoC.
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 45 ++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2ca55bb5a8be..ebd95fd0f36e 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -26,6 +26,23 @@
>
> #define INT_MUTEX BIT(1)
>
> +#define MT8186_MUTEX_MOD_DISP_OVL0 0
> +#define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
> +#define MT8186_MUTEX_MOD_DISP_RDMA0 2
> +#define MT8186_MUTEX_MOD_DISP_COLOR0 4
> +#define MT8186_MUTEX_MOD_DISP_CCORR0 5
> +#define MT8186_MUTEX_MOD_DISP_AAL0 7
> +#define MT8186_MUTEX_MOD_DISP_GAMMA0 8
> +#define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
> +#define MT8186_MUTEX_MOD_DISP_DITHER0 10
> +#define MT8186_MUTEX_MOD_DISP_RDMA1 17
> +
> +#define MT8186_MUTEX_SOF_SINGLE_MODE 0
> +#define MT8186_MUTEX_SOF_DSI0 1
> +#define MT8186_MUTEX_SOF_DPI0 2
> +#define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
> +#define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
> +
> #define MT8167_MUTEX_MOD_DISP_PWM 1
> #define MT8167_MUTEX_MOD_DISP_OVL0 6
> #define MT8167_MUTEX_MOD_DISP_OVL1 7
> @@ -226,6 +243,19 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> };
>
> +static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
> + [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
> +};
> +
> static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
> [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
> @@ -264,6 +294,12 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> };
>
> +static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> + [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
> + [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -301,6 +337,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> .no_clk = true,
> };
>
> +static const struct mtk_mutex_data mt8186_mutex_driver_data = {
> + .mutex_mod = mt8186_mutex_mod,
> + .mutex_sof = mt8186_mutex_sof,
> + .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> +};
> +
> static const struct mtk_mutex_data mt8192_mutex_driver_data = {
> .mutex_mod = mt8192_mutex_mod,
> .mutex_sof = mt8183_mutex_sof,
> @@ -540,6 +583,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
> .data = &mt8173_mutex_driver_data},
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = &mt8183_mutex_driver_data},
> + { .compatible = "mediatek,mt8186-disp-mutex",
Add "mediatek,mt8186-disp-mutex" to binding document.
Regards,
Chun-Kuang.
> + .data = &mt8186_mutex_driver_data},
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = &mt8192_mutex_driver_data},
> {},
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1, 3/4] drm/mediatek: split postmask component
2022-01-28 12:07 [PATCH v1, 0/4] add display support for mediatek SOC MT8186 Yongqiang Niu
2022-01-28 12:07 ` [PATCH v1, 1/4] soc: mediatek: mmsys: Add mt8186 mmsys routing table Yongqiang Niu
2022-01-28 12:07 ` [PATCH v1, 2/4] soc: mediatek: add mtk mutex support for MT8186 Yongqiang Niu
@ 2022-01-28 12:07 ` Yongqiang Niu
2022-01-28 16:34 ` Chun-Kuang Hu
2022-01-28 12:07 ` [PATCH v1, 4/4] drm/mediatek: add mt8186 display support Yongqiang Niu
3 siblings, 1 reply; 9+ messages in thread
From: Yongqiang Niu @ 2022-01-28 12:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
add postmask private data for differnt soc support
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 155 +++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 +---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
6 files changed, 170 insertions(+), 27 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..f26fe646ee2a 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -5,6 +5,7 @@ mediatek-drm-y := mtk_disp_aal.o \
mtk_disp_color.o \
mtk_disp_gamma.o \
mtk_disp_ovl.o \
+ mtk_disp_postmask.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
mtk_drm_ddp_comp.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..f4c21195c3ea 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -81,6 +81,14 @@ void mtk_ovl_enable_vblank(struct device *dev,
void *vblank_cb_data);
void mtk_ovl_disable_vblank(struct device *dev);
+int mtk_postmask_clk_enable(struct device *dev);
+void mtk_postmask_clk_disable(struct device *dev);
+void mtk_postmask_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_postmask_start(struct device *dev);
+void mtk_postmask_stop(struct device *dev);
+
void mtk_rdma_bypass_shadow(struct device *dev);
int mtk_rdma_clk_enable(struct device *dev);
void mtk_rdma_clk_disable(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
new file mode 100644
index 000000000000..fc04b445c2ed
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_disp_drv.h"
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+
+#define DISP_POSTMASK_EN 0x0000
+#define POSTMASK_EN BIT(0)
+#define DISP_POSTMASK_CFG 0x0020
+#define POSTMASK_RELAY_MODE BIT(0)
+#define DISP_POSTMASK_SIZE 0x0030
+
+struct mtk_disp_postmask_data {
+ u32 reserved;
+};
+
+/*
+ * struct mtk_disp_postmask - DISP_POSTMASK driver structure
+ */
+struct mtk_disp_postmask {
+ struct clk *clk;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_reg;
+ const struct mtk_disp_postmask_data *data;
+};
+
+int mtk_postmask_clk_enable(struct device *dev)
+{
+ struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
+
+ return clk_prepare_enable(postmask->clk);
+}
+
+void mtk_postmask_clk_disable(struct device *dev)
+{
+ struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(postmask->clk);
+}
+
+void mtk_postmask_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
+
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, &postmask->cmdq_reg, postmask->regs,
+ DISP_POSTMASK_SIZE);
+ mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &postmask->cmdq_reg,
+ postmask->regs, DISP_POSTMASK_CFG);
+}
+
+void mtk_postmask_start(struct device *dev)
+{
+ struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
+
+ writel(POSTMASK_EN, postmask->regs + DISP_POSTMASK_EN);
+}
+
+void mtk_postmask_stop(struct device *dev)
+{
+ struct mtk_disp_postmask *postmask = dev_get_drvdata(dev);
+
+ writel_relaxed(0x0, postmask->regs + DISP_POSTMASK_EN);
+}
+
+static int mtk_disp_postmask_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_postmask_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_postmask_component_ops = {
+ .bind = mtk_disp_postmask_bind,
+ .unbind = mtk_disp_postmask_unbind,
+};
+
+static int mtk_disp_postmask_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_disp_postmask *priv;
+ struct resource *res;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get postmask clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap postmask\n");
+ return PTR_ERR(priv->regs);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ priv->data = of_device_get_match_data(dev);
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_postmask_component_ops);
+ if (ret)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_postmask_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_postmask_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_postmask_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8192-disp-postmask"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_postmask_driver_dt_match);
+
+struct platform_driver mtk_disp_postmask_driver = {
+ .probe = mtk_disp_postmask_probe,
+ .remove = mtk_disp_postmask_remove,
+ .driver = {
+ .name = "mediatek-disp-postmask",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_postmask_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index b4b682bc1991..e02fc8dcad91 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -199,31 +199,6 @@ static void mtk_od_start(struct device *dev)
writel(1, priv->regs + DISP_REG_OD_EN);
}
-static void mtk_postmask_config(struct device *dev, unsigned int w,
- unsigned int h, unsigned int vrefresh,
- unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
- mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
- DISP_REG_POSTMASK_SIZE);
- mtk_ddp_write(cmdq_pkt, POSTMASK_RELAY_MODE, &priv->cmdq_reg,
- priv->regs, DISP_REG_POSTMASK_CFG);
-}
-
-static void mtk_postmask_start(struct device *dev)
-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
- writel(POSTMASK_EN, priv->regs + DISP_REG_POSTMASK_EN);
-}
-
-static void mtk_postmask_stop(struct device *dev)
-{
- struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
-
- writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
-}
static void mtk_ufoe_start(struct device *dev)
{
@@ -308,8 +283,8 @@ static const struct mtk_ddp_comp_funcs ddp_ovl = {
};
static const struct mtk_ddp_comp_funcs ddp_postmask = {
- .clk_enable = mtk_ddp_clk_enable,
- .clk_disable = mtk_ddp_clk_disable,
+ .clk_enable = mtk_postmask_clk_enable,
+ .clk_disable = mtk_postmask_clk_disable,
.config = mtk_postmask_config,
.start = mtk_postmask_start,
.stop = mtk_postmask_stop,
@@ -510,6 +485,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_GAMMA ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
+ type == MTK_DISP_POSTMASK ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DPI ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 56ff8c57ef8f..6efb423ccc92 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -609,6 +609,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_GAMMA ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
+ comp_type == MTK_DISP_POSTMASK ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
@@ -709,6 +710,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_color_driver,
&mtk_disp_gamma_driver,
&mtk_disp_ovl_driver,
+ &mtk_disp_postmask_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
&mtk_drm_platform_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..c1e676aebe57 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_ccorr_driver;
extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
extern struct platform_driver mtk_disp_ovl_driver;
+extern struct platform_driver mtk_disp_postmask_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v1, 3/4] drm/mediatek: split postmask component
2022-01-28 12:07 ` [PATCH v1, 3/4] drm/mediatek: split postmask component Yongqiang Niu
@ 2022-01-28 16:34 ` Chun-Kuang Hu
0 siblings, 0 replies; 9+ messages in thread
From: Chun-Kuang Hu @ 2022-01-28 16:34 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel,
David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent,
Dennis YC Hsieh, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2022年1月28日 週五 下午8:07寫道：
>
> add postmask private data for differnt soc support
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_postmask.c | 155 +++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 30 +---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 6 files changed, 170 insertions(+), 27 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_postmask.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 29098d7c8307..f26fe646ee2a 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -5,6 +5,7 @@ mediatek-drm-y := mtk_disp_aal.o \
> mtk_disp_color.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> + mtk_disp_postmask.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> mtk_drm_ddp_comp.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index 86c3068894b1..f4c21195c3ea 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -81,6 +81,14 @@ void mtk_ovl_enable_vblank(struct device *dev,
> void *vblank_cb_data);
> void mtk_ovl_disable_vblank(struct device *dev);
>
> +int mtk_postmask_clk_enable(struct device *dev);
> +void mtk_postmask_clk_disable(struct device *dev);
> +void mtk_postmask_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_postmask_start(struct device *dev);
> +void mtk_postmask_stop(struct device *dev);
> +
> void mtk_rdma_bypass_shadow(struct device *dev);
> int mtk_rdma_clk_enable(struct device *dev);
> void mtk_rdma_clk_disable(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_postmask.c b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> new file mode 100644
> index 000000000000..fc04b445c2ed
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_postmask.c
> @@ -0,0 +1,155 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
2022
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_disp_drv.h"
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +
> +#define DISP_POSTMASK_EN 0x0000
> +#define POSTMASK_EN BIT(0)
> +#define DISP_POSTMASK_CFG 0x0020
> +#define POSTMASK_RELAY_MODE BIT(0)
> +#define DISP_POSTMASK_SIZE 0x0030
I think you should 'move' these definition not 'copy' them, so
remember to remove them in mtk_drm_ddp_comp.c
Regards,
Chun-Kuang.
> +
> +struct mtk_disp_postmask_data {
> + u32 reserved;
> +};
> +
> +/*
> + * struct mtk_disp_postmask - DISP_POSTMASK driver structure
> + */
> +struct mtk_disp_postmask {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + const struct mtk_disp_postmask_data *data;
> +};
> +
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v1, 4/4] drm/mediatek: add mt8186 display support
2022-01-28 12:07 [PATCH v1, 0/4] add display support for mediatek SOC MT8186 Yongqiang Niu
` (2 preceding siblings ...)
2022-01-28 12:07 ` [PATCH v1, 3/4] drm/mediatek: split postmask component Yongqiang Niu
@ 2022-01-28 12:07 ` Yongqiang Niu
2022-01-28 16:19 ` Chun-Kuang Hu
3 siblings, 1 reply; 9+ messages in thread
From: Yongqiang Niu @ 2022-01-28 12:07 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie,
Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent,
Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 39 ++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6efb423ccc92..754b1be25d0d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -158,6 +158,24 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8186_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_POSTMASK0,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSI0,
+};
+
+static const enum mtk_ddp_comp_id mt8186_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL_2L0,
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_DPI0,
+};
+
static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL_2L0,
@@ -221,6 +239,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
+ .main_path = mt8186_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
+ .ext_path = mt8186_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
+};
+
static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
.main_path = mt8192_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -463,6 +488,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8186-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8192-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-od",
@@ -475,14 +502,20 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl",
.data = (void *)MTK_DISP_OVL },
+ { .compatible = "mediatek,mt8186-disp-ovl",
+ .data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8192-disp-ovl",
.data = (void *)MTK_DISP_OVL },
{ .compatible = "mediatek,mt8183-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
+ { .compatible = "mediatek,mt8186-disp-ovl-2l",
+ .data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt8192-disp-ovl-2l",
.data = (void *)MTK_DISP_OVL_2L },
{ .compatible = "mediatek,mt8192-disp-postmask",
.data = (void *)MTK_DISP_POSTMASK },
+ { .compatible = "mediatek,mt8186-disp-postmask",
+ .data = (void *)MTK_DISP_POSTMASK},
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8167-disp-pwm",
@@ -511,12 +544,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt8183-dpi",
.data = (void *)MTK_DPI },
+ { .compatible = "mediatek,mt8186-dpi",
+ .data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt2701-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dsi",
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8183-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8186-dsi",
+ .data = (void *)MTK_DSI },
{ }
};
@@ -533,6 +570,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8173_mmsys_driver_data},
{ .compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data},
+ { .compatible = "mediatek,mt8186-mmsys",
+ .data = &mt8186_mmsys_driver_data},
{ .compatible = "mediatek,mt8192-mmsys",
.data = &mt8192_mmsys_driver_data},
{ }
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v1, 4/4] drm/mediatek: add mt8186 display support
2022-01-28 12:07 ` [PATCH v1, 4/4] drm/mediatek: add mt8186 display support Yongqiang Niu
@ 2022-01-28 16:19 ` Chun-Kuang Hu
0 siblings, 0 replies; 9+ messages in thread
From: Chun-Kuang Hu @ 2022-01-28 16:19 UTC (permalink / raw)
To: Yongqiang Niu
Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel,
David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent,
Dennis YC Hsieh, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
DRI Development, Project_Global_Chrome_Upstream_Group,
Hsin-Yi Wang
Hi, Yongqiang:
Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2022年1月28日 週五 下午8:07寫道：
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 39 ++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 6efb423ccc92..754b1be25d0d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -158,6 +158,24 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8186_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_POSTMASK0,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DSI0,
> +};
> +
> +static const enum mtk_ddp_comp_id mt8186_mtk_ddp_ext[] = {
> + DDP_COMPONENT_OVL_2L0,
> + DDP_COMPONENT_RDMA1,
> + DDP_COMPONENT_DPI0,
> +};
> +
> static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
> DDP_COMPONENT_OVL0,
> DDP_COMPONENT_OVL_2L0,
> @@ -221,6 +239,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
> + .main_path = mt8186_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8186_mtk_ddp_main),
> + .ext_path = mt8186_mtk_ddp_ext,
> + .ext_len = ARRAY_SIZE(mt8186_mtk_ddp_ext),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> .main_path = mt8192_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
> @@ -463,6 +488,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8186-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8192-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8173-disp-od",
> @@ -475,14 +502,20 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt8183-disp-ovl",
> .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8186-disp-ovl",
Add "mediatek,mt8186-disp-ovl" to binding document.
> + .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt8192-disp-ovl",
> .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt8183-disp-ovl-2l",
> .data = (void *)MTK_DISP_OVL_2L },
> + { .compatible = "mediatek,mt8186-disp-ovl-2l",
Ditto.
> + .data = (void *)MTK_DISP_OVL_2L },
> { .compatible = "mediatek,mt8192-disp-ovl-2l",
> .data = (void *)MTK_DISP_OVL_2L },
> { .compatible = "mediatek,mt8192-disp-postmask",
> .data = (void *)MTK_DISP_POSTMASK },
> + { .compatible = "mediatek,mt8186-disp-postmask",
Ditto.
> + .data = (void *)MTK_DISP_POSTMASK},
> { .compatible = "mediatek,mt2701-disp-pwm",
> .data = (void *)MTK_DISP_BLS },
> { .compatible = "mediatek,mt8167-disp-pwm",
> @@ -511,12 +544,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8183-dpi",
> .data = (void *)MTK_DPI },
> + { .compatible = "mediatek,mt8186-dpi",
Ditto.
> + .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt2701-dsi",
> .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt8173-dsi",
> .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt8183-dsi",
> .data = (void *)MTK_DSI },
> + { .compatible = "mediatek,mt8186-dsi",
Ditto.
Regards,
Chun-Kuang.
> + .data = (void *)MTK_DSI },
> { }
> };
>
> @@ -533,6 +570,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
> .data = &mt8173_mmsys_driver_data},
> { .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data},
> + { .compatible = "mediatek,mt8186-mmsys",
> + .data = &mt8186_mmsys_driver_data},
> { .compatible = "mediatek,mt8192-mmsys",
> .data = &mt8192_mmsys_driver_data},
> { }
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread