* Re: [PATCH v2] arm64: dts: mt8173: Add gce setting in mmsys and display node
2020-04-09 5:50 [PATCH v2] arm64: dts: mt8173: Add gce setting in mmsys and display node Hsin-Yi Wang
@ 2020-04-09 13:25 ` Enric Balletbo i Serra
2020-04-09 16:08 ` Chun-Kuang Hu
2020-04-13 12:11 ` Matthias Brugger
2 siblings, 0 replies; 4+ messages in thread
From: Enric Balletbo i Serra @ 2020-04-09 13:25 UTC (permalink / raw)
To: Hsin-Yi Wang, linux-arm-kernel
Cc: devicetree, Chun-Kuang Hu, linux-kernel, Rob Herring,
linux-mediatek, Matthias Brugger
Hi Hsin-Yi,
Thanks for sending the patch upstream
On 9/4/20 7:50, Hsin-Yi Wang wrote:
> In order to use GCE function, we need add some informations
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Tested on my Acer Chromebook R13, so
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> ---
> change log:
> v1->v2: align with
> 19d8e335d58a ("dt-binding: gce: remove atomic_exec in mboxes property")
> 60fa8c13ab1a ("drm/mediatek: Move gce event property to mutex device node")
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index ccb8e88a60c5..8337ba42845d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -549,7 +549,7 @@ gce: mailbox@10212000 {
> interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
> clocks = <&infracfg CLK_INFRA_GCE>;
> clock-names = "gce";
> - #mbox-cells = <3>;
> + #mbox-cells = <2>;
> };
>
> mipi_tx0: mipi-dphy@10215000 {
> @@ -916,6 +916,9 @@ mmsys: clock-controller@14000000 {
> assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
> assigned-clock-rates = <400000000>;
> #clock-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> };
>
> mdp_rdma0: rdma@14001000 {
> @@ -996,6 +999,7 @@ ovl0: ovl@1400c000 {
> clocks = <&mmsys CLK_MM_DISP_OVL0>;
> iommus = <&iommu M4U_PORT_DISP_OVL0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> ovl1: ovl@1400d000 {
> @@ -1006,6 +1010,7 @@ ovl1: ovl@1400d000 {
> clocks = <&mmsys CLK_MM_DISP_OVL1>;
> iommus = <&iommu M4U_PORT_DISP_OVL1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> rdma0: rdma@1400e000 {
> @@ -1016,6 +1021,7 @@ rdma0: rdma@1400e000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> rdma1: rdma@1400f000 {
> @@ -1026,6 +1032,7 @@ rdma1: rdma@1400f000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> };
>
> rdma2: rdma@14010000 {
> @@ -1036,6 +1043,7 @@ rdma2: rdma@14010000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> };
>
> wdma0: wdma@14011000 {
> @@ -1046,6 +1054,7 @@ wdma0: wdma@14011000 {
> clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> };
>
> wdma1: wdma@14012000 {
> @@ -1056,6 +1065,7 @@ wdma1: wdma@14012000 {
> clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> };
>
> color0: color@14013000 {
> @@ -1064,6 +1074,7 @@ color0: color@14013000 {
> interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
> };
>
> color1: color@14014000 {
> @@ -1072,6 +1083,7 @@ color1: color@14014000 {
> interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> aal@14015000 {
> @@ -1080,6 +1092,7 @@ aal@14015000 {
> interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_AAL>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> gamma@14016000 {
> @@ -1088,6 +1101,7 @@ gamma@14016000 {
> interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> };
>
> merge@14017000 {
> @@ -1193,6 +1207,8 @@ mutex: mutex@14020000 {
> interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_MUTEX_32K>;
> + mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> + <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> };
>
> larb0: larb@14021000 {
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2] arm64: dts: mt8173: Add gce setting in mmsys and display node
2020-04-09 5:50 [PATCH v2] arm64: dts: mt8173: Add gce setting in mmsys and display node Hsin-Yi Wang
2020-04-09 13:25 ` Enric Balletbo i Serra
@ 2020-04-09 16:08 ` Chun-Kuang Hu
2020-04-13 12:11 ` Matthias Brugger
2 siblings, 0 replies; 4+ messages in thread
From: Chun-Kuang Hu @ 2020-04-09 16:08 UTC (permalink / raw)
To: Hsin-Yi Wang
Cc: Linux ARM, Rob Herring, Matthias Brugger, devicetree,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Chun-Kuang Hu, Enric Balletbo i Serra
Hi, Hsin-Yi:
Hsin-Yi Wang <hsinyi@chromium.org> 於 2020年4月9日 週四 下午1:50寫道：
>
> In order to use GCE function, we need add some informations
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
> change log:
> v1->v2: align with
> 19d8e335d58a ("dt-binding: gce: remove atomic_exec in mboxes property")
> 60fa8c13ab1a ("drm/mediatek: Move gce event property to mutex device node")
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index ccb8e88a60c5..8337ba42845d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -549,7 +549,7 @@ gce: mailbox@10212000 {
> interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
> clocks = <&infracfg CLK_INFRA_GCE>;
> clock-names = "gce";
> - #mbox-cells = <3>;
> + #mbox-cells = <2>;
> };
>
> mipi_tx0: mipi-dphy@10215000 {
> @@ -916,6 +916,9 @@ mmsys: clock-controller@14000000 {
> assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
> assigned-clock-rates = <400000000>;
> #clock-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> };
>
> mdp_rdma0: rdma@14001000 {
> @@ -996,6 +999,7 @@ ovl0: ovl@1400c000 {
> clocks = <&mmsys CLK_MM_DISP_OVL0>;
> iommus = <&iommu M4U_PORT_DISP_OVL0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> ovl1: ovl@1400d000 {
> @@ -1006,6 +1010,7 @@ ovl1: ovl@1400d000 {
> clocks = <&mmsys CLK_MM_DISP_OVL1>;
> iommus = <&iommu M4U_PORT_DISP_OVL1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> rdma0: rdma@1400e000 {
> @@ -1016,6 +1021,7 @@ rdma0: rdma@1400e000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> rdma1: rdma@1400f000 {
> @@ -1026,6 +1032,7 @@ rdma1: rdma@1400f000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> };
>
> rdma2: rdma@14010000 {
> @@ -1036,6 +1043,7 @@ rdma2: rdma@14010000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> };
>
> wdma0: wdma@14011000 {
> @@ -1046,6 +1054,7 @@ wdma0: wdma@14011000 {
> clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> };
>
> wdma1: wdma@14012000 {
> @@ -1056,6 +1065,7 @@ wdma1: wdma@14012000 {
> clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> };
>
> color0: color@14013000 {
> @@ -1064,6 +1074,7 @@ color0: color@14013000 {
> interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
> };
>
> color1: color@14014000 {
> @@ -1072,6 +1083,7 @@ color1: color@14014000 {
> interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> aal@14015000 {
> @@ -1080,6 +1092,7 @@ aal@14015000 {
> interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_AAL>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> gamma@14016000 {
> @@ -1088,6 +1101,7 @@ gamma@14016000 {
> interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> };
>
> merge@14017000 {
> @@ -1193,6 +1207,8 @@ mutex: mutex@14020000 {
> interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_MUTEX_32K>;
> + mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> + <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> };
>
> larb0: larb@14021000 {
> --
> 2.26.0.292.g33ef6b2f38-goog
>
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH v2] arm64: dts: mt8173: Add gce setting in mmsys and display node
2020-04-09 5:50 [PATCH v2] arm64: dts: mt8173: Add gce setting in mmsys and display node Hsin-Yi Wang
2020-04-09 13:25 ` Enric Balletbo i Serra
2020-04-09 16:08 ` Chun-Kuang Hu
@ 2020-04-13 12:11 ` Matthias Brugger
2 siblings, 0 replies; 4+ messages in thread
From: Matthias Brugger @ 2020-04-13 12:11 UTC (permalink / raw)
To: Hsin-Yi Wang, linux-arm-kernel
Cc: Rob Herring, devicetree, linux-mediatek, linux-kernel,
Chun-Kuang Hu, Enric Balletbo i Serra
On 4/9/20 7:50 AM, Hsin-Yi Wang wrote:
> In order to use GCE function, we need add some informations
> into display node (mboxes, mediatek,gce-client-reg, mediatek,gce-events).
>
> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org>
> Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> ---
Applied to v5.7-next/dts64
Thanks!
> change log:
> v1->v2: align with
> 19d8e335d58a ("dt-binding: gce: remove atomic_exec in mboxes property")
> 60fa8c13ab1a ("drm/mediatek: Move gce event property to mutex device node")
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> index ccb8e88a60c5..8337ba42845d 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
> @@ -549,7 +549,7 @@ gce: mailbox@10212000 {
> interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>;
> clocks = <&infracfg CLK_INFRA_GCE>;
> clock-names = "gce";
> - #mbox-cells = <3>;
> + #mbox-cells = <2>;
> };
>
> mipi_tx0: mipi-dphy@10215000 {
> @@ -916,6 +916,9 @@ mmsys: clock-controller@14000000 {
> assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
> assigned-clock-rates = <400000000>;
> #clock-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> };
>
> mdp_rdma0: rdma@14001000 {
> @@ -996,6 +999,7 @@ ovl0: ovl@1400c000 {
> clocks = <&mmsys CLK_MM_DISP_OVL0>;
> iommus = <&iommu M4U_PORT_DISP_OVL0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
> };
>
> ovl1: ovl@1400d000 {
> @@ -1006,6 +1010,7 @@ ovl1: ovl@1400d000 {
> clocks = <&mmsys CLK_MM_DISP_OVL1>;
> iommus = <&iommu M4U_PORT_DISP_OVL1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
> };
>
> rdma0: rdma@1400e000 {
> @@ -1016,6 +1021,7 @@ rdma0: rdma@1400e000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA0>;
> iommus = <&iommu M4U_PORT_DISP_RDMA0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
> };
>
> rdma1: rdma@1400f000 {
> @@ -1026,6 +1032,7 @@ rdma1: rdma@1400f000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> iommus = <&iommu M4U_PORT_DISP_RDMA1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
> };
>
> rdma2: rdma@14010000 {
> @@ -1036,6 +1043,7 @@ rdma2: rdma@14010000 {
> clocks = <&mmsys CLK_MM_DISP_RDMA2>;
> iommus = <&iommu M4U_PORT_DISP_RDMA2>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
> };
>
> wdma0: wdma@14011000 {
> @@ -1046,6 +1054,7 @@ wdma0: wdma@14011000 {
> clocks = <&mmsys CLK_MM_DISP_WDMA0>;
> iommus = <&iommu M4U_PORT_DISP_WDMA0>;
> mediatek,larb = <&larb0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> };
>
> wdma1: wdma@14012000 {
> @@ -1056,6 +1065,7 @@ wdma1: wdma@14012000 {
> clocks = <&mmsys CLK_MM_DISP_WDMA1>;
> iommus = <&iommu M4U_PORT_DISP_WDMA1>;
> mediatek,larb = <&larb4>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
> };
>
> color0: color@14013000 {
> @@ -1064,6 +1074,7 @@ color0: color@14013000 {
> interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_COLOR0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
> };
>
> color1: color@14014000 {
> @@ -1072,6 +1083,7 @@ color1: color@14014000 {
> interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_COLOR1>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
> };
>
> aal@14015000 {
> @@ -1080,6 +1092,7 @@ aal@14015000 {
> interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_AAL>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
> };
>
> gamma@14016000 {
> @@ -1088,6 +1101,7 @@ gamma@14016000 {
> interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_DISP_GAMMA>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
> };
>
> merge@14017000 {
> @@ -1193,6 +1207,8 @@ mutex: mutex@14020000 {
> interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
> power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
> clocks = <&mmsys CLK_MM_MUTEX_32K>;
> + mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>,
> + <CMDQ_EVENT_MUTEX1_STREAM_EOF>;
> };
>
> larb0: larb@14021000 {
>
^ permalink raw reply [flat|nested] 4+ messages in thread