From: Anup Patel <anup@brainfault.org>
To: Marc Zyngier <maz@kernel.org>
Cc: Anup Patel <apatel@ventanamicro.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Atish Patra <atishp@atishpatra.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
linux-riscv <linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/6] irqchip/riscv-intc: Create domain using named fwnode
Date: Sat, 19 Feb 2022 09:08:43 +0530 [thread overview]
Message-ID: <CAAhSdy387r314f=YjvXJCxqxkvjm5q-EBOVu420giFzaVr_NYw@mail.gmail.com> (raw)
In-Reply-To: <063b8a5636d6372f37029946b2c3e0f4@kernel.org>
On Thu, Feb 17, 2022 at 8:42 PM Marc Zyngier <maz@kernel.org> wrote:
>
> On 2022-01-28 05:25, Anup Patel wrote:
> > We should create INTC domain using a synthetic fwnode which will allow
> > drivers (such as RISC-V SBI IPI driver, RISC-V timer driver, RISC-V
> > PMU driver, etc) not having dedicated DT/ACPI node to directly create
> > interrupt mapping for standard local interrupt numbers defined by the
> > RISC-V privileged specification.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> > arch/riscv/include/asm/irq.h | 2 ++
> > arch/riscv/kernel/irq.c | 13 +++++++++++++
> > drivers/clocksource/timer-clint.c | 13 +++++++------
> > drivers/clocksource/timer-riscv.c | 11 ++---------
> > drivers/irqchip/irq-riscv-intc.c | 12 ++++++++++--
> > drivers/irqchip/irq-sifive-plic.c | 19 +++++++++++--------
> > 6 files changed, 45 insertions(+), 25 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/irq.h
> > b/arch/riscv/include/asm/irq.h
> > index e4c435509983..f85ebaf07505 100644
> > --- a/arch/riscv/include/asm/irq.h
> > +++ b/arch/riscv/include/asm/irq.h
> > @@ -12,6 +12,8 @@
> >
> > #include <asm-generic/irq.h>
> >
> > +extern struct fwnode_handle *riscv_intc_fwnode(void);
> > +
> > extern void __init init_IRQ(void);
> >
> > #endif /* _ASM_RISCV_IRQ_H */
> > diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c
> > index 7207fa08d78f..f2fed78ab659 100644
> > --- a/arch/riscv/kernel/irq.c
> > +++ b/arch/riscv/kernel/irq.c
> > @@ -7,9 +7,22 @@
> >
> > #include <linux/interrupt.h>
> > #include <linux/irqchip.h>
> > +#include <linux/irqdomain.h>
> > +#include <linux/module.h>
> > #include <linux/seq_file.h>
> > #include <asm/smp.h>
> >
> > +static struct fwnode_handle *intc_fwnode;
> > +
> > +struct fwnode_handle *riscv_intc_fwnode(void)
> > +{
> > + if (!intc_fwnode)
> > + intc_fwnode = irq_domain_alloc_named_fwnode("RISCV-INTC");
> > +
> > + return intc_fwnode;
> > +}
> > +EXPORT_SYMBOL_GPL(riscv_intc_fwnode);
>
> Why is this created outside of the root interrupt controller driver?
> Furthermore, why do you need to create a new fwnode the first place?
> As far as I can tell, the INTC does have a node, and what you don't
> have is the firmware linkage between PMU (an others) and the INTC.
Fair enough, I will update this patch to not create a synthetic fwnode.
The issue is not with INTC driver. We have other drivers and places
(such as SBI IPI driver, SBI PMU driver, and KVM RISC-V AIA support)
where we don't have a way to locate INTC fwnode.
>
> what you should have instead is something like:
>
> static struct fwnode_handle *(*__get_root_intc_node)(void);
> struct fwnode_handle *riscv_get_root_intc_hwnode(void)
> {
> if (__get_root_intc_node)
> return __get_root_intc_node();
>
> return NULL;
> }
>
> and the corresponding registration interface.
Thanks, I will follow this suggestion. This is a much better approach
and it will avoid touching existing drivers.
>
> But either way, something breaks: the INTC has one node per CPU, and
> expect one irqdomain per CPU. Having a single fwnode completely breaks
> the INTC driver (and probably the irqdomain list, as we don't check for
> duplicate entries).
>
> > diff --git a/drivers/irqchip/irq-riscv-intc.c
> > b/drivers/irqchip/irq-riscv-intc.c
> > index b65bd8878d4f..26ed62c11768 100644
> > --- a/drivers/irqchip/irq-riscv-intc.c
> > +++ b/drivers/irqchip/irq-riscv-intc.c
> > @@ -112,8 +112,16 @@ static int __init riscv_intc_init(struct
> > device_node *node,
> > if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
> > return 0;
> >
> > - intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
> > - &riscv_intc_domain_ops, NULL);
> > + /*
> > + * Create INTC domain using a synthetic fwnode which will allow
> > + * drivers (such as RISC-V SBI IPI driver, RISC-V timer driver,
> > + * RISC-V PMU driver, etc) not having dedicated DT/ACPI node to
> > + * directly create interrupt mapping for standard local interrupt
> > + * numbers defined by the RISC-V privileged specification.
> > + */
> > + intc_domain = irq_domain_create_linear(riscv_intc_fwnode(),
> > + BITS_PER_LONG,
> > + &riscv_intc_domain_ops, NULL);
>
> This is what I'm talking about. It is simply broken. So either you don't
> need a per-CPU node (and the DT was bad the first place), or you
> absolutely need
> one (and the whole 'well-known/default domain' doesn't work at all).
>
> Either way, this patch is plain wrong.
Okay, I will update this patch with the new approach which you suggested.
Regards,
Anup
>
>
> M.
> --
> Jazz is not dead. It just smells funny...
next prev parent reply other threads:[~2022-02-19 3:39 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-28 5:24 [PATCH v2 0/6] RISC-V IPI Improvements Anup Patel
2022-01-28 5:25 ` [PATCH v2 1/6] RISC-V: Clear SIP bit only when using SBI IPI operations Anup Patel
2022-01-28 5:25 ` [PATCH v2 2/6] irqchip/riscv-intc: Create domain using named fwnode Anup Patel
2022-02-17 15:12 ` Marc Zyngier
2022-02-19 3:38 ` Anup Patel [this message]
2022-02-19 9:32 ` Marc Zyngier
2022-02-19 13:03 ` Anup Patel
2022-02-21 9:07 ` Marc Zyngier
2022-02-21 9:38 ` Anup Patel
2022-02-19 14:51 ` Jessica Clarke
2022-02-21 9:25 ` Marc Zyngier
2022-02-21 9:44 ` Anup Patel
2022-01-28 5:25 ` [PATCH v2 3/6] RISC-V: Treat IPIs as normal Linux IRQs Anup Patel
2022-01-28 5:25 ` [PATCH v2 4/6] RISC-V: Allow marking IPIs as suitable for remote FENCEs Anup Patel
2022-01-28 5:25 ` [PATCH v2 5/6] RISC-V: Use IPIs for remote TLB flush when possible Anup Patel
2022-01-28 5:25 ` [PATCH v2 6/6] RISC-V: Use IPIs for remote icache " Anup Patel
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