From: Huacai Chen <chenhc@lemote.com>
To: Tiezhu Yang <yangtiezhu@loongson.cn>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
"open list:MIPS" <linux-mips@vger.kernel.org>,
LKML <linux-kernel@vger.kernel.org>,
Xuefeng Li <lixuefeng@loongson.cn>
Subject: Re: [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3
Date: Thu, 5 Nov 2020 13:57:53 +0800 [thread overview]
Message-ID: <CAAhV-H62Ft_mPBY4UaM0vbd70VVgYGnQW5E0n-y8SPHKftU8UQ@mail.gmail.com> (raw)
In-Reply-To: <e999986a-8236-752a-8b17-353bb87fc521@loongson.cn>
Hi, Tiezhu,
On Wed, Nov 4, 2020 at 11:51 AM Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
>
> On 11/04/2020 10:00 AM, Huacai Chen wrote:
> > Hi, Tiezhu,
> >
> > On Tue, Nov 3, 2020 at 3:13 PM Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
> >> The field LPA of CP0_CONFIG3 register is read only for Loongson64, so the
> >> write operations are meaningless, remove them.
> >>
> >> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> >> ---
> >>
> >> v2: No changes
> >> v3: No changes
> >>
> >> arch/mips/include/asm/mach-loongson64/kernel-entry-init.h | 8 --------
> >> arch/mips/loongson64/numa.c | 3 ---
> >> 2 files changed, 11 deletions(-)
> >>
> >> diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> >> index 87a5bfb..e4d77f4 100644
> >> --- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> >> +++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> >> @@ -19,10 +19,6 @@
> >> .macro kernel_entry_setup
> >> .set push
> >> .set mips64
> >> - /* Set LPA on LOONGSON3 config3 */
> >> - mfc0 t0, CP0_CONFIG3
> >> - or t0, (0x1 << 7)
> >> - mtc0 t0, CP0_CONFIG3
> > Sorry for the late response, I have the same worry as Jiaxun. As you
> > know, Loongson's user manuals are not always correct, but the original
> > code comes from Loongson are usually better. So, my opinion is "Don't
> > change it if it doesn't break anything".
>
> Hi Huacai,
>
> Thanks for your reply, I have confirmed by Loongson user manuals and
> hardware designers, CP0_CONFIG3 register is read only.
>
> Without this patch, the related kernel code is meaningless, with
> this patch, it can reflect the reality.
>
> Thanks,
> Tiezhu
Then you should at least test your code on Loongson-3A R1 two way machine.
Huacai
>
> >
> > Huacai
> >
> >> /* Set ELPA on LOONGSON3 pagegrain */
> >> mfc0 t0, CP0_PAGEGRAIN
> >> or t0, (0x1 << 29)
> >> @@ -54,10 +50,6 @@
> >> .macro smp_slave_setup
> >> .set push
> >> .set mips64
> >> - /* Set LPA on LOONGSON3 config3 */
> >> - mfc0 t0, CP0_CONFIG3
> >> - or t0, (0x1 << 7)
> >> - mtc0 t0, CP0_CONFIG3
> >> /* Set ELPA on LOONGSON3 pagegrain */
> >> mfc0 t0, CP0_PAGEGRAIN
> >> or t0, (0x1 << 29)
> >> diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
> >> index cf9459f..c7e3cced 100644
> >> --- a/arch/mips/loongson64/numa.c
> >> +++ b/arch/mips/loongson64/numa.c
> >> @@ -40,9 +40,6 @@ static void enable_lpa(void)
> >> unsigned long value;
> >>
> >> value = __read_32bit_c0_register($16, 3);
> >> - value |= 0x00000080;
> >> - __write_32bit_c0_register($16, 3, value);
> >> - value = __read_32bit_c0_register($16, 3);
> >> pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value);
> >>
> >> value = __read_32bit_c0_register($5, 1);
> >> --
> >> 2.1.0
> >>
>
next prev parent reply other threads:[~2020-11-05 5:58 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-03 7:11 [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3 Tiezhu Yang
2020-11-04 2:00 ` Huacai Chen
2020-11-04 3:50 ` Tiezhu Yang
2020-11-05 5:57 ` Huacai Chen [this message]
2020-11-05 9:05 ` Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 2/6] MIPS: Loongson64: Set the field ELPA of CP0_PAGEGRAIN only once Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 3/6] MIPS: Loongson64: Set IPI_Enable register per core by itself Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 4/6] MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator Tiezhu Yang
2020-11-04 6:31 ` Jinyang He
2020-11-04 7:04 ` Jiaxun Yang
2020-11-04 7:18 ` Jinyang He
2020-11-03 7:12 ` [PATCH v3 6/6] MIPS: Loongson64: Move decode_cpucfg() to loongson_regs.h Tiezhu Yang
2020-11-11 23:05 ` Thomas Bogendoerfer
2020-11-11 23:04 ` [PATCH v3 0/6] Modify some registers operations and move " Thomas Bogendoerfer
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