* [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h
@ 2020-11-03 7:11 Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3 Tiezhu Yang
` (6 more replies)
0 siblings, 7 replies; 16+ messages in thread
From: Tiezhu Yang @ 2020-11-03 7:11 UTC (permalink / raw)
To: Thomas Bogendoerfer, Huacai Chen, Jiaxun Yang
Cc: linux-mips, linux-kernel, Xuefeng Li
v2: Add some callbacks in csr_ipi probe() for patch #4
v3: Update the commit message and comment for patch #5
Tiezhu Yang (6):
MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3
MIPS: Loongson64: Set the field ELPA of CP0_PAGEGRAIN only once
MIPS: Loongson64: Set IPI_Enable register per core by itself
MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU
MIPS: Loongson64: SMP: Fix up play_dead jump indicator
MIPS: Loongson64: Move decode_cpucfg() to loongson_regs.h
.../asm/mach-loongson64/kernel-entry-init.h | 8 --
.../include/asm/mach-loongson64/loongson_regs.h | 34 ++++++
arch/mips/kernel/cpu-probe.c | 31 +-----
arch/mips/loongson64/numa.c | 20 +---
arch/mips/loongson64/smp.c | 123 +++++++++++++++++----
5 files changed, 136 insertions(+), 80 deletions(-)
--
2.1.0
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3
2020-11-03 7:11 [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h Tiezhu Yang
@ 2020-11-03 7:12 ` Tiezhu Yang
2020-11-04 2:00 ` Huacai Chen
2020-11-03 7:12 ` [PATCH v3 2/6] MIPS: Loongson64: Set the field ELPA of CP0_PAGEGRAIN only once Tiezhu Yang
` (5 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Tiezhu Yang @ 2020-11-03 7:12 UTC (permalink / raw)
To: Thomas Bogendoerfer, Huacai Chen, Jiaxun Yang
Cc: linux-mips, linux-kernel, Xuefeng Li
The field LPA of CP0_CONFIG3 register is read only for Loongson64, so the
write operations are meaningless, remove them.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
v2: No changes
v3: No changes
arch/mips/include/asm/mach-loongson64/kernel-entry-init.h | 8 --------
arch/mips/loongson64/numa.c | 3 ---
2 files changed, 11 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
index 87a5bfb..e4d77f4 100644
--- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
+++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
@@ -19,10 +19,6 @@
.macro kernel_entry_setup
.set push
.set mips64
- /* Set LPA on LOONGSON3 config3 */
- mfc0 t0, CP0_CONFIG3
- or t0, (0x1 << 7)
- mtc0 t0, CP0_CONFIG3
/* Set ELPA on LOONGSON3 pagegrain */
mfc0 t0, CP0_PAGEGRAIN
or t0, (0x1 << 29)
@@ -54,10 +50,6 @@
.macro smp_slave_setup
.set push
.set mips64
- /* Set LPA on LOONGSON3 config3 */
- mfc0 t0, CP0_CONFIG3
- or t0, (0x1 << 7)
- mtc0 t0, CP0_CONFIG3
/* Set ELPA on LOONGSON3 pagegrain */
mfc0 t0, CP0_PAGEGRAIN
or t0, (0x1 << 29)
diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
index cf9459f..c7e3cced 100644
--- a/arch/mips/loongson64/numa.c
+++ b/arch/mips/loongson64/numa.c
@@ -40,9 +40,6 @@ static void enable_lpa(void)
unsigned long value;
value = __read_32bit_c0_register($16, 3);
- value |= 0x00000080;
- __write_32bit_c0_register($16, 3, value);
- value = __read_32bit_c0_register($16, 3);
pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value);
value = __read_32bit_c0_register($5, 1);
--
2.1.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 2/6] MIPS: Loongson64: Set the field ELPA of CP0_PAGEGRAIN only once
2020-11-03 7:11 [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3 Tiezhu Yang
@ 2020-11-03 7:12 ` Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 3/6] MIPS: Loongson64: Set IPI_Enable register per core by itself Tiezhu Yang
` (4 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Tiezhu Yang @ 2020-11-03 7:12 UTC (permalink / raw)
To: Thomas Bogendoerfer, Huacai Chen, Jiaxun Yang
Cc: linux-mips, linux-kernel, Xuefeng Li
The field ELPA of CP0_PAGEGRAIN register is set at the beginning
of the kernel entry point in kernel-entry-init.h, no need to set
it again in numa.c, we can remove enable_lpa() and only print the
related information.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
v2: No changes
v3: No changes
arch/mips/loongson64/numa.c | 17 ++---------------
1 file changed, 2 insertions(+), 15 deletions(-)
diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
index c7e3cced..509b360 100644
--- a/arch/mips/loongson64/numa.c
+++ b/arch/mips/loongson64/numa.c
@@ -35,20 +35,6 @@ EXPORT_SYMBOL(__node_data);
cpumask_t __node_cpumask[MAX_NUMNODES];
EXPORT_SYMBOL(__node_cpumask);
-static void enable_lpa(void)
-{
- unsigned long value;
-
- value = __read_32bit_c0_register($16, 3);
- pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value);
-
- value = __read_32bit_c0_register($5, 1);
- value |= 0x20000000;
- __write_32bit_c0_register($5, 1, value);
- value = __read_32bit_c0_register($5, 1);
- pr_info("CP0_PageGrain: CP0 5.1 (0x%lx)\n", value);
-}
-
static void cpu_node_probe(void)
{
int i;
@@ -240,7 +226,8 @@ EXPORT_SYMBOL(pcibus_to_node);
void __init prom_init_numa_memory(void)
{
- enable_lpa();
+ pr_info("CP0_Config3: CP0 16.3 (0x%x)\n", read_c0_config3());
+ pr_info("CP0_PageGrain: CP0 5.1 (0x%x)\n", read_c0_pagegrain());
prom_meminit();
}
EXPORT_SYMBOL(prom_init_numa_memory);
--
2.1.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 3/6] MIPS: Loongson64: Set IPI_Enable register per core by itself
2020-11-03 7:11 [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3 Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 2/6] MIPS: Loongson64: Set the field ELPA of CP0_PAGEGRAIN only once Tiezhu Yang
@ 2020-11-03 7:12 ` Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 4/6] MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU Tiezhu Yang
` (3 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Tiezhu Yang @ 2020-11-03 7:12 UTC (permalink / raw)
To: Thomas Bogendoerfer, Huacai Chen, Jiaxun Yang
Cc: linux-mips, linux-kernel, Xuefeng Li
In the current code, for example, core 1 sets Core[0, 1, 2, 3]_IPI_Enalbe
register and core 2, 3 do the same thing on the 1-way Loongson64 platform,
this is not necessary. Set IPI_Enable register per core by itself to avoid
duplicate operations and make the logic more clear.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
v2: No changes
v3: No changes
arch/mips/loongson64/smp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index e744e1b..7d58853 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -348,8 +348,7 @@ static void loongson3_init_secondary(void)
/* Set interrupt mask, but don't enable */
change_c0_status(ST0_IM, imask);
- for (i = 0; i < num_possible_cpus(); i++)
- loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]);
+ loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]);
per_cpu(cpu_state, cpu) = CPU_ONLINE;
cpu_set_core(&cpu_data[cpu],
@@ -420,6 +419,7 @@ static void __init loongson3_smp_setup(void)
ipi_status0_regs_init();
ipi_en0_regs_init();
ipi_mailbox_buf_init();
+ loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(0)]);
cpu_set_core(&cpu_data[0],
cpu_logical_map(0) % loongson_sysconf.cores_per_package);
cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
--
2.1.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 4/6] MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU
2020-11-03 7:11 [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h Tiezhu Yang
` (2 preceding siblings ...)
2020-11-03 7:12 ` [PATCH v3 3/6] MIPS: Loongson64: Set IPI_Enable register per core by itself Tiezhu Yang
@ 2020-11-03 7:12 ` Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator Tiezhu Yang
` (2 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Tiezhu Yang @ 2020-11-03 7:12 UTC (permalink / raw)
To: Thomas Bogendoerfer, Huacai Chen, Jiaxun Yang
Cc: linux-mips, linux-kernel, Xuefeng Li, Lu Zeng, Jianmin Lv
Loongson 3A4000+ CPU has per-core Mail_Send register to send mail,
there is no need to maintain register address of each core and node,
just simply specify cpu number.
Signed-off-by: Lu Zeng <zenglu@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
v2: Add some callbacks in csr_ipi_probe()
v3: No changes
.../include/asm/mach-loongson64/loongson_regs.h | 10 ++
arch/mips/loongson64/smp.c | 120 +++++++++++++++++----
2 files changed, 107 insertions(+), 23 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h
index 83dbb9f..1659935 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h
@@ -227,6 +227,16 @@ static inline void csr_writeq(u64 val, u32 reg)
#define CSR_IPI_SEND_CPU_SHIFT 16
#define CSR_IPI_SEND_BLOCK BIT(31)
+#define LOONGSON_CSR_MAIL_BUF0 0x1020
+#define LOONGSON_CSR_MAIL_SEND 0x1048
+#define CSR_MAIL_SEND_BLOCK BIT_ULL(31)
+#define CSR_MAIL_SEND_BOX_LOW(box) (box << 1)
+#define CSR_MAIL_SEND_BOX_HIGH(box) ((box << 1) + 1)
+#define CSR_MAIL_SEND_BOX_SHIFT 2
+#define CSR_MAIL_SEND_CPU_SHIFT 16
+#define CSR_MAIL_SEND_BUF_SHIFT 32
+#define CSR_MAIL_SEND_H32_MASK 0xFFFFFFFF00000000ULL
+
static inline u64 drdtime(void)
{
int rID = 0;
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index 7d58853..736e98d 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -53,6 +53,29 @@ static uint32_t core0_c0count[NR_CPUS];
u32 (*ipi_read_clear)(int cpu);
void (*ipi_write_action)(int cpu, u32 action);
+void (*ipi_write_enable)(int cpu);
+void (*ipi_clear_buf)(int cpu);
+void (*ipi_write_buf)(int cpu, struct task_struct *idle);
+
+/* send mail via Mail_Send register for 3A4000+ CPU */
+static void csr_mail_send(uint64_t data, int cpu, int mailbox)
+{
+ uint64_t val;
+
+ /* send high 32 bits */
+ val = CSR_MAIL_SEND_BLOCK;
+ val |= (CSR_MAIL_SEND_BOX_HIGH(mailbox) << CSR_MAIL_SEND_BOX_SHIFT);
+ val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT);
+ val |= (data & CSR_MAIL_SEND_H32_MASK);
+ csr_writeq(val, LOONGSON_CSR_MAIL_SEND);
+
+ /* send low 32 bits */
+ val = CSR_MAIL_SEND_BLOCK;
+ val |= (CSR_MAIL_SEND_BOX_LOW(mailbox) << CSR_MAIL_SEND_BOX_SHIFT);
+ val |= (cpu << CSR_MAIL_SEND_CPU_SHIFT);
+ val |= (data << CSR_MAIL_SEND_BUF_SHIFT);
+ csr_writeq(val, LOONGSON_CSR_MAIL_SEND);
+};
static u32 csr_ipi_read_clear(int cpu)
{
@@ -79,6 +102,35 @@ static void csr_ipi_write_action(int cpu, u32 action)
}
}
+static void csr_ipi_write_enable(int cpu)
+{
+ csr_writel(0xffffffff, LOONGSON_CSR_IPI_EN);
+}
+
+static void csr_ipi_clear_buf(int cpu)
+{
+ csr_writeq(0, LOONGSON_CSR_MAIL_BUF0);
+}
+
+static void csr_ipi_write_buf(int cpu, struct task_struct *idle)
+{
+ unsigned long startargs[4];
+
+ /* startargs[] are initial PC, SP and GP for secondary CPU */
+ startargs[0] = (unsigned long)&smp_bootstrap;
+ startargs[1] = (unsigned long)__KSTK_TOS(idle);
+ startargs[2] = (unsigned long)task_thread_info(idle);
+ startargs[3] = 0;
+
+ pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
+ cpu, startargs[0], startargs[1], startargs[2]);
+
+ csr_mail_send(startargs[3], cpu_logical_map(cpu), 3);
+ csr_mail_send(startargs[2], cpu_logical_map(cpu), 2);
+ csr_mail_send(startargs[1], cpu_logical_map(cpu), 1);
+ csr_mail_send(startargs[0], cpu_logical_map(cpu), 0);
+}
+
static u32 legacy_ipi_read_clear(int cpu)
{
u32 action;
@@ -96,14 +148,53 @@ static void legacy_ipi_write_action(int cpu, u32 action)
loongson3_ipi_write32((u32)action, ipi_set0_regs[cpu]);
}
+static void legacy_ipi_write_enable(int cpu)
+{
+ loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]);
+}
+
+static void legacy_ipi_clear_buf(int cpu)
+{
+ loongson3_ipi_write64(0, ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
+}
+
+static void legacy_ipi_write_buf(int cpu, struct task_struct *idle)
+{
+ unsigned long startargs[4];
+
+ /* startargs[] are initial PC, SP and GP for secondary CPU */
+ startargs[0] = (unsigned long)&smp_bootstrap;
+ startargs[1] = (unsigned long)__KSTK_TOS(idle);
+ startargs[2] = (unsigned long)task_thread_info(idle);
+ startargs[3] = 0;
+
+ pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
+ cpu, startargs[0], startargs[1], startargs[2]);
+
+ loongson3_ipi_write64(startargs[3],
+ ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18);
+ loongson3_ipi_write64(startargs[2],
+ ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10);
+ loongson3_ipi_write64(startargs[1],
+ ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8);
+ loongson3_ipi_write64(startargs[0],
+ ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
+}
+
static void csr_ipi_probe(void)
{
if (cpu_has_csr() && csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_IPI) {
ipi_read_clear = csr_ipi_read_clear;
ipi_write_action = csr_ipi_write_action;
+ ipi_write_enable = csr_ipi_write_enable;
+ ipi_clear_buf = csr_ipi_clear_buf;
+ ipi_write_buf = csr_ipi_write_buf;
} else {
ipi_read_clear = legacy_ipi_read_clear;
ipi_write_action = legacy_ipi_write_action;
+ ipi_write_enable = legacy_ipi_write_enable;
+ ipi_clear_buf = legacy_ipi_clear_buf;
+ ipi_write_buf = legacy_ipi_write_buf;
}
}
@@ -347,8 +438,7 @@ static void loongson3_init_secondary(void)
/* Set interrupt mask, but don't enable */
change_c0_status(ST0_IM, imask);
-
- loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(cpu)]);
+ ipi_write_enable(cpu);
per_cpu(cpu_state, cpu) = CPU_ONLINE;
cpu_set_core(&cpu_data[cpu],
@@ -380,8 +470,8 @@ static void loongson3_smp_finish(void)
write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
local_irq_enable();
- loongson3_ipi_write64(0,
- ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
+ ipi_clear_buf(cpu);
+
pr_info("CPU#%d finished, CP0_ST=%x\n",
smp_processor_id(), read_c0_status());
}
@@ -419,7 +509,8 @@ static void __init loongson3_smp_setup(void)
ipi_status0_regs_init();
ipi_en0_regs_init();
ipi_mailbox_buf_init();
- loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(0)]);
+ ipi_write_enable(0);
+
cpu_set_core(&cpu_data[0],
cpu_logical_map(0) % loongson_sysconf.cores_per_package);
cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
@@ -439,27 +530,10 @@ static void __init loongson3_prepare_cpus(unsigned int max_cpus)
*/
static int loongson3_boot_secondary(int cpu, struct task_struct *idle)
{
- unsigned long startargs[4];
-
pr_info("Booting CPU#%d...\n", cpu);
- /* startargs[] are initial PC, SP and GP for secondary CPU */
- startargs[0] = (unsigned long)&smp_bootstrap;
- startargs[1] = (unsigned long)__KSTK_TOS(idle);
- startargs[2] = (unsigned long)task_thread_info(idle);
- startargs[3] = 0;
-
- pr_debug("CPU#%d, func_pc=%lx, sp=%lx, gp=%lx\n",
- cpu, startargs[0], startargs[1], startargs[2]);
+ ipi_write_buf(cpu, idle);
- loongson3_ipi_write64(startargs[3],
- ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x18);
- loongson3_ipi_write64(startargs[2],
- ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x10);
- loongson3_ipi_write64(startargs[1],
- ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x8);
- loongson3_ipi_write64(startargs[0],
- ipi_mailbox_buf[cpu_logical_map(cpu)] + 0x0);
return 0;
}
--
2.1.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator
2020-11-03 7:11 [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h Tiezhu Yang
` (3 preceding siblings ...)
2020-11-03 7:12 ` [PATCH v3 4/6] MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU Tiezhu Yang
@ 2020-11-03 7:12 ` Tiezhu Yang
2020-11-04 6:31 ` Jinyang He
2020-11-03 7:12 ` [PATCH v3 6/6] MIPS: Loongson64: Move decode_cpucfg() to loongson_regs.h Tiezhu Yang
2020-11-11 23:04 ` [PATCH v3 0/6] Modify some registers operations and move " Thomas Bogendoerfer
6 siblings, 1 reply; 16+ messages in thread
From: Tiezhu Yang @ 2020-11-03 7:12 UTC (permalink / raw)
To: Thomas Bogendoerfer, Huacai Chen, Jiaxun Yang
Cc: linux-mips, linux-kernel, Xuefeng Li, Lu Zeng, Jun Yi
In play_dead function, the whole 64-bit PC mailbox was used as a indicator
to determine if the master core had written boot jump information.
However, after we introduced CSR mailsend, the hardware will not guarante
an atomic write for the 64-bit PC mailbox. Thus we have to use the lower
32-bit which is written at the last as the jump indicator instead.
Signed-off-by: Lu Zeng <zenglu@loongson.cn>
Signed-off-by: Jun Yi <yijun@loongson.cn>
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
v2: No changes
v3: Update the commit message and comment
arch/mips/loongson64/smp.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index 736e98d..aa0cd72 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -764,9 +764,10 @@ static void loongson3_type3_play_dead(int *state_addr)
"1: li %[count], 0x100 \n" /* wait for init loop */
"2: bnez %[count], 2b \n" /* limit mailbox access */
" addiu %[count], -1 \n"
- " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
+ " lw %[initfunc], 0x20(%[base]) \n" /* check lower 32-bit as jump indicator */
" beqz %[initfunc], 1b \n"
" nop \n"
+ " ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole 64-bit) via mailbox */
" ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
" ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
" ld $a1, 0x38(%[base]) \n"
--
2.1.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v3 6/6] MIPS: Loongson64: Move decode_cpucfg() to loongson_regs.h
2020-11-03 7:11 [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h Tiezhu Yang
` (4 preceding siblings ...)
2020-11-03 7:12 ` [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator Tiezhu Yang
@ 2020-11-03 7:12 ` Tiezhu Yang
2020-11-11 23:05 ` Thomas Bogendoerfer
2020-11-11 23:04 ` [PATCH v3 0/6] Modify some registers operations and move " Thomas Bogendoerfer
6 siblings, 1 reply; 16+ messages in thread
From: Tiezhu Yang @ 2020-11-03 7:12 UTC (permalink / raw)
To: Thomas Bogendoerfer, Huacai Chen, Jiaxun Yang
Cc: linux-mips, linux-kernel, Xuefeng Li
Since decode_cpucfg() is only used for Loongson64, just move
it to loongson_regs.h to avoid the pollution of common code
with #ifdef CONFIG_CPU_LOONGSON64.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
---
v2: No changes
v3: No changes
.../include/asm/mach-loongson64/loongson_regs.h | 24 +++++++++++++++++
arch/mips/kernel/cpu-probe.c | 31 +---------------------
2 files changed, 25 insertions(+), 30 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson64/loongson_regs.h b/arch/mips/include/asm/mach-loongson64/loongson_regs.h
index 1659935..2d469d6 100644
--- a/arch/mips/include/asm/mach-loongson64/loongson_regs.h
+++ b/arch/mips/include/asm/mach-loongson64/loongson_regs.h
@@ -129,6 +129,30 @@ static inline u32 read_cpucfg(u32 reg)
#define LOONGSON_CFG7_GCCAEQRP BIT(0)
#define LOONGSON_CFG7_UCAWINP BIT(1)
+static inline void decode_cpucfg(struct cpuinfo_mips *c)
+{
+ u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
+ u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
+ u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
+
+ if (cfg1 & LOONGSON_CFG1_MMI)
+ c->ases |= MIPS_ASE_LOONGSON_MMI;
+
+ if (cfg2 & LOONGSON_CFG2_LEXT1)
+ c->ases |= MIPS_ASE_LOONGSON_EXT;
+
+ if (cfg2 & LOONGSON_CFG2_LEXT2)
+ c->ases |= MIPS_ASE_LOONGSON_EXT2;
+
+ if (cfg2 & LOONGSON_CFG2_LSPW) {
+ c->options |= MIPS_CPU_LDPTE;
+ c->guest.options |= MIPS_CPU_LDPTE;
+ }
+
+ if (cfg3 & LOONGSON_CFG3_LCAMP)
+ c->ases |= MIPS_ASE_LOONGSON_CAM;
+}
+
static inline bool cpu_has_csr(void)
{
if (cpu_has_cfg())
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index e685369..1fa2c8b 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -31,6 +31,7 @@
#include "fpu-probe.h"
#include <asm/mach-loongson64/cpucfg-emul.h>
+#include <asm/mach-loongson64/loongson_regs.h>
/* Hardware capabilities */
unsigned int elf_hwcap __read_mostly;
@@ -1692,33 +1693,6 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
}
}
-#ifdef CONFIG_CPU_LOONGSON64
-#include <loongson_regs.h>
-
-static inline void decode_cpucfg(struct cpuinfo_mips *c)
-{
- u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
- u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
- u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
-
- if (cfg1 & LOONGSON_CFG1_MMI)
- c->ases |= MIPS_ASE_LOONGSON_MMI;
-
- if (cfg2 & LOONGSON_CFG2_LEXT1)
- c->ases |= MIPS_ASE_LOONGSON_EXT;
-
- if (cfg2 & LOONGSON_CFG2_LEXT2)
- c->ases |= MIPS_ASE_LOONGSON_EXT2;
-
- if (cfg2 & LOONGSON_CFG2_LSPW) {
- c->options |= MIPS_CPU_LDPTE;
- c->guest.options |= MIPS_CPU_LDPTE;
- }
-
- if (cfg3 & LOONGSON_CFG3_LCAMP)
- c->ases |= MIPS_ASE_LOONGSON_CAM;
-}
-
static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
{
decode_configs(c);
@@ -1787,9 +1761,6 @@ static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
break;
}
}
-#else
-static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
-#endif
static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
{
--
2.1.0
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3
2020-11-03 7:12 ` [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3 Tiezhu Yang
@ 2020-11-04 2:00 ` Huacai Chen
2020-11-04 3:50 ` Tiezhu Yang
0 siblings, 1 reply; 16+ messages in thread
From: Huacai Chen @ 2020-11-04 2:00 UTC (permalink / raw)
To: Tiezhu Yang
Cc: Thomas Bogendoerfer, Jiaxun Yang, open list:MIPS, LKML, Xuefeng Li
Hi, Tiezhu,
On Tue, Nov 3, 2020 at 3:13 PM Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
>
> The field LPA of CP0_CONFIG3 register is read only for Loongson64, so the
> write operations are meaningless, remove them.
>
> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
>
> v2: No changes
> v3: No changes
>
> arch/mips/include/asm/mach-loongson64/kernel-entry-init.h | 8 --------
> arch/mips/loongson64/numa.c | 3 ---
> 2 files changed, 11 deletions(-)
>
> diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> index 87a5bfb..e4d77f4 100644
> --- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> +++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> @@ -19,10 +19,6 @@
> .macro kernel_entry_setup
> .set push
> .set mips64
> - /* Set LPA on LOONGSON3 config3 */
> - mfc0 t0, CP0_CONFIG3
> - or t0, (0x1 << 7)
> - mtc0 t0, CP0_CONFIG3
Sorry for the late response, I have the same worry as Jiaxun. As you
know, Loongson's user manuals are not always correct, but the original
code comes from Loongson are usually better. So, my opinion is "Don't
change it if it doesn't break anything".
Huacai
> /* Set ELPA on LOONGSON3 pagegrain */
> mfc0 t0, CP0_PAGEGRAIN
> or t0, (0x1 << 29)
> @@ -54,10 +50,6 @@
> .macro smp_slave_setup
> .set push
> .set mips64
> - /* Set LPA on LOONGSON3 config3 */
> - mfc0 t0, CP0_CONFIG3
> - or t0, (0x1 << 7)
> - mtc0 t0, CP0_CONFIG3
> /* Set ELPA on LOONGSON3 pagegrain */
> mfc0 t0, CP0_PAGEGRAIN
> or t0, (0x1 << 29)
> diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
> index cf9459f..c7e3cced 100644
> --- a/arch/mips/loongson64/numa.c
> +++ b/arch/mips/loongson64/numa.c
> @@ -40,9 +40,6 @@ static void enable_lpa(void)
> unsigned long value;
>
> value = __read_32bit_c0_register($16, 3);
> - value |= 0x00000080;
> - __write_32bit_c0_register($16, 3, value);
> - value = __read_32bit_c0_register($16, 3);
> pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value);
>
> value = __read_32bit_c0_register($5, 1);
> --
> 2.1.0
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3
2020-11-04 2:00 ` Huacai Chen
@ 2020-11-04 3:50 ` Tiezhu Yang
2020-11-05 5:57 ` Huacai Chen
0 siblings, 1 reply; 16+ messages in thread
From: Tiezhu Yang @ 2020-11-04 3:50 UTC (permalink / raw)
To: Huacai Chen
Cc: Thomas Bogendoerfer, Jiaxun Yang, open list:MIPS, LKML, Xuefeng Li
On 11/04/2020 10:00 AM, Huacai Chen wrote:
> Hi, Tiezhu,
>
> On Tue, Nov 3, 2020 at 3:13 PM Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
>> The field LPA of CP0_CONFIG3 register is read only for Loongson64, so the
>> write operations are meaningless, remove them.
>>
>> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
>> ---
>>
>> v2: No changes
>> v3: No changes
>>
>> arch/mips/include/asm/mach-loongson64/kernel-entry-init.h | 8 --------
>> arch/mips/loongson64/numa.c | 3 ---
>> 2 files changed, 11 deletions(-)
>>
>> diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
>> index 87a5bfb..e4d77f4 100644
>> --- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
>> +++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
>> @@ -19,10 +19,6 @@
>> .macro kernel_entry_setup
>> .set push
>> .set mips64
>> - /* Set LPA on LOONGSON3 config3 */
>> - mfc0 t0, CP0_CONFIG3
>> - or t0, (0x1 << 7)
>> - mtc0 t0, CP0_CONFIG3
> Sorry for the late response, I have the same worry as Jiaxun. As you
> know, Loongson's user manuals are not always correct, but the original
> code comes from Loongson are usually better. So, my opinion is "Don't
> change it if it doesn't break anything".
Hi Huacai,
Thanks for your reply, I have confirmed by Loongson user manuals and
hardware designers, CP0_CONFIG3 register is read only.
Without this patch, the related kernel code is meaningless, with
this patch, it can reflect the reality.
Thanks,
Tiezhu
>
> Huacai
>
>> /* Set ELPA on LOONGSON3 pagegrain */
>> mfc0 t0, CP0_PAGEGRAIN
>> or t0, (0x1 << 29)
>> @@ -54,10 +50,6 @@
>> .macro smp_slave_setup
>> .set push
>> .set mips64
>> - /* Set LPA on LOONGSON3 config3 */
>> - mfc0 t0, CP0_CONFIG3
>> - or t0, (0x1 << 7)
>> - mtc0 t0, CP0_CONFIG3
>> /* Set ELPA on LOONGSON3 pagegrain */
>> mfc0 t0, CP0_PAGEGRAIN
>> or t0, (0x1 << 29)
>> diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
>> index cf9459f..c7e3cced 100644
>> --- a/arch/mips/loongson64/numa.c
>> +++ b/arch/mips/loongson64/numa.c
>> @@ -40,9 +40,6 @@ static void enable_lpa(void)
>> unsigned long value;
>>
>> value = __read_32bit_c0_register($16, 3);
>> - value |= 0x00000080;
>> - __write_32bit_c0_register($16, 3, value);
>> - value = __read_32bit_c0_register($16, 3);
>> pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value);
>>
>> value = __read_32bit_c0_register($5, 1);
>> --
>> 2.1.0
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator
2020-11-03 7:12 ` [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator Tiezhu Yang
@ 2020-11-04 6:31 ` Jinyang He
2020-11-04 7:04 ` Jiaxun Yang
0 siblings, 1 reply; 16+ messages in thread
From: Jinyang He @ 2020-11-04 6:31 UTC (permalink / raw)
To: Tiezhu Yang, Thomas Bogendoerfer, Huacai Chen, Jiaxun Yang
Cc: linux-mips, linux-kernel, Xuefeng Li, Lu Zeng, Jun Yi
Hi, all,
On 11/03/2020 03:12 PM, Tiezhu Yang wrote:
> In play_dead function, the whole 64-bit PC mailbox was used as a indicator
> to determine if the master core had written boot jump information.
>
> However, after we introduced CSR mailsend, the hardware will not guarante
> an atomic write for the 64-bit PC mailbox. Thus we have to use the lower
> 32-bit which is written at the last as the jump indicator instead.
>
> Signed-off-by: Lu Zeng <zenglu@loongson.cn>
> Signed-off-by: Jun Yi <yijun@loongson.cn>
> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> ---
>
> v2: No changes
> v3: Update the commit message and comment
>
> arch/mips/loongson64/smp.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
> index 736e98d..aa0cd72 100644
> --- a/arch/mips/loongson64/smp.c
> +++ b/arch/mips/loongson64/smp.c
> @@ -764,9 +764,10 @@ static void loongson3_type3_play_dead(int *state_addr)
> "1: li %[count], 0x100 \n" /* wait for init loop */
> "2: bnez %[count], 2b \n" /* limit mailbox access */
> " addiu %[count], -1 \n"
> - " ld %[initfunc], 0x20(%[base]) \n" /* get PC via mailbox */
I have some confusion here. Play_dead CPUs is always brought up by cpu_up().
On Loongson64, it calls loongson3_boot_secondary(). The value of
startargs[0]
is the address of smp_bootstrap() which is in CKSEG0 and a constant
after the
kernel is compiled. That means its value likes 0xffffffff8... and only
the low
32bit is useful. As "lw" is sign-extended, could we replace "ld" with
"lw" simply?
Thanks,
Jinyang
> + " lw %[initfunc], 0x20(%[base]) \n" /* check lower 32-bit as jump indicator */
> " beqz %[initfunc], 1b \n"
> " nop \n"
> + " ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole 64-bit) via mailbox */
> " ld $sp, 0x28(%[base]) \n" /* get SP via mailbox */
> " ld $gp, 0x30(%[base]) \n" /* get GP via mailbox */
> " ld $a1, 0x38(%[base]) \n"
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator
2020-11-04 6:31 ` Jinyang He
@ 2020-11-04 7:04 ` Jiaxun Yang
2020-11-04 7:18 ` Jinyang He
0 siblings, 1 reply; 16+ messages in thread
From: Jiaxun Yang @ 2020-11-04 7:04 UTC (permalink / raw)
To: Jinyang He, Tiezhu Yang, Thomas Bogendoerfer, Huacai Chen
Cc: linux-mips, linux-kernel, Xuefeng Li, Lu Zeng, Jun Yi
在 2020/11/4 14:31, Jinyang He 写道:
> Hi, all,
>
> On 11/03/2020 03:12 PM, Tiezhu Yang wrote:
>> In play_dead function, the whole 64-bit PC mailbox was used as a
>> indicator
>> to determine if the master core had written boot jump information.
>>
>> However, after we introduced CSR mailsend, the hardware will not
>> guarante
>> an atomic write for the 64-bit PC mailbox. Thus we have to use the lower
>> 32-bit which is written at the last as the jump indicator instead.
>>
>> Signed-off-by: Lu Zeng <zenglu@loongson.cn>
>> Signed-off-by: Jun Yi <yijun@loongson.cn>
>> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
>> ---
>>
>> v2: No changes
>> v3: Update the commit message and comment
>>
>> arch/mips/loongson64/smp.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
>> index 736e98d..aa0cd72 100644
>> --- a/arch/mips/loongson64/smp.c
>> +++ b/arch/mips/loongson64/smp.c
>> @@ -764,9 +764,10 @@ static void loongson3_type3_play_dead(int
>> *state_addr)
>> "1: li %[count], 0x100 \n" /* wait for init
>> loop */
>> "2: bnez %[count], 2b \n" /* limit mailbox
>> access */
>> " addiu %[count], -1 \n"
>> - " ld %[initfunc], 0x20(%[base]) \n" /* get PC via
>> mailbox */
> I have some confusion here. Play_dead CPUs is always brought up by
> cpu_up().
> On Loongson64, it calls loongson3_boot_secondary(). The value of
> startargs[0]
> is the address of smp_bootstrap() which is in CKSEG0 and a constant
> after the
> kernel is compiled. That means its value likes 0xffffffff8... and only
> the low
> 32bit is useful. As "lw" is sign-extended, could we replace "ld" with
> "lw" simply?
Hi Jinyang,
I'd prefer not to do so. In future we may have kernel running in other
spaces,
(e.g. xkphys), and there is no reason to add a barrier on that without
actual benefit.
I had check PMON firmware and it's also loading the full 64-bit address.
Also to keep consistent, mailbox writing part needs to be refined to
match the
behavior of reading. Otherwise other readers will be confused.
Thus leaving it as is looks much more reasonable.
Thanks.
- Jiaxun
>
> Thanks,
> Jinyang
>> + " lw %[initfunc], 0x20(%[base]) \n" /* check lower
>> 32-bit as jump indicator */
>> " beqz %[initfunc], 1b \n"
>> " nop \n"
>> + " ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole
>> 64-bit) via mailbox */
>> " ld $sp, 0x28(%[base]) \n" /* get SP via
>> mailbox */
>> " ld $gp, 0x30(%[base]) \n" /* get GP via
>> mailbox */
>> " ld $a1, 0x38(%[base]) \n"
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator
2020-11-04 7:04 ` Jiaxun Yang
@ 2020-11-04 7:18 ` Jinyang He
0 siblings, 0 replies; 16+ messages in thread
From: Jinyang He @ 2020-11-04 7:18 UTC (permalink / raw)
To: Jiaxun Yang, Tiezhu Yang, Thomas Bogendoerfer, Huacai Chen
Cc: linux-mips, linux-kernel, Xuefeng Li, Lu Zeng, Jun Yi
On 11/04/2020 03:04 PM, Jiaxun Yang wrote:
>
>
> 在 2020/11/4 14:31, Jinyang He 写道:
>> Hi, all,
>>
>> On 11/03/2020 03:12 PM, Tiezhu Yang wrote:
>>> In play_dead function, the whole 64-bit PC mailbox was used as a
>>> indicator
>>> to determine if the master core had written boot jump information.
>>>
>>> However, after we introduced CSR mailsend, the hardware will not
>>> guarante
>>> an atomic write for the 64-bit PC mailbox. Thus we have to use the
>>> lower
>>> 32-bit which is written at the last as the jump indicator instead.
>>>
>>> Signed-off-by: Lu Zeng <zenglu@loongson.cn>
>>> Signed-off-by: Jun Yi <yijun@loongson.cn>
>>> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
>>> ---
>>>
>>> v2: No changes
>>> v3: Update the commit message and comment
>>>
>>> arch/mips/loongson64/smp.c | 3 ++-
>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
>>> index 736e98d..aa0cd72 100644
>>> --- a/arch/mips/loongson64/smp.c
>>> +++ b/arch/mips/loongson64/smp.c
>>> @@ -764,9 +764,10 @@ static void loongson3_type3_play_dead(int
>>> *state_addr)
>>> "1: li %[count], 0x100 \n" /* wait for init
>>> loop */
>>> "2: bnez %[count], 2b \n" /* limit mailbox
>>> access */
>>> " addiu %[count], -1 \n"
>>> - " ld %[initfunc], 0x20(%[base]) \n" /* get PC via
>>> mailbox */
>> I have some confusion here. Play_dead CPUs is always brought up by
>> cpu_up().
>> On Loongson64, it calls loongson3_boot_secondary(). The value of
>> startargs[0]
>> is the address of smp_bootstrap() which is in CKSEG0 and a constant
>> after the
>> kernel is compiled. That means its value likes 0xffffffff8... and
>> only the low
>> 32bit is useful. As "lw" is sign-extended, could we replace "ld" with
>> "lw" simply?
>
> Hi Jinyang,
>
> I'd prefer not to do so. In future we may have kernel running in other
> spaces,
> (e.g. xkphys), and there is no reason to add a barrier on that without
> actual benefit.
> I had check PMON firmware and it's also loading the full 64-bit address.
>
> Also to keep consistent, mailbox writing part needs to be refined to
> match the
> behavior of reading. Otherwise other readers will be confused.
>
> Thus leaving it as is looks much more reasonable.
OK, the current code looks better,
please ignore my comment, sorry for the noise.
Thanks,
Jinyang
>
> Thanks.
>
> - Jiaxun
>
>>
>> Thanks,
>> Jinyang
>>> + " lw %[initfunc], 0x20(%[base]) \n" /* check lower
>>> 32-bit as jump indicator */
>>> " beqz %[initfunc], 1b \n"
>>> " nop \n"
>>> + " ld %[initfunc], 0x20(%[base]) \n" /* get PC (whole
>>> 64-bit) via mailbox */
>>> " ld $sp, 0x28(%[base]) \n" /* get SP via
>>> mailbox */
>>> " ld $gp, 0x30(%[base]) \n" /* get GP via
>>> mailbox */
>>> " ld $a1, 0x38(%[base]) \n"
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3
2020-11-04 3:50 ` Tiezhu Yang
@ 2020-11-05 5:57 ` Huacai Chen
2020-11-05 9:05 ` Tiezhu Yang
0 siblings, 1 reply; 16+ messages in thread
From: Huacai Chen @ 2020-11-05 5:57 UTC (permalink / raw)
To: Tiezhu Yang
Cc: Thomas Bogendoerfer, Jiaxun Yang, open list:MIPS, LKML, Xuefeng Li
Hi, Tiezhu,
On Wed, Nov 4, 2020 at 11:51 AM Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
>
> On 11/04/2020 10:00 AM, Huacai Chen wrote:
> > Hi, Tiezhu,
> >
> > On Tue, Nov 3, 2020 at 3:13 PM Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
> >> The field LPA of CP0_CONFIG3 register is read only for Loongson64, so the
> >> write operations are meaningless, remove them.
> >>
> >> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
> >> ---
> >>
> >> v2: No changes
> >> v3: No changes
> >>
> >> arch/mips/include/asm/mach-loongson64/kernel-entry-init.h | 8 --------
> >> arch/mips/loongson64/numa.c | 3 ---
> >> 2 files changed, 11 deletions(-)
> >>
> >> diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> >> index 87a5bfb..e4d77f4 100644
> >> --- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> >> +++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
> >> @@ -19,10 +19,6 @@
> >> .macro kernel_entry_setup
> >> .set push
> >> .set mips64
> >> - /* Set LPA on LOONGSON3 config3 */
> >> - mfc0 t0, CP0_CONFIG3
> >> - or t0, (0x1 << 7)
> >> - mtc0 t0, CP0_CONFIG3
> > Sorry for the late response, I have the same worry as Jiaxun. As you
> > know, Loongson's user manuals are not always correct, but the original
> > code comes from Loongson are usually better. So, my opinion is "Don't
> > change it if it doesn't break anything".
>
> Hi Huacai,
>
> Thanks for your reply, I have confirmed by Loongson user manuals and
> hardware designers, CP0_CONFIG3 register is read only.
>
> Without this patch, the related kernel code is meaningless, with
> this patch, it can reflect the reality.
>
> Thanks,
> Tiezhu
Then you should at least test your code on Loongson-3A R1 two way machine.
Huacai
>
> >
> > Huacai
> >
> >> /* Set ELPA on LOONGSON3 pagegrain */
> >> mfc0 t0, CP0_PAGEGRAIN
> >> or t0, (0x1 << 29)
> >> @@ -54,10 +50,6 @@
> >> .macro smp_slave_setup
> >> .set push
> >> .set mips64
> >> - /* Set LPA on LOONGSON3 config3 */
> >> - mfc0 t0, CP0_CONFIG3
> >> - or t0, (0x1 << 7)
> >> - mtc0 t0, CP0_CONFIG3
> >> /* Set ELPA on LOONGSON3 pagegrain */
> >> mfc0 t0, CP0_PAGEGRAIN
> >> or t0, (0x1 << 29)
> >> diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
> >> index cf9459f..c7e3cced 100644
> >> --- a/arch/mips/loongson64/numa.c
> >> +++ b/arch/mips/loongson64/numa.c
> >> @@ -40,9 +40,6 @@ static void enable_lpa(void)
> >> unsigned long value;
> >>
> >> value = __read_32bit_c0_register($16, 3);
> >> - value |= 0x00000080;
> >> - __write_32bit_c0_register($16, 3, value);
> >> - value = __read_32bit_c0_register($16, 3);
> >> pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value);
> >>
> >> value = __read_32bit_c0_register($5, 1);
> >> --
> >> 2.1.0
> >>
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3
2020-11-05 5:57 ` Huacai Chen
@ 2020-11-05 9:05 ` Tiezhu Yang
0 siblings, 0 replies; 16+ messages in thread
From: Tiezhu Yang @ 2020-11-05 9:05 UTC (permalink / raw)
To: Huacai Chen
Cc: Thomas Bogendoerfer, Jiaxun Yang, open list:MIPS, LKML, Xuefeng Li
On 11/05/2020 01:57 PM, Huacai Chen wrote:
> Hi, Tiezhu,
>
> On Wed, Nov 4, 2020 at 11:51 AM Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
>> On 11/04/2020 10:00 AM, Huacai Chen wrote:
>>> Hi, Tiezhu,
>>>
>>> On Tue, Nov 3, 2020 at 3:13 PM Tiezhu Yang <yangtiezhu@loongson.cn> wrote:
>>>> The field LPA of CP0_CONFIG3 register is read only for Loongson64, so the
>>>> write operations are meaningless, remove them.
>>>>
>>>> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
>>>> ---
>>>>
>>>> v2: No changes
>>>> v3: No changes
>>>>
>>>> arch/mips/include/asm/mach-loongson64/kernel-entry-init.h | 8 --------
>>>> arch/mips/loongson64/numa.c | 3 ---
>>>> 2 files changed, 11 deletions(-)
>>>>
>>>> diff --git a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
>>>> index 87a5bfb..e4d77f4 100644
>>>> --- a/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
>>>> +++ b/arch/mips/include/asm/mach-loongson64/kernel-entry-init.h
>>>> @@ -19,10 +19,6 @@
>>>> .macro kernel_entry_setup
>>>> .set push
>>>> .set mips64
>>>> - /* Set LPA on LOONGSON3 config3 */
>>>> - mfc0 t0, CP0_CONFIG3
>>>> - or t0, (0x1 << 7)
>>>> - mtc0 t0, CP0_CONFIG3
>>> Sorry for the late response, I have the same worry as Jiaxun. As you
>>> know, Loongson's user manuals are not always correct, but the original
>>> code comes from Loongson are usually better. So, my opinion is "Don't
>>> change it if it doesn't break anything".
>> Hi Huacai,
>>
>> Thanks for your reply, I have confirmed by Loongson user manuals and
>> hardware designers, CP0_CONFIG3 register is read only.
>>
>> Without this patch, the related kernel code is meaningless, with
>> this patch, it can reflect the reality.
>>
>> Thanks,
>> Tiezhu
> Then you should at least test your code on Loongson-3A R1 two way machine.
Hi Huacai,
Thanks for your opinion.
I find a 3a1000 machine to test, the result is that CP0 config3
is read only which is consistent with user manual, the LPA field
of CP0 config3 can not write and its reset default value is 1.
So this patch has no problem.
Thanks,
Tiezhu
>
> Huacai
>>> Huacai
>>>
>>>> /* Set ELPA on LOONGSON3 pagegrain */
>>>> mfc0 t0, CP0_PAGEGRAIN
>>>> or t0, (0x1 << 29)
>>>> @@ -54,10 +50,6 @@
>>>> .macro smp_slave_setup
>>>> .set push
>>>> .set mips64
>>>> - /* Set LPA on LOONGSON3 config3 */
>>>> - mfc0 t0, CP0_CONFIG3
>>>> - or t0, (0x1 << 7)
>>>> - mtc0 t0, CP0_CONFIG3
>>>> /* Set ELPA on LOONGSON3 pagegrain */
>>>> mfc0 t0, CP0_PAGEGRAIN
>>>> or t0, (0x1 << 29)
>>>> diff --git a/arch/mips/loongson64/numa.c b/arch/mips/loongson64/numa.c
>>>> index cf9459f..c7e3cced 100644
>>>> --- a/arch/mips/loongson64/numa.c
>>>> +++ b/arch/mips/loongson64/numa.c
>>>> @@ -40,9 +40,6 @@ static void enable_lpa(void)
>>>> unsigned long value;
>>>>
>>>> value = __read_32bit_c0_register($16, 3);
>>>> - value |= 0x00000080;
>>>> - __write_32bit_c0_register($16, 3, value);
>>>> - value = __read_32bit_c0_register($16, 3);
>>>> pr_info("CP0_Config3: CP0 16.3 (0x%lx)\n", value);
>>>>
>>>> value = __read_32bit_c0_register($5, 1);
>>>> --
>>>> 2.1.0
>>>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h
2020-11-03 7:11 [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h Tiezhu Yang
` (5 preceding siblings ...)
2020-11-03 7:12 ` [PATCH v3 6/6] MIPS: Loongson64: Move decode_cpucfg() to loongson_regs.h Tiezhu Yang
@ 2020-11-11 23:04 ` Thomas Bogendoerfer
6 siblings, 0 replies; 16+ messages in thread
From: Thomas Bogendoerfer @ 2020-11-11 23:04 UTC (permalink / raw)
To: Tiezhu Yang
Cc: Huacai Chen, Jiaxun Yang, linux-mips, linux-kernel, Xuefeng Li
On Tue, Nov 03, 2020 at 03:11:59PM +0800, Tiezhu Yang wrote:
> v2: Add some callbacks in csr_ipi probe() for patch #4
> v3: Update the commit message and comment for patch #5
>
> Tiezhu Yang (6):
> MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3
> MIPS: Loongson64: Set the field ELPA of CP0_PAGEGRAIN only once
> MIPS: Loongson64: Set IPI_Enable register per core by itself
> MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU
> MIPS: Loongson64: SMP: Fix up play_dead jump indicator
> MIPS: Loongson64: Move decode_cpucfg() to loongson_regs.h
>
> .../asm/mach-loongson64/kernel-entry-init.h | 8 --
> .../include/asm/mach-loongson64/loongson_regs.h | 34 ++++++
> arch/mips/kernel/cpu-probe.c | 31 +-----
> arch/mips/loongson64/numa.c | 20 +---
> arch/mips/loongson64/smp.c | 123 +++++++++++++++++----
> 5 files changed, 136 insertions(+), 80 deletions(-)
applied patches 1-5 of this series to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v3 6/6] MIPS: Loongson64: Move decode_cpucfg() to loongson_regs.h
2020-11-03 7:12 ` [PATCH v3 6/6] MIPS: Loongson64: Move decode_cpucfg() to loongson_regs.h Tiezhu Yang
@ 2020-11-11 23:05 ` Thomas Bogendoerfer
0 siblings, 0 replies; 16+ messages in thread
From: Thomas Bogendoerfer @ 2020-11-11 23:05 UTC (permalink / raw)
To: Tiezhu Yang
Cc: Huacai Chen, Jiaxun Yang, linux-mips, linux-kernel, Xuefeng Li
On Tue, Nov 03, 2020 at 03:12:05PM +0800, Tiezhu Yang wrote:
> Since decode_cpucfg() is only used for Loongson64, just move
> it to loongson_regs.h to avoid the pollution of common code
> with #ifdef CONFIG_CPU_LOONGSON64.
right now I prefer the way it is. Something like this would be
needed, if we are able to build a generic kernel, which works
also on Loongson64.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-11-12 1:44 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-11-03 7:11 [PATCH v3 0/6] Modify some registers operations and move decode_cpucfg() to loongson_regs.h Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 1/6] MIPS: Loongson64: Do not write the read only field LPA of CP0_CONFIG3 Tiezhu Yang
2020-11-04 2:00 ` Huacai Chen
2020-11-04 3:50 ` Tiezhu Yang
2020-11-05 5:57 ` Huacai Chen
2020-11-05 9:05 ` Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 2/6] MIPS: Loongson64: Set the field ELPA of CP0_PAGEGRAIN only once Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 3/6] MIPS: Loongson64: Set IPI_Enable register per core by itself Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 4/6] MIPS: Loongson64: Add Mail_Send support for 3A4000+ CPU Tiezhu Yang
2020-11-03 7:12 ` [PATCH v3 5/6] MIPS: Loongson64: SMP: Fix up play_dead jump indicator Tiezhu Yang
2020-11-04 6:31 ` Jinyang He
2020-11-04 7:04 ` Jiaxun Yang
2020-11-04 7:18 ` Jinyang He
2020-11-03 7:12 ` [PATCH v3 6/6] MIPS: Loongson64: Move decode_cpucfg() to loongson_regs.h Tiezhu Yang
2020-11-11 23:05 ` Thomas Bogendoerfer
2020-11-11 23:04 ` [PATCH v3 0/6] Modify some registers operations and move " Thomas Bogendoerfer
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