* Re: [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver
@ 2017-08-01 17:08 Rob Herring
0 siblings, 0 replies; 4+ messages in thread
From: Rob Herring @ 2017-08-01 17:08 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: peterz, tglx, jason, Marc Zyngier, Arnd Bergmann,
yamada.masahiro, mmarek, albert, Will Deacon, boqun.feng, oleg,
mingo, Daniel Lezcano, Greg Kroah-Hartman, jslaby, davem,
mchehab, hverkuil, rdunlap, viro, mhiramat, fweisbec, mcgrof,
dledford, bart.vanassche, sstabellini, mpe, rmk+kernel,
paul.gortmaker, nicolas.dichtel, linux, heiko.carstens,
schwidefsky, geert, Andrew Morton, andriy.shevchenko, jiri,
vgupta, airlied, jk, chris, Jason, Paul McKenney, ncardwell,
Linux Kernel Mailing List, linux-kbuild, patches
On Mon, Jul 31, 2017 at 7:59 PM, Palmer Dabbelt <palmer@dabbelt.com> wrote:
> This patch adds a driver that manages the local interrupts on each
> RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual.
> The local interrupt controller manages software interrupts, timer
> interrupts, and hardware interrupts (which are routed via the
> platform level interrupt controller). Per-hart local interrupt
> controllers are found on all RISC-V systems.
>
> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
> ---
> +IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
What happened with the DT bindings? Those need to come first.
Rob
^ permalink raw reply [flat|nested] 4+ messages in thread
* RISC-V Linux Port v7
@ 2017-08-01 0:59 Palmer Dabbelt
2017-08-01 0:59 ` [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
0 siblings, 1 reply; 4+ messages in thread
From: Palmer Dabbelt @ 2017-08-01 0:59 UTC (permalink / raw)
To: peterz, tglx, jason, marc.zyngier, Arnd Bergmann
Cc: yamada.masahiro, mmarek, albert, will.deacon, boqun.feng, oleg,
mingo, daniel.lezcano, gregkh, jslaby, davem, mchehab, hverkuil,
rdunlap, viro, mhiramat, fweisbec, mcgrof, dledford,
bart.vanassche, sstabellini, mpe, rmk+kernel, paul.gortmaker,
nicolas.dichtel, linux, heiko.carstens, schwidefsky, geert, akpm,
andriy.shevchenko, jiri, vgupta, airlied, jk, chris, Jason,
paulmck, ncardwell, linux-kernel, linux-kbuild, patches
It's been a while since my last patch set, but the changes han been fairly
minimal:
* The PCI cleanup patches have been dropped, we'll do them as a separate patch
set later.
* We've the Kconfig entries from CONFIG_ISA_* to CONFIG_RISCV_ISA_*, to make
grep easier.
* There have been a handful of memory model related tweaks in I/O land,
particularly relating the PCI and the upcoming platform specification.
There are significant comments in the relevant files. This is still a WIP,
but I think we're close to getting as good as we're going to get until we
end up with some more specifications.
I'm hoping to begin the push to get this into linux-next now, as I don't know
of any outstanding problems. As usual, if you've send feedback and it hasn't
been incorporated then I'm sorry I missed it -- please either ping me a new
version of the patch or point me to the old one and I'll try to figure it out.
As usual, the patch set is also availiable on github
https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v7
Thanks to everyone for all their help!
[PATCH v7 01/15] MAINTAINERS: Add RISC-V
[PATCH v7 02/15] lib: Add shared copies of some GCC library routines
[PATCH v7 03/15] clocksource: New RISC-V SBI timer driver
[PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver
[PATCH v7 05/15] irqchip: New RISC-V PLIC Driver
[PATCH v7 06/15] tty: New RISC-V SBI console driver
[PATCH v7 07/15] RISC-V: Init and Halt Code
[PATCH v7 08/15] RISC-V: Atomic and Locking Code
[PATCH v7 09/15] RISC-V: Generic library routines and assembly
[PATCH v7 10/15] RISC-V: ELF and module implementation
[PATCH v7 11/15] RISC-V: Task implementation
[PATCH v7 12/15] RISC-V: Device, timer, IRQs, and the SBI
[PATCH v7 13/15] RISC-V: Paging and MMU
[PATCH v7 14/15] RISC-V: User-facing API
[PATCH v7 15/15] RISC-V: Build Infastructure
For reference, here's all the other change messages:
As it's been only a day since the v5 patch set, the changes are pretty minimal:
* The patch set is now based on linux-next/master, which I believe is a better
base now that we're getting closer to upstream.
* EARLY_PRINTK is no longer an option. Since the SBI console is reasonable,
there's no penalty to enabling it (and thus no benefit to disabling it).
* The mmap syscalls were refactored a bit.
Things have really started to calm down, so this is fairly similar to the v4
patch set. The most interesting changes include:
* We've moved back to a single patch set.
* SMP support has been fixed, I was accidentally running on a non-SMP
configuration. There were various mistakes all over the tree as a result of
this.
* The cmpxchg syscalls have been removed, as they were deemed a bad idea. As
a result, RISC-V Linux systems mandate the A extension. The cooresponding
Kconfig entry to enable builds on non-A systems has been removed.
* A few more atomic fixes: mostly fence changes, but those resulted in a
handful of additional macros that were no longer necessary.
* riscv_early_sie has been removed.
There have only been a few changes since the v3 patch set:
* The cmpxchg64 syscall is no longer enabled on 32-bit systems. It's not
possible to provide this on SMP systems, and it's not necessary as glibc
knows not to call it.
* We provide a ELF_HWCAP so users can determine the ISA of the machine the
kernel is running on.
* The multi-line comments are in a better form.
* There were a handful of headers that could be replaced with the asm-generic
versions, and a few unnecessary definitions.
* We no longer use printk, but instead use pr_*.
* A few Kconfig and defconfig entries have been cleaned up.
A highlight of the changes since the v2 patch set includes:
* We've split out all our drivers into separate patch sets, which I've already
sent out to the relevant maintainers. I haven't included those patches in
this patch set, but some of them are necessary to build our port. A git
tree that contains all our patch sets merged together lives at
<https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v3>.
* The patch set is now split up differently: rather than being split per
directory it is split per topic. Hopefully this will make it easier to
review the port on the mailing list. The split is a bit rough, so you
probably still want to look at the patch set as a whole.
* atomic.h has been completely rewritten and is hopefully now correct. I've
attempted to sanitize the various other memory model related code as well,
and I think it should all be sane now aside from a handful of FIXMEs
commented in the code.
* We've changed the cmpexchg syscall to always exist and to not be
multiplexed. There is also a VDSO entry for compare and exchange, which
allows kernels with the A extension to execute user code without the A
extension reasonably fast.
* Our user-visible register state now contains enough space for the Q
extension for 128-bit floating point, as well as a few words to allow
extensibility to future ISA extensions like the eventual V extension for
vectors.
* A handful of driver cleanups, but these have been split into separate patch
sets now so I won't duplicate them here.
A highlight of the changes since the v1 patch set includes:
* We've split out our drivers into the right places, which means now there's
a lot more patches. I'll be submitting these patches to various subsystem
maintainers and including them in any future RISC-V patch sets until
they've been merged.
* The SBI console driver has been completely rewritten to use the HVC helpers
and is now significantly smaller.
* We've begun to use weaker barries as opposed to just the big "fence".
There's still some work to do here, specifically:
- We need fences in the realxed MMIO functions.
- The non-relaxed MMIO functions are missing R/W bits on their fences.
- Many AMOs need the aq and rl bits set.
* We now have thread_info in task_struct. As a result, sscratch now contains
TP instead of SP. This was necessary because thread_info is no longer on
the stack.
* A few shared routines have been added that we use instead of creating
another arch copy.
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver
2017-08-01 0:59 RISC-V Linux Port v7 Palmer Dabbelt
@ 2017-08-01 0:59 ` Palmer Dabbelt
2017-08-01 15:35 ` Randy Dunlap
2017-08-16 15:12 ` Thomas Gleixner
0 siblings, 2 replies; 4+ messages in thread
From: Palmer Dabbelt @ 2017-08-01 0:59 UTC (permalink / raw)
To: peterz, tglx, jason, marc.zyngier, Arnd Bergmann
Cc: yamada.masahiro, mmarek, albert, will.deacon, boqun.feng, oleg,
mingo, daniel.lezcano, gregkh, jslaby, davem, mchehab, hverkuil,
rdunlap, viro, mhiramat, fweisbec, mcgrof, dledford,
bart.vanassche, sstabellini, mpe, rmk+kernel, paul.gortmaker,
nicolas.dichtel, linux, heiko.carstens, schwidefsky, geert, akpm,
andriy.shevchenko, jiri, vgupta, airlied, jk, chris, Jason,
paulmck, ncardwell, linux-kernel, linux-kbuild, patches,
Palmer Dabbelt
This patch adds a driver that manages the local interrupts on each
RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual.
The local interrupt controller manages software interrupts, timer
interrupts, and hardware interrupts (which are routed via the
platform level interrupt controller). Per-hart local interrupt
controllers are found on all RISC-V systems.
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
---
drivers/irqchip/Kconfig | 14 +++
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-riscv-intc.c | 213 +++++++++++++++++++++++++++++++++++++++
3 files changed, 228 insertions(+)
create mode 100644 drivers/irqchip/irq-riscv-intc.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f1fd5f44d1d4..7923d3fa8fae 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -306,3 +306,17 @@ config QCOM_IRQ_COMBINER
help
Say yes here to add support for the IRQ combiner devices embedded
in Qualcomm Technologies chips.
+
+config RISCV_INTC
+ def_bool y if RISCV
+ #bool "RISC-V Interrupt Controller"
+ depends on RISCV
+ default y
+ help
+ This enables support for the local interrupt controller found in
+ standard RISC-V systems. The local interrupt controller handles
+ timer interrupts, software interrupts, and hardware interrupts.
+ Without a local interrupt controller the system will be unable to
+ handle any interrupts, including those passed via the PLIC.
+
+ If you don't know what to do here, say Y.
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index e88d856cc09c..b1aa9114afc4 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -78,3 +78,4 @@ obj-$(CONFIG_EZNPS_GIC) += irq-eznps.o
obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
+obj-$(CONFIG_RISCV_INTC) += irq-riscv-intc.o
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
new file mode 100644
index 000000000000..96ae020cf1d5
--- /dev/null
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -0,0 +1,213 @@
+/*
+ * Copyright (C) 2012 Regents of the University of California
+ * Copyright (C) 2017 SiFive
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/interrupt.h>
+#include <linux/ftrace.h>
+#include <linux/of.h>
+#include <linux/seq_file.h>
+
+#include <asm/ptrace.h>
+#include <asm/sbi.h>
+#include <asm/smp.h>
+
+struct riscv_irq_data {
+ struct irq_chip chip;
+ struct irq_domain *domain;
+ int hart;
+ char name[20];
+};
+DEFINE_PER_CPU(struct riscv_irq_data, riscv_irq_data);
+
+static void riscv_software_interrupt(void)
+{
+#ifdef CONFIG_SMP
+ irqreturn_t ret;
+
+ ret = handle_ipi();
+
+ WARN_ON(ret == IRQ_NONE);
+#else
+ /*
+ * We currently only use software interrupts to pass inter-processor
+ * interrupts, so if a non-SMP system gets a software interrupt then we
+ * don't know what to do.
+ */
+ pr_warning("Software Interrupt without CONFIG_SMP\n");
+#endif
+}
+
+asmlinkage void __irq_entry do_IRQ(unsigned int cause, struct pt_regs *regs)
+{
+ struct pt_regs *old_regs = set_irq_regs(regs);
+ struct irq_domain *domain;
+
+ irq_enter();
+
+ /*
+ * There are three classes of interrupt: timer, software, and
+ * external devices. We dispatch between them here. External
+ * device interrupts use the generic IRQ mechanisms.
+ */
+ switch (cause) {
+ case INTERRUPT_CAUSE_TIMER:
+ riscv_timer_interrupt();
+ break;
+ case INTERRUPT_CAUSE_SOFTWARE:
+ riscv_software_interrupt();
+ break;
+ default:
+ domain = per_cpu(riscv_irq_data, smp_processor_id()).domain;
+ generic_handle_irq(irq_find_mapping(domain, cause));
+ break;
+ }
+
+ irq_exit();
+ set_irq_regs(old_regs);
+}
+
+static int riscv_irqdomain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ struct riscv_irq_data *data = d->host_data;
+
+ irq_set_chip_and_handler(irq, &data->chip, handle_simple_irq);
+ irq_set_chip_data(irq, data);
+ irq_set_noprobe(irq);
+ irq_set_affinity(irq, cpumask_of(data->hart));
+
+ return 0;
+}
+
+static const struct irq_domain_ops riscv_irqdomain_ops = {
+ .map = riscv_irqdomain_map,
+ .xlate = irq_domain_xlate_onecell,
+};
+
+/*
+ * On RISC-V systems local interrupts are masked or unmasked by writing the SIE
+ * (Supervisor Interrupt Enable) CSR. As CSRs can only be written on the local
+ * hart, these functions can only be called on the hart that corresponds to the
+ * IRQ chip. They are only called internally to this module, so they BUG_ON if
+ * this condition is violated rather than attempting to handle the error by
+ * forwarding to the target hart, as that's already expected to have been done.
+ */
+static void riscv_irq_mask(struct irq_data *d)
+{
+ struct riscv_irq_data *data = irq_data_get_irq_chip_data(d);
+
+ BUG_ON(smp_processor_id() != data->hart);
+ csr_clear(sie, 1 << (long)d->hwirq);
+}
+
+static void riscv_irq_unmask(struct irq_data *d)
+{
+ struct riscv_irq_data *data = irq_data_get_irq_chip_data(d);
+
+ BUG_ON(smp_processor_id() != data->hart);
+ csr_set(sie, 1 << (long)d->hwirq);
+}
+
+/* Callbacks for twiddling SIE on another hart. */
+static void riscv_irq_enable_helper(void *d)
+{
+ riscv_irq_unmask(d);
+}
+
+static void riscv_irq_disable_helper(void *d)
+{
+ riscv_irq_mask(d);
+}
+
+static void riscv_irq_enable(struct irq_data *d)
+{
+ struct riscv_irq_data *data = irq_data_get_irq_chip_data(d);
+
+ /*
+ * It's only possible to write SIE on the current hart. This jumps
+ * over to the target hart if it's not the current one. It's invalid
+ * to write SIE on a hart that's not currently running.
+ */
+ if (data->hart == smp_processor_id())
+ riscv_irq_unmask(d);
+ else if (cpu_online(data->hart))
+ smp_call_function_single(data->hart,
+ riscv_irq_enable_helper,
+ d,
+ true);
+ else
+ WARN_ON_ONCE(1);
+}
+
+static void riscv_irq_disable(struct irq_data *d)
+{
+ struct riscv_irq_data *data = irq_data_get_irq_chip_data(d);
+
+ /*
+ * It's only possible to write SIE on the current hart. This jumps
+ * over to the target hart if it's not the current one. It's invalid
+ * to write SIE on a hart that's not currently running.
+ */
+ if (data->hart == smp_processor_id())
+ riscv_irq_mask(d);
+ else if (cpu_online(data->hart))
+ smp_call_function_single(data->hart,
+ riscv_irq_disable_helper,
+ d,
+ true);
+ else
+ WARN_ON_ONCE(1);
+}
+
+static int riscv_intc_init(struct device_node *node, struct device_node *parent)
+{
+ int hart;
+ struct riscv_irq_data *data;
+
+ if (parent)
+ return 0;
+
+ hart = riscv_of_processor_hart(node->parent);
+ if (hart < 0)
+ return -EIO;
+
+ data = &per_cpu(riscv_irq_data, hart);
+ snprintf(data->name, sizeof(data->name), "riscv,cpu_intc,%d", hart);
+ data->hart = hart;
+ data->chip.name = data->name;
+ data->chip.irq_mask = riscv_irq_mask;
+ data->chip.irq_unmask = riscv_irq_unmask;
+ data->chip.irq_enable = riscv_irq_enable;
+ data->chip.irq_disable = riscv_irq_disable;
+ data->domain = irq_domain_add_linear(
+ node,
+ 8*sizeof(uintptr_t),
+ &riscv_irqdomain_ops,
+ data);
+ if (!data->domain)
+ goto error_add_linear;
+ pr_info("%s: %d local interrupts mapped\n",
+ data->name, 8*(int)sizeof(uintptr_t));
+ return 0;
+
+error_add_linear:
+ pr_warning("%s: unable to add IRQ domain\n",
+ data->name);
+ return -(ENXIO);
+
+}
+
+IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
--
2.13.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver
2017-08-01 0:59 ` [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
@ 2017-08-01 15:35 ` Randy Dunlap
2017-08-16 15:12 ` Thomas Gleixner
1 sibling, 0 replies; 4+ messages in thread
From: Randy Dunlap @ 2017-08-01 15:35 UTC (permalink / raw)
To: Palmer Dabbelt, peterz, tglx, jason, marc.zyngier, Arnd Bergmann
Cc: yamada.masahiro, mmarek, albert, will.deacon, boqun.feng, oleg,
mingo, daniel.lezcano, gregkh, jslaby, davem, mchehab, hverkuil,
viro, mhiramat, fweisbec, mcgrof, dledford, bart.vanassche,
sstabellini, mpe, rmk+kernel, paul.gortmaker, nicolas.dichtel,
linux, heiko.carstens, schwidefsky, geert, akpm,
andriy.shevchenko, jiri, vgupta, airlied, jk, chris, Jason,
paulmck, ncardwell, linux-kernel, linux-kbuild, patches
On 07/31/2017 05:59 PM, Palmer Dabbelt wrote:
> This patch adds a driver that manages the local interrupts on each
> RISC-V hart, as specifiec by the RISC-V supervisor level ISA manual.
> The local interrupt controller manages software interrupts, timer
> interrupts, and hardware interrupts (which are routed via the
> platform level interrupt controller). Per-hart local interrupt
> controllers are found on all RISC-V systems.
>
> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
> ---
> drivers/irqchip/Kconfig | 14 +++
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-riscv-intc.c | 213 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 228 insertions(+)
> create mode 100644 drivers/irqchip/irq-riscv-intc.c
> diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
> new file mode 100644
> index 000000000000..96ae020cf1d5
> --- /dev/null
> +++ b/drivers/irqchip/irq-riscv-intc.c
> @@ -0,0 +1,213 @@
> +/*
[]
> +
> +error_add_linear:
> + pr_warning("%s: unable to add IRQ domain\n",
> + data->name);
> + return -(ENXIO);
> +
Why the parentheses around ENXIO? Is it some macro calculation?
Otherwise just use
return -ENXIO;
and drop the following blank line.
> +}
> +
> +IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
>
--
~Randy
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver
2017-08-01 0:59 ` [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
2017-08-01 15:35 ` Randy Dunlap
@ 2017-08-16 15:12 ` Thomas Gleixner
1 sibling, 0 replies; 4+ messages in thread
From: Thomas Gleixner @ 2017-08-16 15:12 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: peterz, jason, marc.zyngier, Arnd Bergmann, yamada.masahiro,
mmarek, albert, will.deacon, boqun.feng, oleg, mingo,
daniel.lezcano, gregkh, jslaby, davem, mchehab, hverkuil,
rdunlap, viro, mhiramat, fweisbec, mcgrof, dledford,
bart.vanassche, sstabellini, mpe, rmk+kernel, paul.gortmaker,
nicolas.dichtel, linux, heiko.carstens, schwidefsky, geert, akpm,
andriy.shevchenko, jiri, vgupta, airlied, jk, chris, Jason,
paulmck, ncardwell, linux-kernel, linux-kbuild, patches
On Mon, 31 Jul 2017, Palmer Dabbelt wrote:
> +static void riscv_software_interrupt(void)
> +{
> +#ifdef CONFIG_SMP
> + irqreturn_t ret;
> +
> + ret = handle_ipi();
> +
> + WARN_ON(ret == IRQ_NONE);
WARN_ON(handle_ipi() == IRQ_NONE);
perhaps?
> +#else
> + /*
> + * We currently only use software interrupts to pass inter-processor
> + * interrupts, so if a non-SMP system gets a software interrupt then we
> + * don't know what to do.
> + */
> + pr_warning("Software Interrupt without CONFIG_SMP\n");
> +#endif
> +}
> +static void riscv_irq_enable(struct irq_data *d)
> +{
> + struct riscv_irq_data *data = irq_data_get_irq_chip_data(d);
> +
> + /*
> + * It's only possible to write SIE on the current hart. This jumps
> + * over to the target hart if it's not the current one. It's invalid
> + * to write SIE on a hart that's not currently running.
> + */
> + if (data->hart == smp_processor_id())
> + riscv_irq_unmask(d);
> + else if (cpu_online(data->hart))
> + smp_call_function_single(data->hart,
> + riscv_irq_enable_helper,
> + d,
> + true);
> + else
> + WARN_ON_ONCE(1);
If you write a small helper:
static void riscv_remote_ctrl(unsigned int cpu, void (*fn)(void *d),
struct irq_data *data)
{
smp_call_function_single(cpu, cb, data, true);
}
Then both riscv_irq_enable() and riscv_irq_disable() become readable
functions.
if (data->hart == smp_processor_id())
riscv_irq_unmask(d);
else if (cpu_online(data->hart))
riscv_remote_ctrl(data->hart, riscv_irq_enable_helper, d);
else
WARN_ON_ONCE(1);
Hmm?
> +static int riscv_intc_init(struct device_node *node, struct device_node *parent)
> +{
> + int hart;
> + struct riscv_irq_data *data;
> +
> + if (parent)
> + return 0;
> +
> + hart = riscv_of_processor_hart(node->parent);
> + if (hart < 0)
> + return -EIO;
> +
> + data = &per_cpu(riscv_irq_data, hart);
> + snprintf(data->name, sizeof(data->name), "riscv,cpu_intc,%d", hart);
> + data->hart = hart;
> + data->chip.name = data->name;
> + data->chip.irq_mask = riscv_irq_mask;
> + data->chip.irq_unmask = riscv_irq_unmask;
> + data->chip.irq_enable = riscv_irq_enable;
> + data->chip.irq_disable = riscv_irq_disable;
> + data->domain = irq_domain_add_linear(
> + node,
> + 8*sizeof(uintptr_t),
> + &riscv_irqdomain_ops,
> + data);
This is really horrible to read. What's wrong with using the full 80 chars?
data->domain = irq_domain_add_linear(node, 8 * sizeof(uintptr_t),
&riscv_irqdomain_ops, data);
> + if (!data->domain)
> + goto error_add_linear;
> + pr_info("%s: %d local interrupts mapped\n",
> + data->name, 8*(int)sizeof(uintptr_t));
Can we please make that '8 * sizeof()' a constant and use it in both
places? Which makes the pr_info also fit into a single line.
> + return 0;
> +
> +error_add_linear:
> + pr_warning("%s: unable to add IRQ domain\n",
> + data->name);
Single line please. Enough room.
> + return -(ENXIO);
No braces.
Thanks,
tglx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2017-08-16 15:14 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2017-08-01 17:08 [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver Rob Herring
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2017-08-01 0:59 RISC-V Linux Port v7 Palmer Dabbelt
2017-08-01 0:59 ` [PATCH v7 04/15] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
2017-08-01 15:35 ` Randy Dunlap
2017-08-16 15:12 ` Thomas Gleixner
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