From: Stephane Eranian <eranian@google.com>
To: Peter Zijlstra <peterz@infradead.org>
Cc: "Liang, Kan" <kan.liang@intel.com>,
"mingo@redhat.com" <mingo@redhat.com>,
LKML <linux-kernel@vger.kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
"ak@linux.intel.com" <ak@linux.intel.com>,
"Odzioba, Lukasz" <lukasz.odzioba@intel.com>
Subject: Re: [PATCH] perf/x86: fix event counter update issue
Date: Tue, 29 Nov 2016 10:11:23 -0800 [thread overview]
Message-ID: <CABPqkBTubyf48Q9rbXfTLwJcZOV-pG9+=qACOhdMLhATs9htBA@mail.gmail.com> (raw)
In-Reply-To: <20161129173055.GP3092@twins.programming.kicks-ass.net>
On Tue, Nov 29, 2016 at 9:30 AM, Peter Zijlstra <peterz@infradead.org> wrote:
> On Tue, Nov 29, 2016 at 09:20:10AM -0800, Stephane Eranian wrote:
>> Max period is limited by the number of bits the kernel can write to an MSR.
>> Used to be 31, now it is 47 for core PMU as per patch pointed to by Kan.
>
> No, I think it sets it to 48 now, which is the problem. It should be 1
> bit less than the total width.
>
> So something like so.
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index a74a2dbc0180..cb8522290e6a 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -4034,7 +4034,7 @@ __init int intel_pmu_init(void)
>
> /* Support full width counters using alternative MSR range */
> if (x86_pmu.intel_cap.full_width_write) {
> - x86_pmu.max_period = x86_pmu.cntval_mask;
> + x86_pmu.max_period = x86_pmu.cntval_mask >> 1;
> x86_pmu.perfctr = MSR_IA32_PMC0;
> pr_cont("full-width counters, ");
> }
Ah, yes!
That would make it consistent with the other Intel PMU settings I see
in intel/core.c such as for
intel_core_pmu.max_period = (1<<31) -1 which is 0x7ffffff whereas now
I see max_period of
0x0000ffffffffffff instead of 0x7fffffffffff. So I think Peter's
patch is required no matter what.
next prev parent reply other threads:[~2016-11-29 18:11 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-28 19:26 [PATCH] perf/x86: fix event counter update issue kan.liang
2016-11-28 19:41 ` Stephane Eranian
2016-11-28 19:59 ` Liang, Kan
2016-11-28 20:18 ` Stephane Eranian
2016-11-28 20:23 ` Liang, Kan
2016-11-29 9:25 ` Peter Zijlstra
2016-11-29 14:46 ` Liang, Kan
2016-11-29 16:58 ` Peter Zijlstra
2016-11-29 17:06 ` Liang, Kan
2016-11-29 17:17 ` Peter Zijlstra
2016-11-29 17:20 ` Stephane Eranian
2016-11-29 17:30 ` Peter Zijlstra
2016-11-29 18:11 ` Stephane Eranian [this message]
2016-11-29 18:37 ` Andi Kleen
2016-11-29 19:07 ` Liang, Kan
2016-11-29 19:32 ` Peter Zijlstra
2016-11-29 20:33 ` Liang, Kan
2016-11-29 20:37 ` Stephane Eranian
2016-12-02 12:58 ` Odzioba, Lukasz
2016-12-05 10:25 ` Peter Zijlstra
2016-12-05 11:21 ` Odzioba, Lukasz
2017-02-22 14:49 ` Vince Weaver
2017-02-22 15:28 ` Liang, Kan
2017-02-22 19:18 ` Andi Kleen
2017-02-23 15:07 ` Vince Weaver
2017-02-23 16:14 ` Liang, Kan
2016-11-29 19:08 ` Odzioba, Lukasz
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