* [PATCH v5 1/7] ARM: dts: aspeed: Add GFX node to AST2600
2021-12-08 1:33 [PATCH v5 0/7] Add Aspeed AST2600 soc display support Tommy Haung
@ 2021-12-08 1:33 ` Tommy Haung
2021-12-08 1:33 ` [PATCH v5 2/7] ARM: dts: aspeed: ast2600-evb: Enable GFX device Tommy Haung
` (6 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Tommy Haung @ 2021-12-08 1:33 UTC (permalink / raw)
To: joel, airlied, daniel, robh+dt, andrew, linux-aspeed, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
Cc: BMC-SW, tommy-huang
From: Joel Stanley <joel@jms.id.au>
The GFX device is present in the AST2600 SoC.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
---
arch/arm/boot/dts/aspeed-g6.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 1b47be1704f8..e38c3742761b 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -351,6 +351,17 @@
quality = <100>;
};
+ gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2600-gfx", "aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ reg-io-width = <4>;
+ clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
+ resets = <&syscon ASPEED_RESET_GRAPHICS>;
+ syscon = <&syscon>;
+ status = "disabled";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
xdma: xdma@1e6e7000 {
compatible = "aspeed,ast2600-xdma";
reg = <0x1e6e7000 0x100>;
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v5 2/7] ARM: dts: aspeed: ast2600-evb: Enable GFX device
2021-12-08 1:33 [PATCH v5 0/7] Add Aspeed AST2600 soc display support Tommy Haung
2021-12-08 1:33 ` [PATCH v5 1/7] ARM: dts: aspeed: Add GFX node to AST2600 Tommy Haung
@ 2021-12-08 1:33 ` Tommy Haung
2021-12-08 1:33 ` [PATCH v5 3/7] drm/aspeed: Update INTR_STS handling Tommy Haung
` (5 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Tommy Haung @ 2021-12-08 1:33 UTC (permalink / raw)
To: joel, airlied, daniel, robh+dt, andrew, linux-aspeed, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
Cc: BMC-SW, tommy-huang
From: Joel Stanley <joel@jms.id.au>
Enable the GFX device with a framebuffer memory region.
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
---
arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
index b7eb552640cb..e223dad2abd0 100644
--- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -23,6 +23,19 @@
reg = <0x80000000 0x80000000>;
};
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gfx_memory: framebuffer {
+ size = <0x01000000>;
+ alignment = <0x01000000>;
+ compatible = "shared-dma-pool";
+ reusable;
+ };
+ };
+
vcc_sdhci0: regulator-vcc-sdhci0 {
compatible = "regulator-fixed";
regulator-name = "SDHCI0 Vcc";
@@ -300,3 +313,8 @@
vqmmc-supply = <&vccq_sdhci1>;
clk-phase-sd-hs = <7>, <200>;
};
+
+&gfx {
+ status = "okay";
+ memory-region = <&gfx_memory>;
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v5 3/7] drm/aspeed: Update INTR_STS handling
2021-12-08 1:33 [PATCH v5 0/7] Add Aspeed AST2600 soc display support Tommy Haung
2021-12-08 1:33 ` [PATCH v5 1/7] ARM: dts: aspeed: Add GFX node to AST2600 Tommy Haung
2021-12-08 1:33 ` [PATCH v5 2/7] ARM: dts: aspeed: ast2600-evb: Enable GFX device Tommy Haung
@ 2021-12-08 1:33 ` Tommy Haung
2021-12-08 1:33 ` [PATCH v5 4/7] drm/aspeed: Add AST2600 chip support Tommy Haung
` (4 subsequent siblings)
7 siblings, 0 replies; 15+ messages in thread
From: Tommy Haung @ 2021-12-08 1:33 UTC (permalink / raw)
To: joel, airlied, daniel, robh+dt, andrew, linux-aspeed, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
Cc: BMC-SW, tommy-huang
From: tommy-huang <tommy_huang@aspeedtech.com>
Add interrupt clear register define for further chip support.
Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
---
drivers/gpu/drm/aspeed/aspeed_gfx.h | 1 +
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 6 +++++-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h b/drivers/gpu/drm/aspeed/aspeed_gfx.h
index 96501152bafa..4e6a442c3886 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
@@ -12,6 +12,7 @@ struct aspeed_gfx {
struct regmap *scu;
u32 dac_reg;
+ u32 int_clr_reg;
u32 vga_scratch_reg;
u32 throd_val;
u32 scan_line_max;
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
index b53fee6f1c17..d4b56b3c7597 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
@@ -60,6 +60,7 @@
struct aspeed_gfx_config {
u32 dac_reg; /* DAC register in SCU */
+ u32 int_clear_reg; /* Interrupt clear register */
u32 vga_scratch_reg; /* VGA scratch register in SCU */
u32 throd_val; /* Default Threshold Seting */
u32 scan_line_max; /* Max memory size of one scan line */
@@ -67,6 +68,7 @@ struct aspeed_gfx_config {
static const struct aspeed_gfx_config ast2400_config = {
.dac_reg = 0x2c,
+ .int_clear_reg = 0x60,
.vga_scratch_reg = 0x50,
.throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12),
.scan_line_max = 64,
@@ -74,6 +76,7 @@ static const struct aspeed_gfx_config ast2400_config = {
static const struct aspeed_gfx_config ast2500_config = {
.dac_reg = 0x2c,
+ .int_clear_reg = 0x60,
.vga_scratch_reg = 0x50,
.throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c),
.scan_line_max = 128,
@@ -119,7 +122,7 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void *data)
if (reg & CRT_CTRL_VERTICAL_INTR_STS) {
drm_crtc_handle_vblank(&priv->pipe.crtc);
- writel(reg, priv->base + CRT_CTRL1);
+ writel(reg, priv->base + priv->int_clr_reg);
return IRQ_HANDLED;
}
@@ -147,6 +150,7 @@ static int aspeed_gfx_load(struct drm_device *drm)
config = match->data;
priv->dac_reg = config->dac_reg;
+ priv->int_clr_reg = config->int_clear_reg;
priv->vga_scratch_reg = config->vga_scratch_reg;
priv->throd_val = config->throd_val;
priv->scan_line_max = config->scan_line_max;
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v5 4/7] drm/aspeed: Add AST2600 chip support
2021-12-08 1:33 [PATCH v5 0/7] Add Aspeed AST2600 soc display support Tommy Haung
` (2 preceding siblings ...)
2021-12-08 1:33 ` [PATCH v5 3/7] drm/aspeed: Update INTR_STS handling Tommy Haung
@ 2021-12-08 1:33 ` Tommy Haung
2022-02-28 9:44 ` Joel Stanley
2021-12-08 1:33 ` [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600 Tommy Haung
` (3 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Tommy Haung @ 2021-12-08 1:33 UTC (permalink / raw)
To: joel, airlied, daniel, robh+dt, andrew, linux-aspeed, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
Cc: BMC-SW, tommy-huang
From: tommy-huang <tommy_huang@aspeedtech.com>
Add AST2600 chip support and setting.
Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
---
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
index d4b56b3c7597..d10246b1d1c2 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
@@ -82,9 +82,18 @@ static const struct aspeed_gfx_config ast2500_config = {
.scan_line_max = 128,
};
+static const struct aspeed_gfx_config ast2600_config = {
+ .dac_reg = 0xc0,
+ .int_clear_reg = 0x68,
+ .vga_scratch_reg = 0x50,
+ .throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
+ .scan_line_max = 128,
+};
+
static const struct of_device_id aspeed_gfx_match[] = {
{ .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
{ .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
+ { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
{ },
};
MODULE_DEVICE_TABLE(of, aspeed_gfx_match);
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v5 4/7] drm/aspeed: Add AST2600 chip support
2021-12-08 1:33 ` [PATCH v5 4/7] drm/aspeed: Add AST2600 chip support Tommy Haung
@ 2022-02-28 9:44 ` Joel Stanley
0 siblings, 0 replies; 15+ messages in thread
From: Joel Stanley @ 2022-02-28 9:44 UTC (permalink / raw)
To: Tommy Haung
Cc: David Airlie, Daniel Vetter, Rob Herring, Andrew Jeffery,
linux-aspeed, open list:DRM DRIVERS, devicetree, Linux ARM,
Linux Kernel Mailing List, BMC-SW
On Wed, 8 Dec 2021 at 01:34, Tommy Haung <tommy_huang@aspeedtech.com> wrote:
>
> From: tommy-huang <tommy_huang@aspeedtech.com>
>
> Add AST2600 chip support and setting.
>
> Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> index d4b56b3c7597..d10246b1d1c2 100644
> --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> @@ -82,9 +82,18 @@ static const struct aspeed_gfx_config ast2500_config = {
> .scan_line_max = 128,
> };
>
> +static const struct aspeed_gfx_config ast2600_config = {
> + .dac_reg = 0xc0,
> + .int_clear_reg = 0x68,
> + .vga_scratch_reg = 0x50,
> + .throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
> + .scan_line_max = 128,
> +};
> +
> static const struct of_device_id aspeed_gfx_match[] = {
> { .compatible = "aspeed,ast2400-gfx", .data = &ast2400_config },
> { .compatible = "aspeed,ast2500-gfx", .data = &ast2500_config },
> + { .compatible = "aspeed,ast2600-gfx", .data = &ast2600_config },
> { },
> };
> MODULE_DEVICE_TABLE(of, aspeed_gfx_match);
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
2021-12-08 1:33 [PATCH v5 0/7] Add Aspeed AST2600 soc display support Tommy Haung
` (3 preceding siblings ...)
2021-12-08 1:33 ` [PATCH v5 4/7] drm/aspeed: Add AST2600 chip support Tommy Haung
@ 2021-12-08 1:33 ` Tommy Haung
2022-02-28 9:50 ` Joel Stanley
2021-12-08 1:33 ` [PATCH v5 6/7] arm:boot:dts:aspeed-g6 Add more gfx reset control Tommy Haung
` (2 subsequent siblings)
7 siblings, 1 reply; 15+ messages in thread
From: Tommy Haung @ 2021-12-08 1:33 UTC (permalink / raw)
To: joel, airlied, daniel, robh+dt, andrew, linux-aspeed, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
Cc: BMC-SW, tommy-huang
From: tommy-huang <tommy_huang@aspeedtech.com>
Add more reset and clock select code for AST2600.
The gfx_flags parameter was added for chip caps idenified.
Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
---
drivers/gpu/drm/aspeed/aspeed_gfx.h | 16 +++++++-
drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 16 ++++++++
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 50 ++++++++++++++++++++++--
3 files changed, 77 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h b/drivers/gpu/drm/aspeed/aspeed_gfx.h
index 4e6a442c3886..2c733225d3c7 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
@@ -8,7 +8,8 @@ struct aspeed_gfx {
struct drm_device drm;
void __iomem *base;
struct clk *clk;
- struct reset_control *rst;
+ struct reset_control *rst_crt;
+ struct reset_control *rst_engine;
struct regmap *scu;
u32 dac_reg;
@@ -16,6 +17,7 @@ struct aspeed_gfx {
u32 vga_scratch_reg;
u32 throd_val;
u32 scan_line_max;
+ u32 flags;
struct drm_simple_display_pipe pipe;
struct drm_connector connector;
@@ -106,3 +108,15 @@ int aspeed_gfx_create_output(struct drm_device *drm);
/* CRT_THROD */
#define CRT_THROD_LOW(x) (x)
#define CRT_THROD_HIGH(x) ((x) << 8)
+
+/* SCU control */
+#define SCU_G6_CLK_COURCE 0x300
+
+/* GFX FLAGS */
+#define RESET_MASK BIT(0)
+#define RESET_G6 BIT(0)
+#define CLK_MASK BIT(4)
+#define CLK_G6 BIT(4)
+
+#define G6_CLK_MASK (BIT(8) | BIT(9) | BIT(10))
+#define G6_USB_40_CLK BIT(9)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
index 827e62c1daba..e0975ecda92d 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
@@ -77,6 +77,18 @@ static void aspeed_gfx_disable_controller(struct aspeed_gfx *priv)
regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0);
}
+static void aspeed_gfx_set_clk(struct aspeed_gfx *priv)
+{
+ switch (priv->flags & CLK_MASK) {
+ case CLK_G6:
+ regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE, G6_CLK_MASK, 0x0);
+ regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE, G6_CLK_MASK, G6_USB_40_CLK);
+ break;
+ default:
+ break;
+ }
+}
+
static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv)
{
struct drm_display_mode *m = &priv->pipe.crtc.state->adjusted_mode;
@@ -87,6 +99,8 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv)
if (err)
return;
+ aspeed_gfx_set_clk(priv);
+
#if 0
/* TODO: we have only been able to test with the 40MHz USB clock. The
* clock is fixed, so we cannot adjust it here. */
@@ -193,6 +207,7 @@ static void aspeed_gfx_pipe_update(struct drm_simple_display_pipe *pipe,
static int aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe)
{
struct aspeed_gfx *priv = drm_pipe_to_aspeed_gfx(pipe);
+
u32 reg = readl(priv->base + CRT_CTRL1);
/* Clear pending VBLANK IRQ */
@@ -207,6 +222,7 @@ static int aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe)
static void aspeed_gfx_disable_vblank(struct drm_simple_display_pipe *pipe)
{
struct aspeed_gfx *priv = drm_pipe_to_aspeed_gfx(pipe);
+
u32 reg = readl(priv->base + CRT_CTRL1);
reg &= ~CRT_CTRL_VERTICAL_INTR_EN;
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
index d10246b1d1c2..59a0de92650f 100644
--- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
+++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
@@ -64,6 +64,7 @@ struct aspeed_gfx_config {
u32 vga_scratch_reg; /* VGA scratch register in SCU */
u32 throd_val; /* Default Threshold Seting */
u32 scan_line_max; /* Max memory size of one scan line */
+ u32 gfx_flags; /* Flags for gfx chip caps */
};
static const struct aspeed_gfx_config ast2400_config = {
@@ -72,6 +73,7 @@ static const struct aspeed_gfx_config ast2400_config = {
.vga_scratch_reg = 0x50,
.throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12),
.scan_line_max = 64,
+ .gfx_flags = 0,
};
static const struct aspeed_gfx_config ast2500_config = {
@@ -80,6 +82,7 @@ static const struct aspeed_gfx_config ast2500_config = {
.vga_scratch_reg = 0x50,
.throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c),
.scan_line_max = 128,
+ .gfx_flags = 0,
};
static const struct aspeed_gfx_config ast2600_config = {
@@ -88,6 +91,7 @@ static const struct aspeed_gfx_config ast2600_config = {
.vga_scratch_reg = 0x50,
.throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
.scan_line_max = 128,
+ .gfx_flags = RESET_G6 | CLK_G6,
};
static const struct of_device_id aspeed_gfx_match[] = {
@@ -138,6 +142,44 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void *data)
return IRQ_NONE;
}
+static int aspeed_gfx_reset(struct drm_device *drm)
+{
+ struct platform_device *pdev = to_platform_device(drm->dev);
+ struct aspeed_gfx *priv = to_aspeed_gfx(drm);
+
+ switch (priv->flags & RESET_MASK) {
+ case RESET_G6:
+ priv->rst_crt = devm_reset_control_get(&pdev->dev, "crt");
+ if (IS_ERR(priv->rst_crt)) {
+ dev_err(&pdev->dev,
+ "missing or invalid crt reset controller device tree entry");
+ return PTR_ERR(priv->rst_crt);
+ }
+ reset_control_deassert(priv->rst_crt);
+
+ priv->rst_engine = devm_reset_control_get(&pdev->dev, "engine");
+ if (IS_ERR(priv->rst_engine)) {
+ dev_err(&pdev->dev,
+ "missing or invalid engine reset controller device tree entry");
+ return PTR_ERR(priv->rst_engine);
+ }
+ reset_control_deassert(priv->rst_engine);
+ break;
+
+ default:
+ priv->rst_crt = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (IS_ERR(priv->rst_crt)) {
+ dev_err(&pdev->dev,
+ "missing or invalid reset controller device tree entry");
+ return PTR_ERR(priv->rst_crt);
+ }
+ reset_control_deassert(priv->rst_crt);
+ break;
+ }
+
+ return 0;
+}
+
static int aspeed_gfx_load(struct drm_device *drm)
{
struct platform_device *pdev = to_platform_device(drm->dev);
@@ -163,6 +205,7 @@ static int aspeed_gfx_load(struct drm_device *drm)
priv->vga_scratch_reg = config->vga_scratch_reg;
priv->throd_val = config->throd_val;
priv->scan_line_max = config->scan_line_max;
+ priv->flags = config->gfx_flags;
priv->scu = syscon_regmap_lookup_by_phandle(np, "syscon");
if (IS_ERR(priv->scu)) {
@@ -186,13 +229,12 @@ static int aspeed_gfx_load(struct drm_device *drm)
return ret;
}
- priv->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
- if (IS_ERR(priv->rst)) {
+ ret = aspeed_gfx_reset(drm);
+ if (ret) {
dev_err(&pdev->dev,
"missing or invalid reset controller device tree entry");
- return PTR_ERR(priv->rst);
+ return ret;
}
- reset_control_deassert(priv->rst);
priv->clk = devm_clk_get(drm->dev, NULL);
if (IS_ERR(priv->clk)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
2021-12-08 1:33 ` [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600 Tommy Haung
@ 2022-02-28 9:50 ` Joel Stanley
2022-03-01 7:00 ` Tommy Huang
0 siblings, 1 reply; 15+ messages in thread
From: Joel Stanley @ 2022-02-28 9:50 UTC (permalink / raw)
To: Tommy Haung
Cc: David Airlie, Daniel Vetter, Rob Herring, Andrew Jeffery,
linux-aspeed, open list:DRM DRIVERS, devicetree, Linux ARM,
Linux Kernel Mailing List, BMC-SW
On Wed, 8 Dec 2021 at 01:34, Tommy Haung <tommy_huang@aspeedtech.com> wrote:
>
> From: tommy-huang <tommy_huang@aspeedtech.com>
>
> Add more reset and clock select code for AST2600.
> The gfx_flags parameter was added for chip caps idenified.
Can you tell me a bit more about the two reset lines:
What is the CRT reset line controlling?
What does the engine reset line control?
Can we use devm_reset_control_array_get() to get whichever are
specified in the device tree, so we don't need to have different logic
for the 2600 and earlier chips?
>
> Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
> ---
> drivers/gpu/drm/aspeed/aspeed_gfx.h | 16 +++++++-
> drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 16 ++++++++
> drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 50 ++++++++++++++++++++++--
> 3 files changed, 77 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> index 4e6a442c3886..2c733225d3c7 100644
> --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> @@ -8,7 +8,8 @@ struct aspeed_gfx {
> struct drm_device drm;
> void __iomem *base;
> struct clk *clk;
> - struct reset_control *rst;
> + struct reset_control *rst_crt;
> + struct reset_control *rst_engine;
> struct regmap *scu;
>
> u32 dac_reg;
> @@ -16,6 +17,7 @@ struct aspeed_gfx {
> u32 vga_scratch_reg;
> u32 throd_val;
> u32 scan_line_max;
> + u32 flags;
>
> struct drm_simple_display_pipe pipe;
> struct drm_connector connector;
> @@ -106,3 +108,15 @@ int aspeed_gfx_create_output(struct drm_device *drm);
> /* CRT_THROD */
> #define CRT_THROD_LOW(x) (x)
> #define CRT_THROD_HIGH(x) ((x) << 8)
> +
> +/* SCU control */
> +#define SCU_G6_CLK_COURCE 0x300
> +
> +/* GFX FLAGS */
> +#define RESET_MASK BIT(0)
> +#define RESET_G6 BIT(0)
> +#define CLK_MASK BIT(4)
> +#define CLK_G6 BIT(4)
> +
> +#define G6_CLK_MASK (BIT(8) | BIT(9) | BIT(10))
> +#define G6_USB_40_CLK BIT(9)
> diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> index 827e62c1daba..e0975ecda92d 100644
> --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> @@ -77,6 +77,18 @@ static void aspeed_gfx_disable_controller(struct aspeed_gfx *priv)
> regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0);
> }
>
> +static void aspeed_gfx_set_clk(struct aspeed_gfx *priv)
> +{
> + switch (priv->flags & CLK_MASK) {
> + case CLK_G6:
> + regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE, G6_CLK_MASK, 0x0);
> + regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE, G6_CLK_MASK, G6_USB_40_CLK);
> + break;
> + default:
> + break;
> + }
> +}
> +
> static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv)
> {
> struct drm_display_mode *m = &priv->pipe.crtc.state->adjusted_mode;
> @@ -87,6 +99,8 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv)
> if (err)
> return;
>
> + aspeed_gfx_set_clk(priv);
> +
> #if 0
> /* TODO: we have only been able to test with the 40MHz USB clock. The
> * clock is fixed, so we cannot adjust it here. */
> @@ -193,6 +207,7 @@ static void aspeed_gfx_pipe_update(struct drm_simple_display_pipe *pipe,
> static int aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe)
> {
> struct aspeed_gfx *priv = drm_pipe_to_aspeed_gfx(pipe);
> +
> u32 reg = readl(priv->base + CRT_CTRL1);
>
> /* Clear pending VBLANK IRQ */
> @@ -207,6 +222,7 @@ static int aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe)
> static void aspeed_gfx_disable_vblank(struct drm_simple_display_pipe *pipe)
> {
> struct aspeed_gfx *priv = drm_pipe_to_aspeed_gfx(pipe);
> +
> u32 reg = readl(priv->base + CRT_CTRL1);
>
> reg &= ~CRT_CTRL_VERTICAL_INTR_EN;
> diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> index d10246b1d1c2..59a0de92650f 100644
> --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> @@ -64,6 +64,7 @@ struct aspeed_gfx_config {
> u32 vga_scratch_reg; /* VGA scratch register in SCU */
> u32 throd_val; /* Default Threshold Seting */
> u32 scan_line_max; /* Max memory size of one scan line */
> + u32 gfx_flags; /* Flags for gfx chip caps */
> };
>
> static const struct aspeed_gfx_config ast2400_config = {
> @@ -72,6 +73,7 @@ static const struct aspeed_gfx_config ast2400_config = {
> .vga_scratch_reg = 0x50,
> .throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12),
> .scan_line_max = 64,
> + .gfx_flags = 0,
> };
>
> static const struct aspeed_gfx_config ast2500_config = {
> @@ -80,6 +82,7 @@ static const struct aspeed_gfx_config ast2500_config = {
> .vga_scratch_reg = 0x50,
> .throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c),
> .scan_line_max = 128,
> + .gfx_flags = 0,
> };
>
> static const struct aspeed_gfx_config ast2600_config = {
> @@ -88,6 +91,7 @@ static const struct aspeed_gfx_config ast2600_config = {
> .vga_scratch_reg = 0x50,
> .throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
> .scan_line_max = 128,
> + .gfx_flags = RESET_G6 | CLK_G6,
> };
>
> static const struct of_device_id aspeed_gfx_match[] = {
> @@ -138,6 +142,44 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void *data)
> return IRQ_NONE;
> }
>
> +static int aspeed_gfx_reset(struct drm_device *drm)
> +{
> + struct platform_device *pdev = to_platform_device(drm->dev);
> + struct aspeed_gfx *priv = to_aspeed_gfx(drm);
> +
> + switch (priv->flags & RESET_MASK) {
> + case RESET_G6:
> + priv->rst_crt = devm_reset_control_get(&pdev->dev, "crt");
> + if (IS_ERR(priv->rst_crt)) {
> + dev_err(&pdev->dev,
> + "missing or invalid crt reset controller device tree entry");
> + return PTR_ERR(priv->rst_crt);
> + }
> + reset_control_deassert(priv->rst_crt);
> +
> + priv->rst_engine = devm_reset_control_get(&pdev->dev, "engine");
> + if (IS_ERR(priv->rst_engine)) {
> + dev_err(&pdev->dev,
> + "missing or invalid engine reset controller device tree entry");
> + return PTR_ERR(priv->rst_engine);
> + }
> + reset_control_deassert(priv->rst_engine);
> + break;
> +
> + default:
> + priv->rst_crt = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> + if (IS_ERR(priv->rst_crt)) {
> + dev_err(&pdev->dev,
> + "missing or invalid reset controller device tree entry");
> + return PTR_ERR(priv->rst_crt);
> + }
> + reset_control_deassert(priv->rst_crt);
> + break;
> + }
> +
> + return 0;
> +}
> +
> static int aspeed_gfx_load(struct drm_device *drm)
> {
> struct platform_device *pdev = to_platform_device(drm->dev);
> @@ -163,6 +205,7 @@ static int aspeed_gfx_load(struct drm_device *drm)
> priv->vga_scratch_reg = config->vga_scratch_reg;
> priv->throd_val = config->throd_val;
> priv->scan_line_max = config->scan_line_max;
> + priv->flags = config->gfx_flags;
>
> priv->scu = syscon_regmap_lookup_by_phandle(np, "syscon");
> if (IS_ERR(priv->scu)) {
> @@ -186,13 +229,12 @@ static int aspeed_gfx_load(struct drm_device *drm)
> return ret;
> }
>
> - priv->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> - if (IS_ERR(priv->rst)) {
> + ret = aspeed_gfx_reset(drm);
> + if (ret) {
> dev_err(&pdev->dev,
> "missing or invalid reset controller device tree entry");
> - return PTR_ERR(priv->rst);
> + return ret;
> }
> - reset_control_deassert(priv->rst);
>
> priv->clk = devm_clk_get(drm->dev, NULL);
> if (IS_ERR(priv->clk)) {
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
2022-02-28 9:50 ` Joel Stanley
@ 2022-03-01 7:00 ` Tommy Huang
2022-03-01 11:04 ` Joel Stanley
0 siblings, 1 reply; 15+ messages in thread
From: Tommy Huang @ 2022-03-01 7:00 UTC (permalink / raw)
To: Joel Stanley
Cc: David Airlie, Daniel Vetter, Rob Herring, Andrew Jeffery,
linux-aspeed, open list:DRM DRIVERS, devicetree, Linux ARM,
Linux Kernel Mailing List, BMC-SW
Hi Joel,
It seems that the reset control could keep original code behavior.
Just change the reset define in the .dtsi file from ASPEED_RESET_CRT1 into ASPEED_RESET_GRAPHICS.
By the way, the HW controller states and FW programming register will be reset by CRT reset line.
And another part HW controller states will be reset by engine reset line.
Thanks,
By Tommy
> -----Original Message-----
> From: Joel Stanley <joel@jms.id.au>
> Sent: Monday, February 28, 2022 5:51 PM
> To: Tommy Huang <tommy_huang@aspeedtech.com>
> Cc: David Airlie <airlied@linux.ie>; Daniel Vetter <daniel@ffwll.ch>; Rob
> Herring <robh+dt@kernel.org>; Andrew Jeffery <andrew@aj.id.au>;
> linux-aspeed <linux-aspeed@lists.ozlabs.org>; open list:DRM DRIVERS
> <dri-devel@lists.freedesktop.org>; devicetree <devicetree@vger.kernel.org>;
> Linux ARM <linux-arm-kernel@lists.infradead.org>; Linux Kernel Mailing List
> <linux-kernel@vger.kernel.org>; BMC-SW <BMC-SW@aspeedtech.com>
> Subject: Re: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
>
> On Wed, 8 Dec 2021 at 01:34, Tommy Haung
> <tommy_huang@aspeedtech.com> wrote:
> >
> > From: tommy-huang <tommy_huang@aspeedtech.com>
> >
> > Add more reset and clock select code for AST2600.
> > The gfx_flags parameter was added for chip caps idenified.
>
> Can you tell me a bit more about the two reset lines:
>
> What is the CRT reset line controlling?
>
> What does the engine reset line control?
>
> Can we use devm_reset_control_array_get() to get whichever are specified in
> the device tree, so we don't need to have different logic for the 2600 and
> earlier chips?
>
>
>
> >
> > Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
> > ---
> > drivers/gpu/drm/aspeed/aspeed_gfx.h | 16 +++++++-
> > drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 16 ++++++++
> > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 50
> ++++++++++++++++++++++--
> > 3 files changed, 77 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > index 4e6a442c3886..2c733225d3c7 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > @@ -8,7 +8,8 @@ struct aspeed_gfx {
> > struct drm_device drm;
> > void __iomem *base;
> > struct clk *clk;
> > - struct reset_control *rst;
> > + struct reset_control *rst_crt;
> > + struct reset_control *rst_engine;
> > struct regmap *scu;
> >
> > u32 dac_reg;
> > @@ -16,6 +17,7 @@ struct aspeed_gfx {
> > u32 vga_scratch_reg;
> > u32 throd_val;
> > u32 scan_line_max;
> > + u32 flags;
> >
> > struct drm_simple_display_pipe pipe;
> > struct drm_connector connector;
> > @@ -106,3 +108,15 @@ int aspeed_gfx_create_output(struct drm_device
> > *drm);
> > /* CRT_THROD */
> > #define CRT_THROD_LOW(x) (x)
> > #define CRT_THROD_HIGH(x) ((x) << 8)
> > +
> > +/* SCU control */
> > +#define SCU_G6_CLK_COURCE 0x300
> > +
> > +/* GFX FLAGS */
> > +#define RESET_MASK BIT(0)
> > +#define RESET_G6 BIT(0)
> > +#define CLK_MASK BIT(4)
> > +#define CLK_G6 BIT(4)
> > +
> > +#define G6_CLK_MASK (BIT(8) | BIT(9) | BIT(10))
> > +#define G6_USB_40_CLK BIT(9)
> > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > index 827e62c1daba..e0975ecda92d 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > @@ -77,6 +77,18 @@ static void aspeed_gfx_disable_controller(struct
> aspeed_gfx *priv)
> > regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0); }
> >
> > +static void aspeed_gfx_set_clk(struct aspeed_gfx *priv) {
> > + switch (priv->flags & CLK_MASK) {
> > + case CLK_G6:
> > + regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE,
> G6_CLK_MASK, 0x0);
> > + regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE,
> G6_CLK_MASK, G6_USB_40_CLK);
> > + break;
> > + default:
> > + break;
> > + }
> > +}
> > +
> > static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) {
> > struct drm_display_mode *m =
> > &priv->pipe.crtc.state->adjusted_mode;
> > @@ -87,6 +99,8 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct
> aspeed_gfx *priv)
> > if (err)
> > return;
> >
> > + aspeed_gfx_set_clk(priv);
> > +
> > #if 0
> > /* TODO: we have only been able to test with the 40MHz USB
> clock. The
> > * clock is fixed, so we cannot adjust it here. */ @@ -193,6
> > +207,7 @@ static void aspeed_gfx_pipe_update(struct
> > drm_simple_display_pipe *pipe, static int
> > aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe) {
> > struct aspeed_gfx *priv = drm_pipe_to_aspeed_gfx(pipe);
> > +
> > u32 reg = readl(priv->base + CRT_CTRL1);
> >
> > /* Clear pending VBLANK IRQ */ @@ -207,6 +222,7 @@ static int
> > aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe) static
> > void aspeed_gfx_disable_vblank(struct drm_simple_display_pipe *pipe)
> > {
> > struct aspeed_gfx *priv = drm_pipe_to_aspeed_gfx(pipe);
> > +
> > u32 reg = readl(priv->base + CRT_CTRL1);
> >
> > reg &= ~CRT_CTRL_VERTICAL_INTR_EN; diff --git
> > a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > index d10246b1d1c2..59a0de92650f 100644
> > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > @@ -64,6 +64,7 @@ struct aspeed_gfx_config {
> > u32 vga_scratch_reg; /* VGA scratch register in SCU */
> > u32 throd_val; /* Default Threshold Seting */
> > u32 scan_line_max; /* Max memory size of one scan line */
> > + u32 gfx_flags; /* Flags for gfx chip caps */
> > };
> >
> > static const struct aspeed_gfx_config ast2400_config = { @@ -72,6
> > +73,7 @@ static const struct aspeed_gfx_config ast2400_config = {
> > .vga_scratch_reg = 0x50,
> > .throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12),
> > .scan_line_max = 64,
> > + .gfx_flags = 0,
> > };
> >
> > static const struct aspeed_gfx_config ast2500_config = { @@ -80,6
> > +82,7 @@ static const struct aspeed_gfx_config ast2500_config = {
> > .vga_scratch_reg = 0x50,
> > .throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c),
> > .scan_line_max = 128,
> > + .gfx_flags = 0,
> > };
> >
> > static const struct aspeed_gfx_config ast2600_config = { @@ -88,6
> > +91,7 @@ static const struct aspeed_gfx_config ast2600_config = {
> > .vga_scratch_reg = 0x50,
> > .throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
> > .scan_line_max = 128,
> > + .gfx_flags = RESET_G6 | CLK_G6,
> > };
> >
> > static const struct of_device_id aspeed_gfx_match[] = { @@ -138,6
> > +142,44 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void *data)
> > return IRQ_NONE;
> > }
> >
> > +static int aspeed_gfx_reset(struct drm_device *drm) {
> > + struct platform_device *pdev = to_platform_device(drm->dev);
> > + struct aspeed_gfx *priv = to_aspeed_gfx(drm);
> > +
> > + switch (priv->flags & RESET_MASK) {
> > + case RESET_G6:
> > + priv->rst_crt = devm_reset_control_get(&pdev->dev,
> "crt");
> > + if (IS_ERR(priv->rst_crt)) {
> > + dev_err(&pdev->dev,
> > + "missing or invalid crt reset controller
> device tree entry");
> > + return PTR_ERR(priv->rst_crt);
> > + }
> > + reset_control_deassert(priv->rst_crt);
> > +
> > + priv->rst_engine = devm_reset_control_get(&pdev->dev,
> "engine");
> > + if (IS_ERR(priv->rst_engine)) {
> > + dev_err(&pdev->dev,
> > + "missing or invalid engine reset
> controller device tree entry");
> > + return PTR_ERR(priv->rst_engine);
> > + }
> > + reset_control_deassert(priv->rst_engine);
> > + break;
> > +
> > + default:
> > + priv->rst_crt =
> devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > + if (IS_ERR(priv->rst_crt)) {
> > + dev_err(&pdev->dev,
> > + "missing or invalid reset controller
> device tree entry");
> > + return PTR_ERR(priv->rst_crt);
> > + }
> > + reset_control_deassert(priv->rst_crt);
> > + break;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static int aspeed_gfx_load(struct drm_device *drm) {
> > struct platform_device *pdev = to_platform_device(drm->dev);
> > @@ -163,6 +205,7 @@ static int aspeed_gfx_load(struct drm_device *drm)
> > priv->vga_scratch_reg = config->vga_scratch_reg;
> > priv->throd_val = config->throd_val;
> > priv->scan_line_max = config->scan_line_max;
> > + priv->flags = config->gfx_flags;
> >
> > priv->scu = syscon_regmap_lookup_by_phandle(np, "syscon");
> > if (IS_ERR(priv->scu)) {
> > @@ -186,13 +229,12 @@ static int aspeed_gfx_load(struct drm_device
> *drm)
> > return ret;
> > }
> >
> > - priv->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > - if (IS_ERR(priv->rst)) {
> > + ret = aspeed_gfx_reset(drm);
> > + if (ret) {
> > dev_err(&pdev->dev,
> > "missing or invalid reset controller device tree
> entry");
> > - return PTR_ERR(priv->rst);
> > + return ret;
> > }
> > - reset_control_deassert(priv->rst);
> >
> > priv->clk = devm_clk_get(drm->dev, NULL);
> > if (IS_ERR(priv->clk)) {
> > --
> > 2.17.1
> >
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
2022-03-01 7:00 ` Tommy Huang
@ 2022-03-01 11:04 ` Joel Stanley
2022-03-02 0:04 ` Tommy Huang
0 siblings, 1 reply; 15+ messages in thread
From: Joel Stanley @ 2022-03-01 11:04 UTC (permalink / raw)
To: Tommy Huang
Cc: David Airlie, Daniel Vetter, Rob Herring, Andrew Jeffery,
linux-aspeed, open list:DRM DRIVERS, devicetree, Linux ARM,
Linux Kernel Mailing List, BMC-SW
On Tue, 1 Mar 2022 at 07:00, Tommy Huang <tommy_huang@aspeedtech.com> wrote:
>
> Hi Joel,
>
> It seems that the reset control could keep original code behavior.
> Just change the reset define in the .dtsi file from ASPEED_RESET_CRT1 into ASPEED_RESET_GRAPHICS.
Right, because the ASPEED_RESET_CRT reset is released by the
ASPEED_CLK_GATE_D1CLK line?
include/dt-bindings/clock/ast2600-clock.h:#define ASPEED_RESET_CRT
13
drivers/clk/clk-ast2600.c: /*
clk rst name parent flags */
drivers/clk/clk-ast2600.c: [ASPEED_CLK_GATE_D1CLK] = {
10, 13, "d1clk-gate", "d1clk", 0 >
>
> By the way, the HW controller states and FW programming register will be reset by CRT reset line.
> And another part HW controller states will be reset by engine reset line.
Thanks. Can we include that in the commit message for the device tree change?
>
> Thanks,
>
> By Tommy
>
> > -----Original Message-----
> > From: Joel Stanley <joel@jms.id.au>
> > Sent: Monday, February 28, 2022 5:51 PM
> > To: Tommy Huang <tommy_huang@aspeedtech.com>
> > Cc: David Airlie <airlied@linux.ie>; Daniel Vetter <daniel@ffwll.ch>; Rob
> > Herring <robh+dt@kernel.org>; Andrew Jeffery <andrew@aj.id.au>;
> > linux-aspeed <linux-aspeed@lists.ozlabs.org>; open list:DRM DRIVERS
> > <dri-devel@lists.freedesktop.org>; devicetree <devicetree@vger.kernel.org>;
> > Linux ARM <linux-arm-kernel@lists.infradead.org>; Linux Kernel Mailing List
> > <linux-kernel@vger.kernel.org>; BMC-SW <BMC-SW@aspeedtech.com>
> > Subject: Re: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
> >
> > On Wed, 8 Dec 2021 at 01:34, Tommy Haung
> > <tommy_huang@aspeedtech.com> wrote:
> > >
> > > From: tommy-huang <tommy_huang@aspeedtech.com>
> > >
> > > Add more reset and clock select code for AST2600.
> > > The gfx_flags parameter was added for chip caps idenified.
> >
> > Can you tell me a bit more about the two reset lines:
> >
> > What is the CRT reset line controlling?
> >
> > What does the engine reset line control?
> >
> > Can we use devm_reset_control_array_get() to get whichever are specified in
> > the device tree, so we don't need to have different logic for the 2600 and
> > earlier chips?
> >
> >
> >
> > >
> > > Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
> > > ---
> > > drivers/gpu/drm/aspeed/aspeed_gfx.h | 16 +++++++-
> > > drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 16 ++++++++
> > > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 50
> > ++++++++++++++++++++++--
> > > 3 files changed, 77 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > index 4e6a442c3886..2c733225d3c7 100644
> > > --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > @@ -8,7 +8,8 @@ struct aspeed_gfx {
> > > struct drm_device drm;
> > > void __iomem *base;
> > > struct clk *clk;
> > > - struct reset_control *rst;
> > > + struct reset_control *rst_crt;
> > > + struct reset_control *rst_engine;
> > > struct regmap *scu;
> > >
> > > u32 dac_reg;
> > > @@ -16,6 +17,7 @@ struct aspeed_gfx {
> > > u32 vga_scratch_reg;
> > > u32 throd_val;
> > > u32 scan_line_max;
> > > + u32 flags;
> > >
> > > struct drm_simple_display_pipe pipe;
> > > struct drm_connector connector;
> > > @@ -106,3 +108,15 @@ int aspeed_gfx_create_output(struct drm_device
> > > *drm);
> > > /* CRT_THROD */
> > > #define CRT_THROD_LOW(x) (x)
> > > #define CRT_THROD_HIGH(x) ((x) << 8)
> > > +
> > > +/* SCU control */
> > > +#define SCU_G6_CLK_COURCE 0x300
> > > +
> > > +/* GFX FLAGS */
> > > +#define RESET_MASK BIT(0)
> > > +#define RESET_G6 BIT(0)
> > > +#define CLK_MASK BIT(4)
> > > +#define CLK_G6 BIT(4)
> > > +
> > > +#define G6_CLK_MASK (BIT(8) | BIT(9) | BIT(10))
> > > +#define G6_USB_40_CLK BIT(9)
> > > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > index 827e62c1daba..e0975ecda92d 100644
> > > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > @@ -77,6 +77,18 @@ static void aspeed_gfx_disable_controller(struct
> > aspeed_gfx *priv)
> > > regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0); }
> > >
> > > +static void aspeed_gfx_set_clk(struct aspeed_gfx *priv) {
> > > + switch (priv->flags & CLK_MASK) {
> > > + case CLK_G6:
> > > + regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE,
> > G6_CLK_MASK, 0x0);
> > > + regmap_update_bits(priv->scu, SCU_G6_CLK_COURCE,
> > G6_CLK_MASK, G6_USB_40_CLK);
> > > + break;
> > > + default:
> > > + break;
> > > + }
> > > +}
> > > +
> > > static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) {
> > > struct drm_display_mode *m =
> > > &priv->pipe.crtc.state->adjusted_mode;
> > > @@ -87,6 +99,8 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct
> > aspeed_gfx *priv)
> > > if (err)
> > > return;
> > >
> > > + aspeed_gfx_set_clk(priv);
> > > +
> > > #if 0
> > > /* TODO: we have only been able to test with the 40MHz USB
> > clock. The
> > > * clock is fixed, so we cannot adjust it here. */ @@ -193,6
> > > +207,7 @@ static void aspeed_gfx_pipe_update(struct
> > > drm_simple_display_pipe *pipe, static int
> > > aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe) {
> > > struct aspeed_gfx *priv = drm_pipe_to_aspeed_gfx(pipe);
> > > +
> > > u32 reg = readl(priv->base + CRT_CTRL1);
> > >
> > > /* Clear pending VBLANK IRQ */ @@ -207,6 +222,7 @@ static int
> > > aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe) static
> > > void aspeed_gfx_disable_vblank(struct drm_simple_display_pipe *pipe)
> > > {
> > > struct aspeed_gfx *priv = drm_pipe_to_aspeed_gfx(pipe);
> > > +
> > > u32 reg = readl(priv->base + CRT_CTRL1);
> > >
> > > reg &= ~CRT_CTRL_VERTICAL_INTR_EN; diff --git
> > > a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > > b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > > index d10246b1d1c2..59a0de92650f 100644
> > > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > > @@ -64,6 +64,7 @@ struct aspeed_gfx_config {
> > > u32 vga_scratch_reg; /* VGA scratch register in SCU */
> > > u32 throd_val; /* Default Threshold Seting */
> > > u32 scan_line_max; /* Max memory size of one scan line */
> > > + u32 gfx_flags; /* Flags for gfx chip caps */
> > > };
> > >
> > > static const struct aspeed_gfx_config ast2400_config = { @@ -72,6
> > > +73,7 @@ static const struct aspeed_gfx_config ast2400_config = {
> > > .vga_scratch_reg = 0x50,
> > > .throd_val = CRT_THROD_LOW(0x1e) | CRT_THROD_HIGH(0x12),
> > > .scan_line_max = 64,
> > > + .gfx_flags = 0,
> > > };
> > >
> > > static const struct aspeed_gfx_config ast2500_config = { @@ -80,6
> > > +82,7 @@ static const struct aspeed_gfx_config ast2500_config = {
> > > .vga_scratch_reg = 0x50,
> > > .throd_val = CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3c),
> > > .scan_line_max = 128,
> > > + .gfx_flags = 0,
> > > };
> > >
> > > static const struct aspeed_gfx_config ast2600_config = { @@ -88,6
> > > +91,7 @@ static const struct aspeed_gfx_config ast2600_config = {
> > > .vga_scratch_reg = 0x50,
> > > .throd_val = CRT_THROD_LOW(0x50) | CRT_THROD_HIGH(0x70),
> > > .scan_line_max = 128,
> > > + .gfx_flags = RESET_G6 | CLK_G6,
> > > };
> > >
> > > static const struct of_device_id aspeed_gfx_match[] = { @@ -138,6
> > > +142,44 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void *data)
> > > return IRQ_NONE;
> > > }
> > >
> > > +static int aspeed_gfx_reset(struct drm_device *drm) {
> > > + struct platform_device *pdev = to_platform_device(drm->dev);
> > > + struct aspeed_gfx *priv = to_aspeed_gfx(drm);
> > > +
> > > + switch (priv->flags & RESET_MASK) {
> > > + case RESET_G6:
> > > + priv->rst_crt = devm_reset_control_get(&pdev->dev,
> > "crt");
> > > + if (IS_ERR(priv->rst_crt)) {
> > > + dev_err(&pdev->dev,
> > > + "missing or invalid crt reset controller
> > device tree entry");
> > > + return PTR_ERR(priv->rst_crt);
> > > + }
> > > + reset_control_deassert(priv->rst_crt);
> > > +
> > > + priv->rst_engine = devm_reset_control_get(&pdev->dev,
> > "engine");
> > > + if (IS_ERR(priv->rst_engine)) {
> > > + dev_err(&pdev->dev,
> > > + "missing or invalid engine reset
> > controller device tree entry");
> > > + return PTR_ERR(priv->rst_engine);
> > > + }
> > > + reset_control_deassert(priv->rst_engine);
> > > + break;
> > > +
> > > + default:
> > > + priv->rst_crt =
> > devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > > + if (IS_ERR(priv->rst_crt)) {
> > > + dev_err(&pdev->dev,
> > > + "missing or invalid reset controller
> > device tree entry");
> > > + return PTR_ERR(priv->rst_crt);
> > > + }
> > > + reset_control_deassert(priv->rst_crt);
> > > + break;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > static int aspeed_gfx_load(struct drm_device *drm) {
> > > struct platform_device *pdev = to_platform_device(drm->dev);
> > > @@ -163,6 +205,7 @@ static int aspeed_gfx_load(struct drm_device *drm)
> > > priv->vga_scratch_reg = config->vga_scratch_reg;
> > > priv->throd_val = config->throd_val;
> > > priv->scan_line_max = config->scan_line_max;
> > > + priv->flags = config->gfx_flags;
> > >
> > > priv->scu = syscon_regmap_lookup_by_phandle(np, "syscon");
> > > if (IS_ERR(priv->scu)) {
> > > @@ -186,13 +229,12 @@ static int aspeed_gfx_load(struct drm_device
> > *drm)
> > > return ret;
> > > }
> > >
> > > - priv->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > > - if (IS_ERR(priv->rst)) {
> > > + ret = aspeed_gfx_reset(drm);
> > > + if (ret) {
> > > dev_err(&pdev->dev,
> > > "missing or invalid reset controller device tree
> > entry");
> > > - return PTR_ERR(priv->rst);
> > > + return ret;
> > > }
> > > - reset_control_deassert(priv->rst);
> > >
> > > priv->clk = devm_clk_get(drm->dev, NULL);
> > > if (IS_ERR(priv->clk)) {
> > > --
> > > 2.17.1
> > >
^ permalink raw reply [flat|nested] 15+ messages in thread* RE: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
2022-03-01 11:04 ` Joel Stanley
@ 2022-03-02 0:04 ` Tommy Huang
0 siblings, 0 replies; 15+ messages in thread
From: Tommy Huang @ 2022-03-02 0:04 UTC (permalink / raw)
To: Joel Stanley
Cc: David Airlie, Daniel Vetter, Rob Herring, Andrew Jeffery,
linux-aspeed, open list:DRM DRIVERS, devicetree, Linux ARM,
Linux Kernel Mailing List, BMC-SW
Hi Joel,
> -----Original Message-----
> From: Joel Stanley <joel@jms.id.au>
> Sent: Tuesday, March 1, 2022 7:05 PM
> To: Tommy Huang <tommy_huang@aspeedtech.com>
> Cc: David Airlie <airlied@linux.ie>; Daniel Vetter <daniel@ffwll.ch>; Rob
> Herring <robh+dt@kernel.org>; Andrew Jeffery <andrew@aj.id.au>;
> linux-aspeed <linux-aspeed@lists.ozlabs.org>; open list:DRM DRIVERS
> <dri-devel@lists.freedesktop.org>; devicetree <devicetree@vger.kernel.org>;
> Linux ARM <linux-arm-kernel@lists.infradead.org>; Linux Kernel Mailing List
> <linux-kernel@vger.kernel.org>; BMC-SW <BMC-SW@aspeedtech.com>
> Subject: Re: [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600
>
> On Tue, 1 Mar 2022 at 07:00, Tommy Huang
> <tommy_huang@aspeedtech.com> wrote:
> >
> > Hi Joel,
> >
> > It seems that the reset control could keep original code behavior.
> > Just change the reset define in the .dtsi file from
> ASPEED_RESET_CRT1 into ASPEED_RESET_GRAPHICS.
>
> Right, because the ASPEED_RESET_CRT reset is released by the
> ASPEED_CLK_GATE_D1CLK line?
>
> include/dt-bindings/clock/ast2600-clock.h:#define ASPEED_RESET_CRT
> 13
>
> drivers/clk/clk-ast2600.c: /*
> clk rst name parent flags */
> drivers/clk/clk-ast2600.c: [ASPEED_CLK_GATE_D1CLK] = {
> 10, 13, "d1clk-gate", "d1clk", 0 >
>
>
>
> >
> > By the way, the HW controller states and FW programming register
> will be reset by CRT reset line.
> > And another part HW controller states will be reset by engine
> reset line.
>
> Thanks. Can we include that in the commit message for the device tree
> change?
>
Got it. I will add this and re-send the patches.
Thanks for your suggestion.
> >
> > Thanks,
> >
> > By Tommy
> >
> > > -----Original Message-----
> > > From: Joel Stanley <joel@jms.id.au>
> > > Sent: Monday, February 28, 2022 5:51 PM
> > > To: Tommy Huang <tommy_huang@aspeedtech.com>
> > > Cc: David Airlie <airlied@linux.ie>; Daniel Vetter
> > > <daniel@ffwll.ch>; Rob Herring <robh+dt@kernel.org>; Andrew Jeffery
> > > <andrew@aj.id.au>; linux-aspeed <linux-aspeed@lists.ozlabs.org>;
> > > open list:DRM DRIVERS <dri-devel@lists.freedesktop.org>; devicetree
> > > <devicetree@vger.kernel.org>; Linux ARM
> > > <linux-arm-kernel@lists.infradead.org>; Linux Kernel Mailing List
> > > <linux-kernel@vger.kernel.org>; BMC-SW <BMC-SW@aspeedtech.com>
> > > Subject: Re: [PATCH v5 5/7] drm/aspeed: Add reset and clock for
> > > AST2600
> > >
> > > On Wed, 8 Dec 2021 at 01:34, Tommy Haung
> > > <tommy_huang@aspeedtech.com> wrote:
> > > >
> > > > From: tommy-huang <tommy_huang@aspeedtech.com>
> > > >
> > > > Add more reset and clock select code for AST2600.
> > > > The gfx_flags parameter was added for chip caps idenified.
> > >
> > > Can you tell me a bit more about the two reset lines:
> > >
> > > What is the CRT reset line controlling?
> > >
> > > What does the engine reset line control?
> > >
> > > Can we use devm_reset_control_array_get() to get whichever are
> > > specified in the device tree, so we don't need to have different
> > > logic for the 2600 and earlier chips?
> > >
> > >
> > >
> > > >
> > > > Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
> > > > ---
> > > > drivers/gpu/drm/aspeed/aspeed_gfx.h | 16 +++++++-
> > > > drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 16 ++++++++
> > > > drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 50
> > > ++++++++++++++++++++++--
> > > > 3 files changed, 77 insertions(+), 5 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > > b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > > index 4e6a442c3886..2c733225d3c7 100644
> > > > --- a/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx.h
> > > > @@ -8,7 +8,8 @@ struct aspeed_gfx {
> > > > struct drm_device drm;
> > > > void __iomem *base;
> > > > struct clk *clk;
> > > > - struct reset_control *rst;
> > > > + struct reset_control *rst_crt;
> > > > + struct reset_control *rst_engine;
> > > > struct regmap *scu;
> > > >
> > > > u32 dac_reg;
> > > > @@ -16,6 +17,7 @@ struct aspeed_gfx {
> > > > u32 vga_scratch_reg;
> > > > u32 throd_val;
> > > > u32 scan_line_max;
> > > > + u32 flags;
> > > >
> > > > struct drm_simple_display_pipe pipe;
> > > > struct drm_connector connector;
> > > > @@ -106,3 +108,15 @@ int aspeed_gfx_create_output(struct
> > > > drm_device *drm);
> > > > /* CRT_THROD */
> > > > #define CRT_THROD_LOW(x) (x)
> > > > #define CRT_THROD_HIGH(x) ((x) << 8)
> > > > +
> > > > +/* SCU control */
> > > > +#define SCU_G6_CLK_COURCE 0x300
> > > > +
> > > > +/* GFX FLAGS */
> > > > +#define RESET_MASK BIT(0)
> > > > +#define RESET_G6 BIT(0)
> > > > +#define CLK_MASK BIT(4)
> > > > +#define CLK_G6 BIT(4)
> > > > +
> > > > +#define G6_CLK_MASK (BIT(8) | BIT(9) | BIT(10))
> > > > +#define G6_USB_40_CLK BIT(9)
> > > > diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > > b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > > index 827e62c1daba..e0975ecda92d 100644
> > > > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c
> > > > @@ -77,6 +77,18 @@ static void
> > > > aspeed_gfx_disable_controller(struct
> > > aspeed_gfx *priv)
> > > > regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0);
> > > > }
> > > >
> > > > +static void aspeed_gfx_set_clk(struct aspeed_gfx *priv) {
> > > > + switch (priv->flags & CLK_MASK) {
> > > > + case CLK_G6:
> > > > + regmap_update_bits(priv->scu,
> SCU_G6_CLK_COURCE,
> > > G6_CLK_MASK, 0x0);
> > > > + regmap_update_bits(priv->scu,
> SCU_G6_CLK_COURCE,
> > > G6_CLK_MASK, G6_USB_40_CLK);
> > > > + break;
> > > > + default:
> > > > + break;
> > > > + }
> > > > +}
> > > > +
> > > > static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv)
> {
> > > > struct drm_display_mode *m =
> > > > &priv->pipe.crtc.state->adjusted_mode;
> > > > @@ -87,6 +99,8 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct
> > > aspeed_gfx *priv)
> > > > if (err)
> > > > return;
> > > >
> > > > + aspeed_gfx_set_clk(priv);
> > > > +
> > > > #if 0
> > > > /* TODO: we have only been able to test with the 40MHz USB
> > > clock. The
> > > > * clock is fixed, so we cannot adjust it here. */ @@
> > > > -193,6
> > > > +207,7 @@ static void aspeed_gfx_pipe_update(struct
> > > > drm_simple_display_pipe *pipe, static int
> > > > aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe) {
> > > > struct aspeed_gfx *priv = drm_pipe_to_aspeed_gfx(pipe);
> > > > +
> > > > u32 reg = readl(priv->base + CRT_CTRL1);
> > > >
> > > > /* Clear pending VBLANK IRQ */ @@ -207,6 +222,7 @@ static
> > > > int aspeed_gfx_enable_vblank(struct drm_simple_display_pipe *pipe)
> > > > static void aspeed_gfx_disable_vblank(struct
> > > > drm_simple_display_pipe *pipe) {
> > > > struct aspeed_gfx *priv = drm_pipe_to_aspeed_gfx(pipe);
> > > > +
> > > > u32 reg = readl(priv->base + CRT_CTRL1);
> > > >
> > > > reg &= ~CRT_CTRL_VERTICAL_INTR_EN; diff --git
> > > > a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > > > b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > > > index d10246b1d1c2..59a0de92650f 100644
> > > > --- a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > > > +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
> > > > @@ -64,6 +64,7 @@ struct aspeed_gfx_config {
> > > > u32 vga_scratch_reg; /* VGA scratch register in SCU */
> > > > u32 throd_val; /* Default Threshold Seting */
> > > > u32 scan_line_max; /* Max memory size of one scan
> line */
> > > > + u32 gfx_flags; /* Flags for gfx chip caps */
> > > > };
> > > >
> > > > static const struct aspeed_gfx_config ast2400_config = { @@ -72,6
> > > > +73,7 @@ static const struct aspeed_gfx_config ast2400_config = {
> > > > .vga_scratch_reg = 0x50,
> > > > .throd_val = CRT_THROD_LOW(0x1e) |
> CRT_THROD_HIGH(0x12),
> > > > .scan_line_max = 64,
> > > > + .gfx_flags = 0,
> > > > };
> > > >
> > > > static const struct aspeed_gfx_config ast2500_config = { @@ -80,6
> > > > +82,7 @@ static const struct aspeed_gfx_config ast2500_config = {
> > > > .vga_scratch_reg = 0x50,
> > > > .throd_val = CRT_THROD_LOW(0x24) |
> CRT_THROD_HIGH(0x3c),
> > > > .scan_line_max = 128,
> > > > + .gfx_flags = 0,
> > > > };
> > > >
> > > > static const struct aspeed_gfx_config ast2600_config = { @@ -88,6
> > > > +91,7 @@ static const struct aspeed_gfx_config ast2600_config = {
> > > > .vga_scratch_reg = 0x50,
> > > > .throd_val = CRT_THROD_LOW(0x50) |
> CRT_THROD_HIGH(0x70),
> > > > .scan_line_max = 128,
> > > > + .gfx_flags = RESET_G6 | CLK_G6,
> > > > };
> > > >
> > > > static const struct of_device_id aspeed_gfx_match[] = { @@ -138,6
> > > > +142,44 @@ static irqreturn_t aspeed_gfx_irq_handler(int irq, void
> > > > +*data)
> > > > return IRQ_NONE;
> > > > }
> > > >
> > > > +static int aspeed_gfx_reset(struct drm_device *drm) {
> > > > + struct platform_device *pdev = to_platform_device(drm->dev);
> > > > + struct aspeed_gfx *priv = to_aspeed_gfx(drm);
> > > > +
> > > > + switch (priv->flags & RESET_MASK) {
> > > > + case RESET_G6:
> > > > + priv->rst_crt = devm_reset_control_get(&pdev->dev,
> > > "crt");
> > > > + if (IS_ERR(priv->rst_crt)) {
> > > > + dev_err(&pdev->dev,
> > > > + "missing or invalid crt reset
> > > > + controller
> > > device tree entry");
> > > > + return PTR_ERR(priv->rst_crt);
> > > > + }
> > > > + reset_control_deassert(priv->rst_crt);
> > > > +
> > > > + priv->rst_engine =
> > > > + devm_reset_control_get(&pdev->dev,
> > > "engine");
> > > > + if (IS_ERR(priv->rst_engine)) {
> > > > + dev_err(&pdev->dev,
> > > > + "missing or invalid engine reset
> > > controller device tree entry");
> > > > + return PTR_ERR(priv->rst_engine);
> > > > + }
> > > > + reset_control_deassert(priv->rst_engine);
> > > > + break;
> > > > +
> > > > + default:
> > > > + priv->rst_crt =
> > > devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > > > + if (IS_ERR(priv->rst_crt)) {
> > > > + dev_err(&pdev->dev,
> > > > + "missing or invalid reset
> > > > + controller
> > > device tree entry");
> > > > + return PTR_ERR(priv->rst_crt);
> > > > + }
> > > > + reset_control_deassert(priv->rst_crt);
> > > > + break;
> > > > + }
> > > > +
> > > > + return 0;
> > > > +}
> > > > +
> > > > static int aspeed_gfx_load(struct drm_device *drm) {
> > > > struct platform_device *pdev =
> > > > to_platform_device(drm->dev); @@ -163,6 +205,7 @@ static int
> aspeed_gfx_load(struct drm_device *drm)
> > > > priv->vga_scratch_reg = config->vga_scratch_reg;
> > > > priv->throd_val = config->throd_val;
> > > > priv->scan_line_max = config->scan_line_max;
> > > > + priv->flags = config->gfx_flags;
> > > >
> > > > priv->scu = syscon_regmap_lookup_by_phandle(np, "syscon");
> > > > if (IS_ERR(priv->scu)) {
> > > > @@ -186,13 +229,12 @@ static int aspeed_gfx_load(struct drm_device
> > > *drm)
> > > > return ret;
> > > > }
> > > >
> > > > - priv->rst = devm_reset_control_get_exclusive(&pdev->dev,
> NULL);
> > > > - if (IS_ERR(priv->rst)) {
> > > > + ret = aspeed_gfx_reset(drm);
> > > > + if (ret) {
> > > > dev_err(&pdev->dev,
> > > > "missing or invalid reset controller
> > > > device tree
> > > entry");
> > > > - return PTR_ERR(priv->rst);
> > > > + return ret;
> > > > }
> > > > - reset_control_deassert(priv->rst);
> > > >
> > > > priv->clk = devm_clk_get(drm->dev, NULL);
> > > > if (IS_ERR(priv->clk)) {
> > > > --
> > > > 2.17.1
> > > >
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 6/7] arm:boot:dts:aspeed-g6 Add more gfx reset control
2021-12-08 1:33 [PATCH v5 0/7] Add Aspeed AST2600 soc display support Tommy Haung
` (4 preceding siblings ...)
2021-12-08 1:33 ` [PATCH v5 5/7] drm/aspeed: Add reset and clock for AST2600 Tommy Haung
@ 2021-12-08 1:33 ` Tommy Haung
2021-12-08 1:33 ` [PATCH v5 7/7] dt-bindings:ast2600-clock Add CRT reset define Tommy Haung
2022-02-28 9:53 ` [PATCH v5 0/7] Add Aspeed AST2600 soc display support Joel Stanley
7 siblings, 0 replies; 15+ messages in thread
From: Tommy Haung @ 2021-12-08 1:33 UTC (permalink / raw)
To: joel, airlied, daniel, robh+dt, andrew, linux-aspeed, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
Cc: BMC-SW, tommy-huang
From: tommy-huang <tommy_huang@aspeedtech.com>
Add more gfx reset control for ast2600.
Signed-off-by: tommy-huang <tommy_huang@aspeedtech.com>
---
arch/arm/boot/dts/aspeed-g6.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index e38c3742761b..b92b24609660 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -356,7 +356,9 @@
reg = <0x1e6e6000 0x1000>;
reg-io-width = <4>;
clocks = <&syscon ASPEED_CLK_GATE_D1CLK>;
- resets = <&syscon ASPEED_RESET_GRAPHICS>;
+ resets = <&syscon ASPEED_RESET_CRT>,
+ <&syscon ASPEED_RESET_GRAPHICS>;
+ reset-names = "crt", "engine";
syscon = <&syscon>;
status = "disabled";
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v5 7/7] dt-bindings:ast2600-clock Add CRT reset define
2021-12-08 1:33 [PATCH v5 0/7] Add Aspeed AST2600 soc display support Tommy Haung
` (5 preceding siblings ...)
2021-12-08 1:33 ` [PATCH v5 6/7] arm:boot:dts:aspeed-g6 Add more gfx reset control Tommy Haung
@ 2021-12-08 1:33 ` Tommy Haung
2021-12-10 21:18 ` Rob Herring
2022-02-28 9:53 ` [PATCH v5 0/7] Add Aspeed AST2600 soc display support Joel Stanley
7 siblings, 1 reply; 15+ messages in thread
From: Tommy Haung @ 2021-12-08 1:33 UTC (permalink / raw)
To: joel, airlied, daniel, robh+dt, andrew, linux-aspeed, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
Cc: BMC-SW
Add new CRT reset define for ast2600.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
---
include/dt-bindings/clock/ast2600-clock.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h
index 62b9520a00fd..f8bee338a00f 100644
--- a/include/dt-bindings/clock/ast2600-clock.h
+++ b/include/dt-bindings/clock/ast2600-clock.h
@@ -110,6 +110,7 @@
#define ASPEED_RESET_PCIE_DEV_OEN 20
#define ASPEED_RESET_PCIE_RC_O 19
#define ASPEED_RESET_PCIE_RC_OEN 18
+#define ASPEED_RESET_CRT 13
#define ASPEED_RESET_PCI_DP 5
#define ASPEED_RESET_AHB 1
#define ASPEED_RESET_SDRAM 0
--
2.17.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH v5 7/7] dt-bindings:ast2600-clock Add CRT reset define
2021-12-08 1:33 ` [PATCH v5 7/7] dt-bindings:ast2600-clock Add CRT reset define Tommy Haung
@ 2021-12-10 21:18 ` Rob Herring
0 siblings, 0 replies; 15+ messages in thread
From: Rob Herring @ 2021-12-10 21:18 UTC (permalink / raw)
To: Tommy Haung
Cc: linux-arm-kernel, robh+dt, airlied, linux-aspeed, devicetree,
joel, linux-kernel, BMC-SW, dri-devel, daniel, andrew
On Wed, 08 Dec 2021 09:33:37 +0800, Tommy Haung wrote:
> Add new CRT reset define for ast2600.
>
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com>
> ---
> include/dt-bindings/clock/ast2600-clock.h | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 0/7] Add Aspeed AST2600 soc display support
2021-12-08 1:33 [PATCH v5 0/7] Add Aspeed AST2600 soc display support Tommy Haung
` (6 preceding siblings ...)
2021-12-08 1:33 ` [PATCH v5 7/7] dt-bindings:ast2600-clock Add CRT reset define Tommy Haung
@ 2022-02-28 9:53 ` Joel Stanley
7 siblings, 0 replies; 15+ messages in thread
From: Joel Stanley @ 2022-02-28 9:53 UTC (permalink / raw)
To: Tommy Haung
Cc: David Airlie, Daniel Vetter, Rob Herring, Andrew Jeffery,
linux-aspeed, open list:DRM DRIVERS, devicetree, Linux ARM,
Linux Kernel Mailing List, BMC-SW
Hi Tommy,
On Wed, 8 Dec 2021 at 01:34, Tommy Haung <tommy_huang@aspeedtech.com> wrote:
>
> v5:
> Add lost reset define.
>
> v4:
> Add necessary reset control for ast2600.
> Add chip caps for futher use.
> These code are test on AST2500 and AST2600 by below steps.
>
> 1. Add below config to turn VT and LOGO on.
>
> CONFIG_TTY=y
> CONFIG_VT=y
> CONFIG_CONSOLE_TRANSLATIONS=y
> CONFIG_VT_CONSOLE=y
> CONFIG_VT_CONSOLE_SLEEP=y
> CONFIG_HW_CONSOLE=y
> CONFIG_VT_HW_CONSOLE_BINDING=y
> CONFIG_UNIX98_PTYS=y
> CONFIG_LDISC_AUTOLOAD=y
> CONFIG_DEVMEM=y
> CONFIG_DUMMY_CONSOLE=y
> CONFIG_FRAMEBUFFER_CONSOLE=y
> CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
> CONFIG_LOGO=y
> CONFIG_LOGO_LINUX_CLUT224=y
>
> 2. The Linux logo will be shown on the screen, when the BMC boot in Linux.
Sorry for the long delay. I have tested your patches on an ast2600a3
evb and they worked. I have some questions about the reset lines that
I couldn't answer by reading the datasheet, so once they are cleared
up we can go ahead with merging your patches.
When you re-send, you will need to fix your git configuration so your
name appears correctly:
git config --global user.name "Tommy Haung"
And then for each patch, do this to fix up the authorship and the s-o-b line:
git commit --amend --reset-author -s
Cheers,
Joel
>
> v3:
> Refine the patch for clear separate purpose.
> Skip to send devicetree patch
>
> v2:
> Remove some unnecessary patch.
> Refine for reviwer request.
>
> v1:
> First add patch.
>
> Joel Stanley (2):
> ARM: dts: aspeed: Add GFX node to AST2600
> ARM: dts: aspeed: ast2600-evb: Enable GFX device
>
> Tommy Haung (1):
> dt-bindings:ast2600-clock Add CRT reset define
>
> tommy-huang (4):
> drm/aspeed: Update INTR_STS handling
> drm/aspeed: Add AST2600 chip support
> drm/aspeed: Add reset and clock for AST2600
> arm:boot:dts:aspeed-g6 Add more gfx reset control
>
> arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 +++++++
> arch/arm/boot/dts/aspeed-g6.dtsi | 13 +++++
> drivers/gpu/drm/aspeed/aspeed_gfx.h | 17 +++++-
> drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 16 ++++++
> drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 65 +++++++++++++++++++++--
> include/dt-bindings/clock/ast2600-clock.h | 1 +
> 6 files changed, 124 insertions(+), 6 deletions(-)
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread