[PATCH 0/3] pinctrl: sunxi: Remove non-existent reset line references

[PATCH 0/3] pinctrl: sunxi: Remove non-existent reset line references

[Samuel Holland]

I assume these properties came from a lack of documentation, and the
very reasonable assumption that where there's a clock gate bit in the
CCU, there's a reset bit. But the pin controllers are special and don't
have a module reset line. The only way to reset the pin controller is to
reset the whole VDD_SYS power domain.

This series is preparation for converting the PRCM MFD and legacy clock
drivers to a CCU clock/reset driver like all of the other Allwinner
SoCs. I don't plan to add reset lines that don't actually exist to the
new CCU driver. So we might as well get rid of the references now.
Technically this breaks devicetree compatibility, since the old drivers
expect the reset. But the CCU conversion will be a compatibility break
anyway, so it's a bit of a moot point.


Samuel Holland (3):
  pinctrl: sunxi: Remove reset controller consumers
  ARM: dts: sunxi: Drop resets from r_pio nodes
  dt-bindings: pinctrl: sunxi: Disallow the resets property

 .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml  |  3 ---
 arch/arm/boot/dts/sun6i-a31.dtsi              |  1 -
 arch/arm/boot/dts/sun8i-a23-a33.dtsi          |  1 -
 arch/arm/boot/dts/sun9i-a80.dtsi              |  1 -
 drivers/pinctrl/sunxi/Kconfig                 |  3 ---
 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c  |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c   |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c   | 22 +---------------
 drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c   | 25 +------------------
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c  |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c   |  1 -
 12 files changed, 2 insertions(+), 59 deletions(-)

-- 
2.35.1

[PATCH 1/3] pinctrl: sunxi: Remove reset controller consumers

[Samuel Holland]

None of the sunxi pin controllers have a module reset line. All of the
SoC documentation, where available, agrees. The bits that would be used
for the PIO reset (i.e. matching the order of the clock gate bits) are
always reserved, both in the CCU and in the PRCM. And experiments on
several SoCs, including the A33, confirm that those reserved bits indeed
have no effect.

Let's remove this superfluous code and dependency, and also remove the
include statement that was copied to the other r_pio drivers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 drivers/pinctrl/sunxi/Kconfig                 |  3 ---
 drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c  |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c   |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c   | 22 +---------------
 drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c   | 25 +------------------
 drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c  |  1 -
 drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c   |  1 -
 8 files changed, 2 insertions(+), 53 deletions(-)

diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
index 33751a6a0757..7a7bcdc198a3 100644
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -29,7 +29,6 @@ config PINCTRL_SUN6I_A31
 config PINCTRL_SUN6I_A31_R
 	bool "Support for the Allwinner A31 R-PIO"
 	default MACH_SUN6I
-	depends on RESET_CONTROLLER
 	select PINCTRL_SUNXI
 
 config PINCTRL_SUN8I_A23
@@ -55,7 +54,6 @@ config PINCTRL_SUN8I_A83T_R
 config PINCTRL_SUN8I_A23_R
 	bool "Support for the Allwinner A23 and A33 R-PIO"
 	default MACH_SUN8I
-	depends on RESET_CONTROLLER
 	select PINCTRL_SUNXI
 
 config PINCTRL_SUN8I_H3
@@ -81,7 +79,6 @@ config PINCTRL_SUN9I_A80
 config PINCTRL_SUN9I_A80_R
 	bool "Support for the Allwinner A80 R-PIO"
 	default MACH_SUN9I
-	depends on RESET_CONTROLLER
 	select PINCTRL_SUNXI
 
 config PINCTRL_SUN50I_A64
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
index e69c8dae121a..ef261eccda56 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c
@@ -24,7 +24,6 @@
 #include <linux/of_device.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/platform_device.h>
-#include <linux/reset.h>
 
 #include "pinctrl-sunxi.h"
 
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
index c7d90c44e87a..487a76c45f7e 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c
@@ -16,7 +16,6 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/pinctrl/pinctrl.h>
-#include <linux/reset.h>
 
 #include "pinctrl-sunxi.h"
 
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
index 8e4f10ab96ce..c39ea46046c2 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c
@@ -12,7 +12,6 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/pinctrl/pinctrl.h>
-#include <linux/reset.h>
 
 #include "pinctrl-sunxi.h"
 
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
index a00246d3dd49..2486cdf345e1 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
@@ -17,7 +17,6 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/pinctrl/pinctrl.h>
-#include <linux/reset.h>
 
 #include "pinctrl-sunxi.h"
 
@@ -111,26 +110,7 @@ static const struct sunxi_pinctrl_desc sun6i_a31_r_pinctrl_data = {
 
 static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
 {
-	struct reset_control *rstc;
-	int ret;
-
-	rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
-	if (IS_ERR(rstc)) {
-		dev_err(&pdev->dev, "Reset controller missing\n");
-		return PTR_ERR(rstc);
-	}
-
-	ret = reset_control_deassert(rstc);
-	if (ret)
-		return ret;
-
-	ret = sunxi_pinctrl_init(pdev,
-				 &sun6i_a31_r_pinctrl_data);
-
-	if (ret)
-		reset_control_assert(rstc);
-
-	return ret;
+	return sunxi_pinctrl_init(pdev, &sun6i_a31_r_pinctrl_data);
 }
 
 static const struct of_device_id sun6i_a31_r_pinctrl_match[] = {
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
index 9e5b61449999..4fae12c905b7 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
@@ -20,7 +20,6 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/pinctrl/pinctrl.h>
-#include <linux/reset.h>
 
 #include "pinctrl-sunxi.h"
 
@@ -98,29 +97,7 @@ static const struct sunxi_pinctrl_desc sun8i_a23_r_pinctrl_data = {
 
 static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)
 {
-	struct reset_control *rstc;
-	int ret;
-
-	rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
-	if (IS_ERR(rstc)) {
-		ret = PTR_ERR(rstc);
-		if (ret == -EPROBE_DEFER)
-			return ret;
-		dev_err(&pdev->dev, "Reset controller missing err=%d\n", ret);
-		return ret;
-	}
-
-	ret = reset_control_deassert(rstc);
-	if (ret)
-		return ret;
-
-	ret = sunxi_pinctrl_init(pdev,
-				 &sun8i_a23_r_pinctrl_data);
-
-	if (ret)
-		reset_control_assert(rstc);
-
-	return ret;
+	return sunxi_pinctrl_init(pdev, &sun8i_a23_r_pinctrl_data);
 }
 
 static const struct of_device_id sun8i_a23_r_pinctrl_match[] = {
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
index 6531cf67958e..0cb6c1a970c9 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c
@@ -27,7 +27,6 @@
 #include <linux/of_device.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/platform_device.h>
-#include <linux/reset.h>
 
 #include "pinctrl-sunxi.h"
 
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
index a191a65217ac..f11cb5bba0f7 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c
@@ -14,7 +14,6 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/pinctrl/pinctrl.h>
-#include <linux/reset.h>
 
 #include "pinctrl-sunxi.h"
 
-- 
2.35.1

[PATCH 2/3] ARM: dts: sunxi: Drop resets from r_pio nodes

[Samuel Holland]

None of the sunxi pin controllers have a module reset line. This is
confirmed by documentation (A80) as well as experimentation (A33).

Let's remove the inaccurate properties.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/arm/boot/dts/sun6i-a31.dtsi     | 1 -
 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 1 -
 arch/arm/boot/dts/sun9i-a80.dtsi     | 1 -
 3 files changed, 3 deletions(-)

diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 715d74854449..df3330073687 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -1387,7 +1387,6 @@ r_pio: pinctrl@1f02c00 {
 				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
 			clock-names = "apb", "hosc", "losc";
-			resets = <&apb0_rst 0>;
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index 4461d5098b20..8d3dd9e2b54e 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -812,7 +812,6 @@ r_pio: pinctrl@1f02c00 {
 			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
 			clock-names = "apb", "hosc", "losc";
-			resets = <&apb0_rst 0>;
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
index ce4fa6706d06..7d3f3300f431 100644
--- a/arch/arm/boot/dts/sun9i-a80.dtsi
+++ b/arch/arm/boot/dts/sun9i-a80.dtsi
@@ -1218,7 +1218,6 @@ r_pio: pinctrl@8002c00 {
 				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>;
 			clock-names = "apb", "hosc", "losc";
-			resets = <&apbs_rst 0>;
 			gpio-controller;
 			interrupt-controller;
 			#interrupt-cells = <3>;
-- 
2.35.1

[PATCH 3/3] dt-bindings: pinctrl: sunxi: Disallow the resets property

[Samuel Holland]

None of the sunxi pin controllers have a module reset line. This is
confirmed by documentation (A80) as well as experimentation (A33).

Since the property is not applicable to any variant of the hardware,
let's remove it from the binding.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml          | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
index bfce850c2035..fa0c2df04675 100644
--- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml
@@ -80,9 +80,6 @@ properties:
       - const: hosc
       - const: losc
 
-  resets:
-    maxItems: 1
-
   gpio-controller: true
   interrupt-controller: true
   gpio-line-names: true
-- 
2.35.1

Re: [PATCH 0/3] pinctrl: sunxi: Remove non-existent reset line references

[Jernej Škrabec]

Dne torek, 31. maj 2022 ob 07:36:20 CEST je Samuel Holland napisal(a):
> I assume these properties came from a lack of documentation, and the
> very reasonable assumption that where there's a clock gate bit in the
> CCU, there's a reset bit. But the pin controllers are special and don't
> have a module reset line. The only way to reset the pin controller is to
> reset the whole VDD_SYS power domain.
> 
> This series is preparation for converting the PRCM MFD and legacy clock
> drivers to a CCU clock/reset driver like all of the other Allwinner
> SoCs. I don't plan to add reset lines that don't actually exist to the
> new CCU driver. So we might as well get rid of the references now.
> Technically this breaks devicetree compatibility, since the old drivers
> expect the reset. But the CCU conversion will be a compatibility break
> anyway, so it's a bit of a moot point.

If I understand correclty, this would cause only DT forward compatibility 
issue, which happens now and then anyway. Kernel would still be compatible 
with older DTs, it would just ignore that reset, right?

Best regards,
Jernej

> 
> 
> Samuel Holland (3):
>   pinctrl: sunxi: Remove reset controller consumers
>   ARM: dts: sunxi: Drop resets from r_pio nodes
>   dt-bindings: pinctrl: sunxi: Disallow the resets property
> 
>  .../pinctrl/allwinner,sun4i-a10-pinctrl.yaml  |  3 ---
>  arch/arm/boot/dts/sun6i-a31.dtsi              |  1 -
>  arch/arm/boot/dts/sun8i-a23-a33.dtsi          |  1 -
>  arch/arm/boot/dts/sun9i-a80.dtsi              |  1 -
>  drivers/pinctrl/sunxi/Kconfig                 |  3 ---
>  drivers/pinctrl/sunxi/pinctrl-sun50i-a64-r.c  |  1 -
>  drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c   |  1 -
>  drivers/pinctrl/sunxi/pinctrl-sun50i-h616-r.c |  1 -
>  drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c   | 22 +---------------
>  drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c   | 25 +------------------
>  drivers/pinctrl/sunxi/pinctrl-sun8i-a83t-r.c  |  1 -
>  drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c   |  1 -
>  12 files changed, 2 insertions(+), 59 deletions(-)
> 
> -- 
> 2.35.1
> 
> 

Re: [PATCH 0/3] pinctrl: sunxi: Remove non-existent reset line references

[Samuel Holland]

Hi Jernej,

On 5/31/22 10:22 AM, Jernej Škrabec wrote:
> Dne torek, 31. maj 2022 ob 07:36:20 CEST je Samuel Holland napisal(a):
>> I assume these properties came from a lack of documentation, and the
>> very reasonable assumption that where there's a clock gate bit in the
>> CCU, there's a reset bit. But the pin controllers are special and don't
>> have a module reset line. The only way to reset the pin controller is to
>> reset the whole VDD_SYS power domain.
>>
>> This series is preparation for converting the PRCM MFD and legacy clock
>> drivers to a CCU clock/reset driver like all of the other Allwinner
>> SoCs. I don't plan to add reset lines that don't actually exist to the
>> new CCU driver. So we might as well get rid of the references now.
>> Technically this breaks devicetree compatibility, since the old drivers
>> expect the reset. But the CCU conversion will be a compatibility break
>> anyway, so it's a bit of a moot point.
> 
> If I understand correclty, this would cause only DT forward compatibility 
> issue, which happens now and then anyway. Kernel would still be compatible 
> with older DTs, it would just ignore that reset, right?

Right, this only prevents older kernels from working with newer devicetrees. I
brought it up because I'm generally trying to minimize how much we do that.

Regards,
Samuel

Re: Re: [PATCH 0/3] pinctrl: sunxi: Remove non-existent reset line references

[Jernej Škrabec]

Dne sreda, 01. junij 2022 ob 06:42:34 CEST je Samuel Holland napisal(a):
> Hi Jernej,
> 
> On 5/31/22 10:22 AM, Jernej Škrabec wrote:
> > Dne torek, 31. maj 2022 ob 07:36:20 CEST je Samuel Holland napisal(a):
> >> I assume these properties came from a lack of documentation, and the
> >> very reasonable assumption that where there's a clock gate bit in the
> >> CCU, there's a reset bit. But the pin controllers are special and don't
> >> have a module reset line. The only way to reset the pin controller is to
> >> reset the whole VDD_SYS power domain.
> >>
> >> This series is preparation for converting the PRCM MFD and legacy clock
> >> drivers to a CCU clock/reset driver like all of the other Allwinner
> >> SoCs. I don't plan to add reset lines that don't actually exist to the
> >> new CCU driver. So we might as well get rid of the references now.
> >> Technically this breaks devicetree compatibility, since the old drivers
> >> expect the reset. But the CCU conversion will be a compatibility break
> >> anyway, so it's a bit of a moot point.
> > 
> > If I understand correclty, this would cause only DT forward compatibility 
> > issue, which happens now and then anyway. Kernel would still be compatible 
> > with older DTs, it would just ignore that reset, right?
> 
> Right, this only prevents older kernels from working with newer devicetrees. 
I
> brought it up because I'm generally trying to minimize how much we do that.

All good then, this series is:
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>

Best regards,
Jernej

Re: [PATCH 3/3] dt-bindings: pinctrl: sunxi: Disallow the resets property

[Rob Herring]

On Tue, 31 May 2022 00:36:23 -0500, Samuel Holland wrote:
> None of the sunxi pin controllers have a module reset line. This is
> confirmed by documentation (A80) as well as experimentation (A33).
> 
> Since the property is not applicable to any variant of the hardware,
> let's remove it from the binding.
> 
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
> 
>  .../bindings/pinctrl/allwinner,sun4i-a10-pinctrl.yaml          | 3 ---
>  1 file changed, 3 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 0/3] pinctrl: sunxi: Remove non-existent reset line references

[Linus Walleij]

On Tue, May 31, 2022 at 7:36 AM Samuel Holland <samuel@sholland.org> wrote:

> I assume these properties came from a lack of documentation, and the
> very reasonable assumption that where there's a clock gate bit in the
> CCU, there's a reset bit. But the pin controllers are special and don't
> have a module reset line. The only way to reset the pin controller is to
> reset the whole VDD_SYS power domain.
>
> This series is preparation for converting the PRCM MFD and legacy clock
> drivers to a CCU clock/reset driver like all of the other Allwinner
> SoCs. I don't plan to add reset lines that don't actually exist to the
> new CCU driver. So we might as well get rid of the references now.
> Technically this breaks devicetree compatibility, since the old drivers
> expect the reset. But the CCU conversion will be a compatibility break
> anyway, so it's a bit of a moot point.
>
>
> Samuel Holland (3):
>   pinctrl: sunxi: Remove reset controller consumers
>   ARM: dts: sunxi: Drop resets from r_pio nodes
>   dt-bindings: pinctrl: sunxi: Disallow the resets property

Patches applied for v5.20!

Yours,
Linus Walleij