[PATCH] arm64: dts: sdm845-mtp: Reserve reserved gpios

[PATCH] arm64: dts: sdm845-mtp: Reserve reserved gpios

[Bjorn Andersson]

With the introduction of commit 3edfb7bd76bd ("gpiolib: Show correct
direction from the beginning") the gpiolib will attempt to read the
direction of all pins, which triggers a read from protected register
regions.

The pins 0 through 3 and 81 through 84 are protected, so mark these as
reserved.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---

Given that mainline has not yet booted on the SDM845 MTP or MSM8998 MTP
(which seems to be the affected platform), I think it's better to pick this
change than to rework the offending commit.

 arch/arm64/boot/dts/qcom/sdm845-mtp.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
index eedfaf8922e2..d667eee4e6d0 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-mtp.dts
@@ -352,6 +352,10 @@
 	status = "okay";
 };
 
+&tlmm {
+	gpio-reserved-ranges = <0 4>, <81 4>;
+};
+
 &uart9 {
 	status = "okay";
 };
-- 
2.18.0

Re: [PATCH] arm64: dts: sdm845-mtp: Reserve reserved gpios

[Stephen Boyd]

Quoting Bjorn Andersson (2018-11-02 14:45:32)
> With the introduction of commit 3edfb7bd76bd ("gpiolib: Show correct
> direction from the beginning") the gpiolib will attempt to read the
> direction of all pins, which triggers a read from protected register
> regions.
> 
> The pins 0 through 3 and 81 through 84 are protected, so mark these as
> reserved.
> 
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---

Reviewed-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH] arm64: dts: sdm845-mtp: Reserve reserved gpios

[Linus Walleij]

On Fri, Nov 2, 2018 at 10:42 PM Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:

> With the introduction of commit 3edfb7bd76bd ("gpiolib: Show correct
> direction from the beginning") the gpiolib will attempt to read the
> direction of all pins, which triggers a read from protected register
> regions.
>
> The pins 0 through 3 and 81 through 84 are protected, so mark these as
> reserved.
>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>

Thanks for fixing this up so elegantly.

Yours,
Linus Walleij