From: Doug Anderson <dianders@chromium.org>
To: Sibi Sankar <sibis@codeaurora.org>
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>,
Andy Gross <agross@kernel.org>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>, LKML <linux-kernel@vger.kernel.org>,
Evan Green <evgreen@chromium.org>,
Rob Herring <robh+dt@kernel.org>,
Stephen Boyd <swboyd@chromium.org>,
Matthias Kaehlcke <mka@chromium.org>
Subject: Re: [PATCH v2 1/2] arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite
Date: Tue, 24 Nov 2020 09:55:34 -0800 [thread overview]
Message-ID: <CAD=FV=XpX3zq-rzMNE8f7mZEWBqD1aOrCekzwzugdG7ANW9j-A@mail.gmail.com> (raw)
In-Reply-To: <1606198876-3515-1-git-send-email-sibis@codeaurora.org>
Hi,
On Mon, Nov 23, 2020 at 10:21 PM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> Tweak the DDR/L3 bandwidth votes on the lite variant of the SC7180 SoC
> since the gold cores only support frequencies upto 2.1 GHz.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
>
> V2:
> * Updated the lite ddr/l3 cpufreq map to have better power numbers with
> similar perf.
>
> arch/arm64/boot/dts/qcom/sc7180-lite.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
I certainly don't love the way that this works but it does match the
way folks have agreed that DDR bandwidth votes should work. Long term
it feels like we should re-think how this is working, but it seems
fine for now.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
prev parent reply other threads:[~2020-11-24 17:56 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-24 6:21 [PATCH v2 1/2] arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite Sibi Sankar
2020-11-24 6:21 ` [PATCH v2 2/2] arm64: dts: qcom: sc7180: Add DDR/L3 votes for the pro variant Sibi Sankar
2020-11-24 17:55 ` Doug Anderson
2020-11-24 17:55 ` Doug Anderson [this message]
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