* [PATCH v5 1/7] interconnect: qcom: Allow icc node to be used across icc providers
2020-02-27 10:56 [PATCH v5 0/7] Add OSM L3 Interconnect Provider Sibi Sankar
@ 2020-02-27 10:56 ` Sibi Sankar
2020-02-29 0:21 ` Evan Green
2020-02-27 10:56 ` [PATCH v5 2/7] dt-bindings: interconnect: Add OSM L3 DT bindings Sibi Sankar
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Sibi Sankar @ 2020-02-27 10:56 UTC (permalink / raw)
To: robh+dt, georgi.djakov, evgreen
Cc: bjorn.andersson, agross, linux-kernel, devicetree, linux-arm-msm,
mark.rutland, saravanak, viresh.kumar, okukatla, Sibi Sankar
Move the icc node ids to a common header, this will allow for
referencing/linking of icc nodes to multiple icc providers on
SDM845 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/interconnect/qcom/sdm845.c | 134 +--------------------------
drivers/interconnect/qcom/sdm845.h | 140 +++++++++++++++++++++++++++++
2 files changed, 141 insertions(+), 133 deletions(-)
create mode 100644 drivers/interconnect/qcom/sdm845.h
diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c
index ab968afeee594..b013b80caa452 100644
--- a/drivers/interconnect/qcom/sdm845.c
+++ b/drivers/interconnect/qcom/sdm845.c
@@ -13,139 +13,7 @@
#include "bcm-voter.h"
#include "icc-rpmh.h"
-
-enum {
- SDM845_MASTER_A1NOC_CFG = 1,
- SDM845_MASTER_BLSP_1,
- SDM845_MASTER_TSIF,
- SDM845_MASTER_SDCC_2,
- SDM845_MASTER_SDCC_4,
- SDM845_MASTER_UFS_CARD,
- SDM845_MASTER_UFS_MEM,
- SDM845_MASTER_PCIE_0,
- SDM845_MASTER_A2NOC_CFG,
- SDM845_MASTER_QDSS_BAM,
- SDM845_MASTER_BLSP_2,
- SDM845_MASTER_CNOC_A2NOC,
- SDM845_MASTER_CRYPTO,
- SDM845_MASTER_IPA,
- SDM845_MASTER_PCIE_1,
- SDM845_MASTER_QDSS_ETR,
- SDM845_MASTER_USB3_0,
- SDM845_MASTER_USB3_1,
- SDM845_MASTER_CAMNOC_HF0_UNCOMP,
- SDM845_MASTER_CAMNOC_HF1_UNCOMP,
- SDM845_MASTER_CAMNOC_SF_UNCOMP,
- SDM845_MASTER_SPDM,
- SDM845_MASTER_TIC,
- SDM845_MASTER_SNOC_CNOC,
- SDM845_MASTER_QDSS_DAP,
- SDM845_MASTER_CNOC_DC_NOC,
- SDM845_MASTER_APPSS_PROC,
- SDM845_MASTER_GNOC_CFG,
- SDM845_MASTER_LLCC,
- SDM845_MASTER_TCU_0,
- SDM845_MASTER_MEM_NOC_CFG,
- SDM845_MASTER_GNOC_MEM_NOC,
- SDM845_MASTER_MNOC_HF_MEM_NOC,
- SDM845_MASTER_MNOC_SF_MEM_NOC,
- SDM845_MASTER_SNOC_GC_MEM_NOC,
- SDM845_MASTER_SNOC_SF_MEM_NOC,
- SDM845_MASTER_GFX3D,
- SDM845_MASTER_CNOC_MNOC_CFG,
- SDM845_MASTER_CAMNOC_HF0,
- SDM845_MASTER_CAMNOC_HF1,
- SDM845_MASTER_CAMNOC_SF,
- SDM845_MASTER_MDP0,
- SDM845_MASTER_MDP1,
- SDM845_MASTER_ROTATOR,
- SDM845_MASTER_VIDEO_P0,
- SDM845_MASTER_VIDEO_P1,
- SDM845_MASTER_VIDEO_PROC,
- SDM845_MASTER_SNOC_CFG,
- SDM845_MASTER_A1NOC_SNOC,
- SDM845_MASTER_A2NOC_SNOC,
- SDM845_MASTER_GNOC_SNOC,
- SDM845_MASTER_MEM_NOC_SNOC,
- SDM845_MASTER_ANOC_PCIE_SNOC,
- SDM845_MASTER_PIMEM,
- SDM845_MASTER_GIC,
- SDM845_SLAVE_A1NOC_SNOC,
- SDM845_SLAVE_SERVICE_A1NOC,
- SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC,
- SDM845_SLAVE_A2NOC_SNOC,
- SDM845_SLAVE_ANOC_PCIE_SNOC,
- SDM845_SLAVE_SERVICE_A2NOC,
- SDM845_SLAVE_CAMNOC_UNCOMP,
- SDM845_SLAVE_A1NOC_CFG,
- SDM845_SLAVE_A2NOC_CFG,
- SDM845_SLAVE_AOP,
- SDM845_SLAVE_AOSS,
- SDM845_SLAVE_CAMERA_CFG,
- SDM845_SLAVE_CLK_CTL,
- SDM845_SLAVE_CDSP_CFG,
- SDM845_SLAVE_RBCPR_CX_CFG,
- SDM845_SLAVE_CRYPTO_0_CFG,
- SDM845_SLAVE_DCC_CFG,
- SDM845_SLAVE_CNOC_DDRSS,
- SDM845_SLAVE_DISPLAY_CFG,
- SDM845_SLAVE_GLM,
- SDM845_SLAVE_GFX3D_CFG,
- SDM845_SLAVE_IMEM_CFG,
- SDM845_SLAVE_IPA_CFG,
- SDM845_SLAVE_CNOC_MNOC_CFG,
- SDM845_SLAVE_PCIE_0_CFG,
- SDM845_SLAVE_PCIE_1_CFG,
- SDM845_SLAVE_PDM,
- SDM845_SLAVE_SOUTH_PHY_CFG,
- SDM845_SLAVE_PIMEM_CFG,
- SDM845_SLAVE_PRNG,
- SDM845_SLAVE_QDSS_CFG,
- SDM845_SLAVE_BLSP_2,
- SDM845_SLAVE_BLSP_1,
- SDM845_SLAVE_SDCC_2,
- SDM845_SLAVE_SDCC_4,
- SDM845_SLAVE_SNOC_CFG,
- SDM845_SLAVE_SPDM_WRAPPER,
- SDM845_SLAVE_SPSS_CFG,
- SDM845_SLAVE_TCSR,
- SDM845_SLAVE_TLMM_NORTH,
- SDM845_SLAVE_TLMM_SOUTH,
- SDM845_SLAVE_TSIF,
- SDM845_SLAVE_UFS_CARD_CFG,
- SDM845_SLAVE_UFS_MEM_CFG,
- SDM845_SLAVE_USB3_0,
- SDM845_SLAVE_USB3_1,
- SDM845_SLAVE_VENUS_CFG,
- SDM845_SLAVE_VSENSE_CTRL_CFG,
- SDM845_SLAVE_CNOC_A2NOC,
- SDM845_SLAVE_SERVICE_CNOC,
- SDM845_SLAVE_LLCC_CFG,
- SDM845_SLAVE_MEM_NOC_CFG,
- SDM845_SLAVE_GNOC_SNOC,
- SDM845_SLAVE_GNOC_MEM_NOC,
- SDM845_SLAVE_SERVICE_GNOC,
- SDM845_SLAVE_EBI1,
- SDM845_SLAVE_MSS_PROC_MS_MPU_CFG,
- SDM845_SLAVE_MEM_NOC_GNOC,
- SDM845_SLAVE_LLCC,
- SDM845_SLAVE_MEM_NOC_SNOC,
- SDM845_SLAVE_SERVICE_MEM_NOC,
- SDM845_SLAVE_MNOC_SF_MEM_NOC,
- SDM845_SLAVE_MNOC_HF_MEM_NOC,
- SDM845_SLAVE_SERVICE_MNOC,
- SDM845_SLAVE_APPSS,
- SDM845_SLAVE_SNOC_CNOC,
- SDM845_SLAVE_SNOC_MEM_NOC_GC,
- SDM845_SLAVE_SNOC_MEM_NOC_SF,
- SDM845_SLAVE_IMEM,
- SDM845_SLAVE_PCIE_0,
- SDM845_SLAVE_PCIE_1,
- SDM845_SLAVE_PIMEM,
- SDM845_SLAVE_SERVICE_SNOC,
- SDM845_SLAVE_QDSS_STM,
- SDM845_SLAVE_TCU
-};
+#include "sdm845.h"
DEFINE_QNODE(qhm_a1noc_cfg, SDM845_MASTER_A1NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A1NOC);
DEFINE_QNODE(qhm_qup1, SDM845_MASTER_BLSP_1, 1, 4, SDM845_SLAVE_A1NOC_SNOC);
diff --git a/drivers/interconnect/qcom/sdm845.h b/drivers/interconnect/qcom/sdm845.h
new file mode 100644
index 0000000000000..bc7e425ce9852
--- /dev/null
+++ b/drivers/interconnect/qcom/sdm845.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
+#define __DRIVERS_INTERCONNECT_QCOM_SDM845_H__
+
+#define SDM845_MASTER_A1NOC_CFG 1
+#define SDM845_MASTER_BLSP_1 2
+#define SDM845_MASTER_TSIF 3
+#define SDM845_MASTER_SDCC_2 4
+#define SDM845_MASTER_SDCC_4 5
+#define SDM845_MASTER_UFS_CARD 6
+#define SDM845_MASTER_UFS_MEM 7
+#define SDM845_MASTER_PCIE_0 8
+#define SDM845_MASTER_A2NOC_CFG 9
+#define SDM845_MASTER_QDSS_BAM 10
+#define SDM845_MASTER_BLSP_2 11
+#define SDM845_MASTER_CNOC_A2NOC 12
+#define SDM845_MASTER_CRYPTO 13
+#define SDM845_MASTER_IPA 14
+#define SDM845_MASTER_PCIE_1 15
+#define SDM845_MASTER_QDSS_ETR 16
+#define SDM845_MASTER_USB3_0 17
+#define SDM845_MASTER_USB3_1 18
+#define SDM845_MASTER_CAMNOC_HF0_UNCOMP 19
+#define SDM845_MASTER_CAMNOC_HF1_UNCOMP 20
+#define SDM845_MASTER_CAMNOC_SF_UNCOMP 21
+#define SDM845_MASTER_SPDM 22
+#define SDM845_MASTER_TIC 23
+#define SDM845_MASTER_SNOC_CNOC 24
+#define SDM845_MASTER_QDSS_DAP 25
+#define SDM845_MASTER_CNOC_DC_NOC 26
+#define SDM845_MASTER_APPSS_PROC 27
+#define SDM845_MASTER_GNOC_CFG 28
+#define SDM845_MASTER_LLCC 29
+#define SDM845_MASTER_TCU_0 30
+#define SDM845_MASTER_MEM_NOC_CFG 31
+#define SDM845_MASTER_GNOC_MEM_NOC 32
+#define SDM845_MASTER_MNOC_HF_MEM_NOC 33
+#define SDM845_MASTER_MNOC_SF_MEM_NOC 34
+#define SDM845_MASTER_SNOC_GC_MEM_NOC 35
+#define SDM845_MASTER_SNOC_SF_MEM_NOC 36
+#define SDM845_MASTER_GFX3D 37
+#define SDM845_MASTER_CNOC_MNOC_CFG 38
+#define SDM845_MASTER_CAMNOC_HF0 39
+#define SDM845_MASTER_CAMNOC_HF1 40
+#define SDM845_MASTER_CAMNOC_SF 41
+#define SDM845_MASTER_MDP0 42
+#define SDM845_MASTER_MDP1 43
+#define SDM845_MASTER_ROTATOR 44
+#define SDM845_MASTER_VIDEO_P0 45
+#define SDM845_MASTER_VIDEO_P1 46
+#define SDM845_MASTER_VIDEO_PROC 47
+#define SDM845_MASTER_SNOC_CFG 48
+#define SDM845_MASTER_A1NOC_SNOC 49
+#define SDM845_MASTER_A2NOC_SNOC 50
+#define SDM845_MASTER_GNOC_SNOC 51
+#define SDM845_MASTER_MEM_NOC_SNOC 52
+#define SDM845_MASTER_ANOC_PCIE_SNOC 53
+#define SDM845_MASTER_PIMEM 54
+#define SDM845_MASTER_GIC 55
+#define SDM845_SLAVE_A1NOC_SNOC 56
+#define SDM845_SLAVE_SERVICE_A1NOC 57
+#define SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC 58
+#define SDM845_SLAVE_A2NOC_SNOC 59
+#define SDM845_SLAVE_ANOC_PCIE_SNOC 60
+#define SDM845_SLAVE_SERVICE_A2NOC 61
+#define SDM845_SLAVE_CAMNOC_UNCOMP 62
+#define SDM845_SLAVE_A1NOC_CFG 63
+#define SDM845_SLAVE_A2NOC_CFG 64
+#define SDM845_SLAVE_AOP 65
+#define SDM845_SLAVE_AOSS 66
+#define SDM845_SLAVE_CAMERA_CFG 67
+#define SDM845_SLAVE_CLK_CTL 68
+#define SDM845_SLAVE_CDSP_CFG 69
+#define SDM845_SLAVE_RBCPR_CX_CFG 70
+#define SDM845_SLAVE_CRYPTO_0_CFG 71
+#define SDM845_SLAVE_DCC_CFG 72
+#define SDM845_SLAVE_CNOC_DDRSS 73
+#define SDM845_SLAVE_DISPLAY_CFG 74
+#define SDM845_SLAVE_GLM 75
+#define SDM845_SLAVE_GFX3D_CFG 76
+#define SDM845_SLAVE_IMEM_CFG 77
+#define SDM845_SLAVE_IPA_CFG 78
+#define SDM845_SLAVE_CNOC_MNOC_CFG 79
+#define SDM845_SLAVE_PCIE_0_CFG 80
+#define SDM845_SLAVE_PCIE_1_CFG 81
+#define SDM845_SLAVE_PDM 82
+#define SDM845_SLAVE_SOUTH_PHY_CFG 83
+#define SDM845_SLAVE_PIMEM_CFG 84
+#define SDM845_SLAVE_PRNG 85
+#define SDM845_SLAVE_QDSS_CFG 86
+#define SDM845_SLAVE_BLSP_2 87
+#define SDM845_SLAVE_BLSP_1 88
+#define SDM845_SLAVE_SDCC_2 89
+#define SDM845_SLAVE_SDCC_4 90
+#define SDM845_SLAVE_SNOC_CFG 91
+#define SDM845_SLAVE_SPDM_WRAPPER 92
+#define SDM845_SLAVE_SPSS_CFG 93
+#define SDM845_SLAVE_TCSR 94
+#define SDM845_SLAVE_TLMM_NORTH 95
+#define SDM845_SLAVE_TLMM_SOUTH 96
+#define SDM845_SLAVE_TSIF 97
+#define SDM845_SLAVE_UFS_CARD_CFG 98
+#define SDM845_SLAVE_UFS_MEM_CFG 99
+#define SDM845_SLAVE_USB3_0 100
+#define SDM845_SLAVE_USB3_1 101
+#define SDM845_SLAVE_VENUS_CFG 102
+#define SDM845_SLAVE_VSENSE_CTRL_CFG 103
+#define SDM845_SLAVE_CNOC_A2NOC 104
+#define SDM845_SLAVE_SERVICE_CNOC 105
+#define SDM845_SLAVE_LLCC_CFG 106
+#define SDM845_SLAVE_MEM_NOC_CFG 107
+#define SDM845_SLAVE_GNOC_SNOC 108
+#define SDM845_SLAVE_GNOC_MEM_NOC 109
+#define SDM845_SLAVE_SERVICE_GNOC 110
+#define SDM845_SLAVE_EBI1 111
+#define SDM845_SLAVE_MSS_PROC_MS_MPU_CFG 112
+#define SDM845_SLAVE_MEM_NOC_GNOC 113
+#define SDM845_SLAVE_LLCC 114
+#define SDM845_SLAVE_MEM_NOC_SNOC 115
+#define SDM845_SLAVE_SERVICE_MEM_NOC 116
+#define SDM845_SLAVE_MNOC_SF_MEM_NOC 117
+#define SDM845_SLAVE_MNOC_HF_MEM_NOC 118
+#define SDM845_SLAVE_SERVICE_MNOC 119
+#define SDM845_SLAVE_APPSS 120
+#define SDM845_SLAVE_SNOC_CNOC 121
+#define SDM845_SLAVE_SNOC_MEM_NOC_GC 122
+#define SDM845_SLAVE_SNOC_MEM_NOC_SF 123
+#define SDM845_SLAVE_IMEM 124
+#define SDM845_SLAVE_PCIE_0 125
+#define SDM845_SLAVE_PCIE_1 126
+#define SDM845_SLAVE_PIMEM 127
+#define SDM845_SLAVE_SERVICE_SNOC 128
+#define SDM845_SLAVE_QDSS_STM 129
+#define SDM845_SLAVE_TCU 130
+
+#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v5 1/7] interconnect: qcom: Allow icc node to be used across icc providers
2020-02-27 10:56 ` [PATCH v5 1/7] interconnect: qcom: Allow icc node to be used across icc providers Sibi Sankar
@ 2020-02-29 0:21 ` Evan Green
0 siblings, 0 replies; 15+ messages in thread
From: Evan Green @ 2020-02-29 0:21 UTC (permalink / raw)
To: Sibi Sankar
Cc: Rob Herring, Georgi Djakov, Bjorn Andersson, Andy Gross, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-msm, Mark Rutland, Saravana Kannan, Viresh Kumar,
Odelu Kukatla
On Thu, Feb 27, 2020 at 2:57 AM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> Move the icc node ids to a common header, this will allow for
> referencing/linking of icc nodes to multiple icc providers on
> SDM845 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 2/7] dt-bindings: interconnect: Add OSM L3 DT bindings
2020-02-27 10:56 [PATCH v5 0/7] Add OSM L3 Interconnect Provider Sibi Sankar
2020-02-27 10:56 ` [PATCH v5 1/7] interconnect: qcom: Allow icc node to be used across icc providers Sibi Sankar
@ 2020-02-27 10:56 ` Sibi Sankar
2020-02-27 10:56 ` [PATCH v5 3/7] interconnect: qcom: Add OSM L3 interconnect provider support Sibi Sankar
` (4 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Sibi Sankar @ 2020-02-27 10:56 UTC (permalink / raw)
To: robh+dt, georgi.djakov, evgreen
Cc: bjorn.andersson, agross, linux-kernel, devicetree, linux-arm-msm,
mark.rutland, saravanak, viresh.kumar, okukatla, Sibi Sankar,
Rob Herring
Add bindings for Operating State Manager (OSM) L3 interconnect provider
on SDM845 SoCs.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
.../bindings/interconnect/qcom,osm-l3.yaml | 61 +++++++++++++++++++
.../dt-bindings/interconnect/qcom,osm-l3.h | 12 ++++
2 files changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
create mode 100644 include/dt-bindings/interconnect/qcom,osm-l3.h
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
new file mode 100644
index 0000000000000..b4d46a1e92573
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
+
+maintainers:
+ - Sibi Sankar <sibis@codeaurora.org>
+
+description:
+ L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
+ The OSM L3 interconnect provider aggregates the L3 bandwidth requests
+ from CPU/GPU and relays it to the OSM.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sdm845-osm-l3
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: xo clock
+ - description: alternate clock
+
+ clock-names:
+ items:
+ - const: xo
+ - const: alternate
+
+ '#interconnect-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#interconnect-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #define GPLL0 165
+ #define RPMH_CXO_CLK 0
+
+ osm_l3: interconnect@17d41000 {
+ compatible = "qcom,sdm845-osm-l3";
+ reg = <0x17d41000 0x1400>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h
new file mode 100644
index 0000000000000..54858ff7674d7
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,osm-l3.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
+
+#define MASTER_OSM_L3_APPS 0
+#define SLAVE_OSM_L3 1
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 3/7] interconnect: qcom: Add OSM L3 interconnect provider support
2020-02-27 10:56 [PATCH v5 0/7] Add OSM L3 Interconnect Provider Sibi Sankar
2020-02-27 10:56 ` [PATCH v5 1/7] interconnect: qcom: Allow icc node to be used across icc providers Sibi Sankar
2020-02-27 10:56 ` [PATCH v5 2/7] dt-bindings: interconnect: Add OSM L3 DT bindings Sibi Sankar
@ 2020-02-27 10:56 ` Sibi Sankar
2020-02-29 0:10 ` Evan Green
2020-02-27 10:56 ` [PATCH v5 4/7] dt-bindings: interconnect: Add OSM L3 DT binding on SC7180 Sibi Sankar
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Sibi Sankar @ 2020-02-27 10:56 UTC (permalink / raw)
To: robh+dt, georgi.djakov, evgreen
Cc: bjorn.andersson, agross, linux-kernel, devicetree, linux-arm-msm,
mark.rutland, saravanak, viresh.kumar, okukatla, Sibi Sankar
On some Qualcomm SoCs, Operating State Manager (OSM) controls the
resources of scaling L3 caches. Add a driver to handle bandwidth
requests to OSM L3 from CPU on SDM845 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/interconnect/qcom/Kconfig | 7 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/osm-l3.c | 261 +++++++++++++++++++++++++++++
drivers/interconnect/qcom/sdm845.h | 2 +
4 files changed, 272 insertions(+)
create mode 100644 drivers/interconnect/qcom/osm-l3.c
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index c8e74b0038c49..35402376427f4 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -28,6 +28,13 @@ config INTERCONNECT_QCOM_MSM8974
This is a driver for the Qualcomm Network-on-Chip on msm8974-based
platforms.
+config INTERCONNECT_QCOM_OSM_L3
+ tristate "Qualcomm OSM L3 interconnect driver"
+ depends on INTERCONNECT_QCOM || COMPILE_TEST
+ help
+ Say y here to support the Operating State Manager (OSM) interconnect
+ driver which controls the scaling of L3 caches on Qualcomm SoCs.
+
config INTERCONNECT_QCOM_QCS404
tristate "Qualcomm QCS404 interconnect driver"
depends on INTERCONNECT_QCOM
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index 532555812ef61..3a047fe6e45a2 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -3,6 +3,7 @@
icc-bcm-voter-objs := bcm-voter.o
qnoc-msm8916-objs := msm8916.o
qnoc-msm8974-objs := msm8974.o
+icc-osm-l3-objs := osm-l3.o
qnoc-qcs404-objs := qcs404.o
icc-rpmh-obj := icc-rpmh.o
qnoc-sc7180-objs := sc7180.o
@@ -12,6 +13,7 @@ icc-smd-rpm-objs := smd-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
+obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
new file mode 100644
index 0000000000000..bbf8133195972
--- /dev/null
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/interconnect-provider.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
+
+#include "sdm845.h"
+
+#define LUT_MAX_ENTRIES 40U
+#define LUT_SRC GENMASK(31, 30)
+#define LUT_L_VAL GENMASK(7, 0)
+#define LUT_ROW_SIZE 32
+#define CLK_HW_DIV 2
+
+/* Register offsets */
+#define REG_ENABLE 0x0
+#define REG_FREQ_LUT 0x110
+#define REG_PERF_STATE 0x920
+
+#define OSM_L3_MAX_LINKS 1
+
+#define to_qcom_provider(_provider) \
+ container_of(_provider, struct qcom_osm_l3_icc_provider, provider)
+
+struct qcom_osm_l3_icc_provider {
+ void __iomem *base;
+ unsigned int max_state;
+ unsigned long lut_tables[LUT_MAX_ENTRIES];
+ struct icc_provider provider;
+};
+
+/**
+ * struct qcom_icc_node - Qualcomm specific interconnect nodes
+ * @name: the node name used in debugfs
+ * @links: an array of nodes where we can go next while traversing
+ * @id: a unique node identifier
+ * @num_links: the total number of @links
+ * @buswidth: width of the interconnect between a node and the bus
+ */
+struct qcom_icc_node {
+ const char *name;
+ u16 links[OSM_L3_MAX_LINKS];
+ u16 id;
+ u16 num_links;
+ u16 buswidth;
+};
+
+struct qcom_icc_desc {
+ struct qcom_icc_node **nodes;
+ size_t num_nodes;
+};
+
+#define DEFINE_QNODE(_name, _id, _buswidth, ...) \
+ static struct qcom_icc_node _name = { \
+ .name = #_name, \
+ .id = _id, \
+ .buswidth = _buswidth, \
+ .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
+ .links = { __VA_ARGS__ }, \
+ }
+
+DEFINE_QNODE(sdm845_osm_apps_l3, SDM845_MASTER_OSM_L3_APPS, 16, SDM845_SLAVE_OSM_L3);
+DEFINE_QNODE(sdm845_osm_l3, SDM845_SLAVE_OSM_L3, 16);
+
+static struct qcom_icc_node *sdm845_osm_l3_nodes[] = {
+ [MASTER_OSM_L3_APPS] = &sdm845_osm_apps_l3,
+ [SLAVE_OSM_L3] = &sdm845_osm_l3,
+};
+
+const static struct qcom_icc_desc sdm845_icc_osm_l3 = {
+ .nodes = sdm845_osm_l3_nodes,
+ .num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
+};
+
+static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+ struct qcom_osm_l3_icc_provider *qp;
+ struct icc_provider *provider;
+ struct qcom_icc_node *qn;
+ struct icc_node *n;
+ unsigned int index;
+ u32 agg_peak = 0;
+ u32 agg_avg = 0;
+ u64 rate;
+
+ qn = src->data;
+ provider = src->provider;
+ qp = to_qcom_provider(provider);
+
+ list_for_each_entry(n, &provider->nodes, node_list)
+ provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
+ &agg_avg, &agg_peak);
+
+ rate = max(agg_avg, agg_peak);
+ rate = icc_units_to_bps(rate);
+ do_div(rate, qn->buswidth);
+
+ for (index = 0; index < qp->max_state - 1; index++) {
+ if (qp->lut_tables[index] >= rate)
+ break;
+ }
+
+ writel_relaxed(index, qp->base + REG_PERF_STATE);
+
+ return 0;
+}
+
+static int qcom_osm_l3_remove(struct platform_device *pdev)
+{
+ struct qcom_osm_l3_icc_provider *qp = platform_get_drvdata(pdev);
+
+ icc_nodes_remove(&qp->provider);
+ return icc_provider_del(&qp->provider);
+}
+
+static int qcom_osm_l3_probe(struct platform_device *pdev)
+{
+ u32 info, src, lval, i, prev_freq = 0, freq;
+ static unsigned long hw_rate, xo_rate;
+ struct qcom_osm_l3_icc_provider *qp;
+ const struct qcom_icc_desc *desc;
+ struct icc_onecell_data *data;
+ struct icc_provider *provider;
+ struct qcom_icc_node **qnodes;
+ struct icc_node *node;
+ size_t num_nodes;
+ struct clk *clk;
+ int ret;
+
+ clk = clk_get(&pdev->dev, "xo");
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ xo_rate = clk_get_rate(clk);
+ clk_put(clk);
+
+ clk = clk_get(&pdev->dev, "alternate");
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ hw_rate = clk_get_rate(clk) / CLK_HW_DIV;
+ clk_put(clk);
+
+ qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
+ if (!qp)
+ return -ENOMEM;
+
+ qp->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(qp->base))
+ return PTR_ERR(qp->base);
+
+ /* HW should be in enabled state to proceed */
+ if (!(readl_relaxed(qp->base + REG_ENABLE) & 0x1)) {
+ dev_err(&pdev->dev, "error hardware not enabled\n");
+ return -ENODEV;
+ }
+
+ for (i = 0; i < LUT_MAX_ENTRIES; i++) {
+ info = readl_relaxed(qp->base + REG_FREQ_LUT +
+ i * LUT_ROW_SIZE);
+ src = FIELD_GET(LUT_SRC, info);
+ lval = FIELD_GET(LUT_L_VAL, info);
+ if (src)
+ freq = xo_rate * lval;
+ else
+ freq = hw_rate;
+
+ /* Two of the same frequencies signify end of table */
+ if (i > 0 && prev_freq == freq)
+ break;
+
+ dev_dbg(&pdev->dev, "index=%d freq=%d\n", i, freq);
+
+ qp->lut_tables[i] = freq;
+ prev_freq = freq;
+ }
+ qp->max_state = i;
+
+ desc = device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ qnodes = desc->nodes;
+ num_nodes = desc->num_nodes;
+
+ data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ provider = &qp->provider;
+ provider->dev = &pdev->dev;
+ provider->set = qcom_icc_set;
+ provider->aggregate = icc_std_aggregate;
+ provider->xlate = of_icc_xlate_onecell;
+ INIT_LIST_HEAD(&provider->nodes);
+ provider->data = data;
+
+ ret = icc_provider_add(provider);
+ if (ret) {
+ dev_err(&pdev->dev, "error adding interconnect provider\n");
+ return ret;
+ }
+
+ for (i = 0; i < num_nodes; i++) {
+ size_t j;
+
+ node = icc_node_create(qnodes[i]->id);
+ if (IS_ERR(node)) {
+ ret = PTR_ERR(node);
+ goto err;
+ }
+
+ node->name = qnodes[i]->name;
+ node->data = qnodes[i];
+ icc_node_add(node, provider);
+
+ for (j = 0; j < qnodes[i]->num_links; j++)
+ icc_link_create(node, qnodes[i]->links[j]);
+
+ data->nodes[i] = node;
+ }
+ data->num_nodes = num_nodes;
+
+ platform_set_drvdata(pdev, qp);
+
+ return 0;
+err:
+ icc_nodes_remove(provider);
+ icc_provider_del(provider);
+
+ return ret;
+}
+
+static const struct of_device_id osm_l3_of_match[] = {
+ { .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
+ { }
+};
+MODULE_DEVICE_TABLE(of, osm_l3_of_match);
+
+static struct platform_driver osm_l3_driver = {
+ .probe = qcom_osm_l3_probe,
+ .remove = qcom_osm_l3_remove,
+ .driver = {
+ .name = "osm-l3",
+ .of_match_table = osm_l3_of_match,
+ },
+};
+module_platform_driver(osm_l3_driver);
+
+MODULE_DESCRIPTION("Qualcomm OSM L3 interconnect driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/interconnect/qcom/sdm845.h b/drivers/interconnect/qcom/sdm845.h
index bc7e425ce9852..776e9c2acb278 100644
--- a/drivers/interconnect/qcom/sdm845.h
+++ b/drivers/interconnect/qcom/sdm845.h
@@ -136,5 +136,7 @@
#define SDM845_SLAVE_SERVICE_SNOC 128
#define SDM845_SLAVE_QDSS_STM 129
#define SDM845_SLAVE_TCU 130
+#define SDM845_MASTER_OSM_L3_APPS 131
+#define SDM845_SLAVE_OSM_L3 132
#endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v5 3/7] interconnect: qcom: Add OSM L3 interconnect provider support
2020-02-27 10:56 ` [PATCH v5 3/7] interconnect: qcom: Add OSM L3 interconnect provider support Sibi Sankar
@ 2020-02-29 0:10 ` Evan Green
0 siblings, 0 replies; 15+ messages in thread
From: Evan Green @ 2020-02-29 0:10 UTC (permalink / raw)
To: Sibi Sankar
Cc: Rob Herring, Georgi Djakov, Bjorn Andersson, Andy Gross, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-msm, Mark Rutland, Saravana Kannan, Viresh Kumar,
Odelu Kukatla
On Thu, Feb 27, 2020 at 2:57 AM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> On some Qualcomm SoCs, Operating State Manager (OSM) controls the
> resources of scaling L3 caches. Add a driver to handle bandwidth
> requests to OSM L3 from CPU on SDM845 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 4/7] dt-bindings: interconnect: Add OSM L3 DT binding on SC7180
2020-02-27 10:56 [PATCH v5 0/7] Add OSM L3 Interconnect Provider Sibi Sankar
` (2 preceding siblings ...)
2020-02-27 10:56 ` [PATCH v5 3/7] interconnect: qcom: Add OSM L3 interconnect provider support Sibi Sankar
@ 2020-02-27 10:56 ` Sibi Sankar
2020-02-27 10:56 ` [PATCH v5 5/7] interconnect: qcom: Add OSM L3 support " Sibi Sankar
` (2 subsequent siblings)
6 siblings, 0 replies; 15+ messages in thread
From: Sibi Sankar @ 2020-02-27 10:56 UTC (permalink / raw)
To: robh+dt, georgi.djakov, evgreen
Cc: bjorn.andersson, agross, linux-kernel, devicetree, linux-arm-msm,
mark.rutland, saravanak, viresh.kumar, okukatla, Sibi Sankar,
Rob Herring
Add OSM L3 interconnect provider binding on SC7180 SoCs.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index b4d46a1e92573..91f70c9067d12 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -17,6 +17,7 @@ description:
properties:
compatible:
enum:
+ - qcom,sc7180-osm-l3
- qcom,sdm845-osm-l3
reg:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v5 5/7] interconnect: qcom: Add OSM L3 support on SC7180
2020-02-27 10:56 [PATCH v5 0/7] Add OSM L3 Interconnect Provider Sibi Sankar
` (3 preceding siblings ...)
2020-02-27 10:56 ` [PATCH v5 4/7] dt-bindings: interconnect: Add OSM L3 DT binding on SC7180 Sibi Sankar
@ 2020-02-27 10:56 ` Sibi Sankar
2020-02-29 0:10 ` Evan Green
2020-02-27 10:56 ` [PATCH v5 6/7] arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider Sibi Sankar
2020-02-27 10:56 ` [PATCH v5 7/7] arm64: dts: qcom: sc7180: " Sibi Sankar
6 siblings, 1 reply; 15+ messages in thread
From: Sibi Sankar @ 2020-02-27 10:56 UTC (permalink / raw)
To: robh+dt, georgi.djakov, evgreen
Cc: bjorn.andersson, agross, linux-kernel, devicetree, linux-arm-msm,
mark.rutland, saravanak, viresh.kumar, okukatla, Sibi Sankar
Add Operating State Manager (OSM) L3 interconnect provider support on
SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/interconnect/qcom/osm-l3.c | 15 +++++++++++++++
drivers/interconnect/qcom/sc7180.h | 2 ++
2 files changed, 17 insertions(+)
diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index bbf8133195972..a03c6d6833dfc 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -14,6 +14,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
+#include "sc7180.h"
#include "sdm845.h"
#define LUT_MAX_ENTRIES 40U
@@ -82,6 +83,19 @@ const static struct qcom_icc_desc sdm845_icc_osm_l3 = {
.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
};
+DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
+DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
+
+static struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
+ [MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
+ [SLAVE_OSM_L3] = &sc7180_osm_l3,
+};
+
+const static struct qcom_icc_desc sc7180_icc_osm_l3 = {
+ .nodes = sc7180_osm_l3_nodes,
+ .num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
+};
+
static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
{
struct qcom_osm_l3_icc_provider *qp;
@@ -242,6 +256,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
}
static const struct of_device_id osm_l3_of_match[] = {
+ { .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
{ }
};
diff --git a/drivers/interconnect/qcom/sc7180.h b/drivers/interconnect/qcom/sc7180.h
index c2d8388bb8809..c6212a10c2f61 100644
--- a/drivers/interconnect/qcom/sc7180.h
+++ b/drivers/interconnect/qcom/sc7180.h
@@ -145,5 +145,7 @@
#define SC7180_SLAVE_SERVICE_SNOC 134
#define SC7180_SLAVE_QDSS_STM 135
#define SC7180_SLAVE_TCU 136
+#define SC7180_MASTER_OSM_L3_APPS 137
+#define SC7180_SLAVE_OSM_L3 138
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v5 5/7] interconnect: qcom: Add OSM L3 support on SC7180
2020-02-27 10:56 ` [PATCH v5 5/7] interconnect: qcom: Add OSM L3 support " Sibi Sankar
@ 2020-02-29 0:10 ` Evan Green
0 siblings, 0 replies; 15+ messages in thread
From: Evan Green @ 2020-02-29 0:10 UTC (permalink / raw)
To: Sibi Sankar
Cc: Rob Herring, Georgi Djakov, Bjorn Andersson, Andy Gross, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-msm, Mark Rutland, Saravana Kannan, Viresh Kumar,
Odelu Kukatla
On Thu, Feb 27, 2020 at 2:57 AM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> Add Operating State Manager (OSM) L3 interconnect provider support on
> SC7180 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 6/7] arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider
2020-02-27 10:56 [PATCH v5 0/7] Add OSM L3 Interconnect Provider Sibi Sankar
` (4 preceding siblings ...)
2020-02-27 10:56 ` [PATCH v5 5/7] interconnect: qcom: Add OSM L3 support " Sibi Sankar
@ 2020-02-27 10:56 ` Sibi Sankar
2020-02-29 0:10 ` Evan Green
2020-03-04 16:32 ` Georgi Djakov
2020-02-27 10:56 ` [PATCH v5 7/7] arm64: dts: qcom: sc7180: " Sibi Sankar
6 siblings, 2 replies; 15+ messages in thread
From: Sibi Sankar @ 2020-02-27 10:56 UTC (permalink / raw)
To: robh+dt, georgi.djakov, evgreen
Cc: bjorn.andersson, agross, linux-kernel, devicetree, linux-arm-msm,
mark.rutland, saravanak, viresh.kumar, okukatla, Sibi Sankar
Add Operation State Manager (OSM) L3 interconnect provider on SDM845 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index ae7d6617d8b87..8105532f6fbde 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
@@ -3323,6 +3324,16 @@ frame@17d10000 {
};
};
+ osm_l3: interconnect@17d41000 {
+ compatible = "qcom,sdm845-osm-l3";
+ reg = <0 0x17d41000 0 0x1400>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@17d43000 {
compatible = "qcom,cpufreq-hw";
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v5 6/7] arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider
2020-02-27 10:56 ` [PATCH v5 6/7] arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider Sibi Sankar
@ 2020-02-29 0:10 ` Evan Green
2020-03-04 16:32 ` Georgi Djakov
1 sibling, 0 replies; 15+ messages in thread
From: Evan Green @ 2020-02-29 0:10 UTC (permalink / raw)
To: Sibi Sankar
Cc: Rob Herring, Georgi Djakov, Bjorn Andersson, Andy Gross, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-msm, Mark Rutland, Saravana Kannan, Viresh Kumar,
Odelu Kukatla
On Thu, Feb 27, 2020 at 2:57 AM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> Add Operation State Manager (OSM) L3 interconnect provider on SDM845 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 6/7] arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider
2020-02-27 10:56 ` [PATCH v5 6/7] arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider Sibi Sankar
2020-02-29 0:10 ` Evan Green
@ 2020-03-04 16:32 ` Georgi Djakov
1 sibling, 0 replies; 15+ messages in thread
From: Georgi Djakov @ 2020-03-04 16:32 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson
Cc: robh+dt, evgreen, agross, linux-kernel, devicetree,
linux-arm-msm, mark.rutland, saravanak, viresh.kumar, okukatla
On 2/27/20 12:56, Sibi Sankar wrote:
> Add Operation State Manager (OSM) L3 interconnect provider on SDM845 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
Thanks,
Georgi
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v5 7/7] arm64: dts: qcom: sc7180: Add OSM L3 interconnect provider
2020-02-27 10:56 [PATCH v5 0/7] Add OSM L3 Interconnect Provider Sibi Sankar
` (5 preceding siblings ...)
2020-02-27 10:56 ` [PATCH v5 6/7] arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider Sibi Sankar
@ 2020-02-27 10:56 ` Sibi Sankar
2020-02-29 0:10 ` Evan Green
2020-03-04 16:33 ` Georgi Djakov
6 siblings, 2 replies; 15+ messages in thread
From: Sibi Sankar @ 2020-02-27 10:56 UTC (permalink / raw)
To: robh+dt, georgi.djakov, evgreen
Cc: bjorn.andersson, agross, linux-kernel, devicetree, linux-arm-msm,
mark.rutland, saravanak, viresh.kumar, okukatla, Sibi Sankar
Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 3e28f340fa3e6..6997467608107 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,gcc-sc7180.h>
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
@@ -1578,6 +1579,16 @@ apps_bcm_voter: bcm_voter {
};
};
+ osm_l3: interconnect@18321000 {
+ compatible = "qcom,sc7180-osm-l3";
+ reg = <0 0x18321000 0 0x1400>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v5 7/7] arm64: dts: qcom: sc7180: Add OSM L3 interconnect provider
2020-02-27 10:56 ` [PATCH v5 7/7] arm64: dts: qcom: sc7180: " Sibi Sankar
@ 2020-02-29 0:10 ` Evan Green
2020-03-04 16:33 ` Georgi Djakov
1 sibling, 0 replies; 15+ messages in thread
From: Evan Green @ 2020-02-29 0:10 UTC (permalink / raw)
To: Sibi Sankar
Cc: Rob Herring, Georgi Djakov, Bjorn Andersson, Andy Gross, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-arm-msm, Mark Rutland, Saravana Kannan, Viresh Kumar,
Odelu Kukatla
On Thu, Feb 27, 2020 at 2:57 AM Sibi Sankar <sibis@codeaurora.org> wrote:
>
> Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v5 7/7] arm64: dts: qcom: sc7180: Add OSM L3 interconnect provider
2020-02-27 10:56 ` [PATCH v5 7/7] arm64: dts: qcom: sc7180: " Sibi Sankar
2020-02-29 0:10 ` Evan Green
@ 2020-03-04 16:33 ` Georgi Djakov
1 sibling, 0 replies; 15+ messages in thread
From: Georgi Djakov @ 2020-03-04 16:33 UTC (permalink / raw)
To: Sibi Sankar, bjorn.andersson
Cc: robh+dt, evgreen, agross, linux-kernel, devicetree,
linux-arm-msm, mark.rutland, saravanak, viresh.kumar, okukatla
On 2/27/20 12:56, Sibi Sankar wrote:
> Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
Thanks,
Georgi
^ permalink raw reply [flat|nested] 15+ messages in thread