* [PATCH 0/3] Add support for the Purism Librem5 devkit
@ 2019-03-11 23:46 Angus Ainslie (Purism)
2019-03-11 23:46 ` [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the " Angus Ainslie (Purism)
` (2 more replies)
0 siblings, 3 replies; 14+ messages in thread
From: Angus Ainslie (Purism) @ 2019-03-11 23:46 UTC (permalink / raw)
To: Mark Rutland
Cc: Rob Herring, Shawn Guo, Fabio Estevam, kernel, Lucas Stach,
abel.vesa, daniel.baluta, agx, linux-imx, devicetree,
linux-kernel, Angus Ainslie (Purism)
The Librem5 devkit is based on the imx8mq from NXP. This is a default config
and devicetree to boot the board to a command prompt.
Angus Ainslie (Purism) (3):
arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit
arm64: dts: fsl: Build the Librem5 devkit devicetree
arm64: librem5-devkit: Add defconfig for the Librem5 devkit
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx8mq-librem5-devkit.dts | 804 ++++++++++++++++++
arch/arm64/configs/librem5-devkit_defconfig | 534 ++++++++++++
3 files changed, 1339 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
create mode 100644 arch/arm64/configs/librem5-devkit_defconfig
--
2.17.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit
2019-03-11 23:46 [PATCH 0/3] Add support for the Purism Librem5 devkit Angus Ainslie (Purism)
@ 2019-03-11 23:46 ` Angus Ainslie (Purism)
2019-03-12 0:10 ` Fabio Estevam
` (2 more replies)
2019-03-11 23:46 ` [PATCH 2/3] arm64: dts: fsl: Build the Librem5 devkit devicetree Angus Ainslie (Purism)
2019-03-11 23:46 ` [PATCH 3/3] arm64: librem5-devkit: Add defconfig for the Librem5 devkit Angus Ainslie (Purism)
2 siblings, 3 replies; 14+ messages in thread
From: Angus Ainslie (Purism) @ 2019-03-11 23:46 UTC (permalink / raw)
To: Mark Rutland
Cc: Rob Herring, Shawn Guo, Fabio Estevam, kernel, Lucas Stach,
abel.vesa, daniel.baluta, agx, linux-imx, devicetree,
linux-kernel, Angus Ainslie (Purism)
This is the development kit for the Librem 5. The current level of support
yields a working console and is able to boot userspace from the network
or eMMC.
Additional subsystems that are active :
- Both USB ports
- SD card socket
- WWAN modem
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
.../dts/freescale/imx8mq-librem5-devkit.dts | 804 ++++++++++++++++++
1 file changed, 804 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
new file mode 100644
index 000000000000..da9221c4200c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
@@ -0,0 +1,804 @@
+/* SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright 2018-2019 Purism SPC
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+#include "dt-bindings/usb/pd.h"
+
+/ {
+ model = "Purism Librem 5 devkit 1.0";
+ compatible = "fsl,librem5-devkit", "fsl,imx8mq";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ reg_usdhc2_vmmc: regulator-vsd-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ reg_pwr_en: pwr_en {
+ compatible = "regulator-fixed";
+ regulator-name = "PWR_EN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ pmic_osc: pmic_osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic_osc";
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+ phy-supply = <®_pwr_en>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ at803x,led-act-blind-workaround;
+ at803x,eee-disabled;
+ power-supply = <®_pwr_en>;
+ };
+ };
+};
+
+&iomuxc {
+ imx8m-som {
+ pinctrl_nc: ncgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x00
+ MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_up: upgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x00
+ >;
+ };
+
+ pinctrl_csi1: csi1grp {
+ fsl,pins = <
+ /* CSI_nRST */
+ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x11
+ /* CSI_PWDN */
+ MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
+ /* CLK01 */
+ MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x19
+ >;
+ };
+
+ pinctrl_pwr_en: pwr_engrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
+ >;
+ };
+
+ pinctrl_wwan: wwan_grp {
+ fsl,pins = <
+ /* nWWAN_DISABLE */
+ MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09
+ /* nWoWWAN */
+ MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80
+ /* WWAN_RESET */
+ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
+ >;
+ };
+
+ pinctrl_dsi: dsigrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x16
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
+ >;
+ };
+
+ pinctrl_hdmi: hdmigrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x16
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000001f
+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000001f
+ >;
+ };
+
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
+ MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
+ >;
+ };
+
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
+ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
+ MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16
+ >;
+ };
+
+ pinctrl_pcie1: pcie1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x16
+ MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
+ MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16
+ >;
+ };
+
+
+ pinctrl_typec: typecgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
+ MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
+ MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
+ MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
+ MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
+ MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
+ MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
+ MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
+ MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
+ MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
+ >;
+ };
+
+ pinctrl_bt: btgrp {
+ fsl,pins = <
+ /* nBT_DISABLE */
+ MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
+ /* BT_HOST_WAKE */
+ MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10
+ >;
+ };
+
+ pinctrl_modem_reset: modem_reset {
+ fsl,pins = <
+ /* WWAN_RESET */
+ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
+ MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
+ /* WIFI_WAKE */
+ MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
+ >;
+ };
+
+ pinctrl_sai2: sai2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
+ >;
+ };
+
+ pinctrl_sai5: sai5grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_sai6: sai6grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
+ MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
+ MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
+ MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
+ >;
+ };
+
+ pinctrl_spdif1: spdif1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
+ MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+
+ pinctrl_pwm1: pwm1 {
+ fsl,pins = <
+ /* DSI_BL_PWM */
+ MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6
+ >;
+ };
+
+ pinctrl_micsel: micselgrp {
+ fsl,pins = <
+ /* mic sel */
+ MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6
+ >;
+ };
+
+ pinctrl_haptic: hapticgrp {
+ fsl,pins = <
+ /* nHAPTIC */
+ MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0xc6
+ >;
+ };
+
+ pinctrl_mute: mute {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x86 /* MUTE */
+ >;
+ };
+
+ pinctrl_pwm4: pwm4 {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0xc6
+ >;
+ };
+
+ pinctrl_prox: prox_nint {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80
+ >;
+ };
+
+ pinctrl_charger: charger_nirq {
+ fsl,pins = <
+ /* CHRG_nINT */
+ MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80
+ >;
+ };
+
+ pinctrl_rtc: rtcirq {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80
+ >;
+ };
+
+ pinctrl_pmic: pmic_int {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80
+ >;
+ };
+
+ pinctrl_spi1: spi1 {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x0f
+ MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x0f
+ MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x0f
+ MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x09
+ >;
+ };
+
+ pinctrl_imu: imugrp {
+ fsl,pins = <
+ /* IMU_INT */
+ MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8
+ >;
+ };
+
+ pinctrl_gpio_leds: gpioleds {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeys {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
+ MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
+ /* HP_DET */
+ MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180
+ >;
+ };
+
+ pinctrl_goodix_ts: gt5688 {
+ fsl,pins = <
+ /* TOUCH INT */
+ MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16
+ /* TOUCH RST */
+ MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
+ >;
+ };
+
+ };
+};
+
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: bd71837@4b {
+ reg = <0x4b>;
+ compatible = "rohm,bd71837";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ clocks = <&pmic_osc>;
+ clock-names = "osc";
+ clock-output-names = "pmic_clk";
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+ interrupt-names = "irq";
+ rohm,reset-snvs-powered;
+
+ gpo {
+ /* 0b0000_1100 all gpos with cmos output mode */
+ rohm,drv = <0x0C>;
+ };
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ buck1_reg: BUCK1 {
+ reg = <0>;
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <900000>;
+ rohm,dvs-idle-voltage = <850000>;
+ rohm,dvs-suspend-voltage = <800000>;
+ };
+
+ buck2_reg: BUCK2 {
+ reg = <1>;
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3_reg: BUCK3 {
+ reg = <2>;
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ rohm,dvs-run-voltage = <1000000>;
+ };
+
+ buck4_reg: BUCK4 {
+ reg = <3>;
+ regulator-name = "buck4";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ rohm,dvs-run-voltage = <1000000>;
+ };
+
+ buck5_reg: BUCK5 {
+ reg = <4>;
+ regulator-name = "buck5";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ reg = <5>;
+ regulator-name = "buck6";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck7_reg: BUCK7 {
+ reg = <6>;
+ regulator-name = "buck7";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck8_reg: BUCK8 {
+ reg = <7>;
+ regulator-name = "buck8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ reg = <8>;
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ reg = <9>;
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ reg = <10>;
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ reg = <11>;
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo5_reg: LDO5 {
+ reg = <12>;
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ reg = <13>;
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo7_reg: LDO7 {
+ reg = <14>;
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ typec_ptn5100: ptn5110@52 {
+ compatible = "nxp,ptn5110";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ reg = <0x52>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+ ss-sel-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ data-role = "dual";
+ power-role = "dual";
+ try-power-role = "sink";
+ source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
+ sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 12000, 2000)>;
+ op-sink-microwatt = <10000000>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ usb_con_hs: endpoint {
+ remote-endpoint = <&typec_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ usb_con_ss: endpoint {
+ remote-endpoint = <&typec_ss>;
+ };
+ };
+ };
+ };
+
+ };
+
+ charger: charger@6b { /* bq25896 */
+ compatible = "ti,bq25890";
+ reg = <0x6b>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_charger>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+ ti,battery-regulation-voltage = <4192000>; // 4.192V
+ ti,charge-current = <1600000>; // 1.6 A
+ ti,termination-current = <66000>; // 66mA
+ ti,precharge-current = <1300000>; // 1.3A
+ ti,minimum-sys-voltage = <2750000>; // 2.75V
+ ti,boost-voltage = <5000000>; // 5V
+ ti,boost-max-current = <50000>; // 50mA
+ };
+
+ rtc@68 {
+ pinctrl-names = "default";
+ compatible = "microcrystal,rv4162";
+ reg = <0x68>;
+ pinctrl-0 = <&pinctrl_rtc>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "disabled";
+};
+
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3>, <&pinctrl_imu>;
+ status = "okay";
+
+ lsm9d: lsm9d@6a {
+ compatible = "st,lsm9ds1-gyro";
+ reg = <0x6a>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+ power-supply = <®_pwr_en>;
+ };
+};
+
+&usb3_phy0 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ typec_hs: endpoint {
+ remote-endpoint = <&usb_con_hs>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ typec_ss: endpoint {
+ remote-endpoint = <&usb_con_ss>;
+ };
+ };
+};
+
+&usb_dwc3_0 {
+ status = "okay";
+ extcon = <&typec_ptn5100>;
+ dr_mode = "otg";
+};
+
+&usb3_phy1 {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
+
+&usb_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&uart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ status = "okay";
+};
+
+&uart4 { /* BT */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
+ fsl,uart-has-rtscts;
+ /* resets = <&modem_reset>; */
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/3] arm64: dts: fsl: Build the Librem5 devkit devicetree
2019-03-11 23:46 [PATCH 0/3] Add support for the Purism Librem5 devkit Angus Ainslie (Purism)
2019-03-11 23:46 ` [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the " Angus Ainslie (Purism)
@ 2019-03-11 23:46 ` Angus Ainslie (Purism)
2019-03-12 0:10 ` Fabio Estevam
2019-03-12 6:24 ` Daniel Baluta
2019-03-11 23:46 ` [PATCH 3/3] arm64: librem5-devkit: Add defconfig for the Librem5 devkit Angus Ainslie (Purism)
2 siblings, 2 replies; 14+ messages in thread
From: Angus Ainslie (Purism) @ 2019-03-11 23:46 UTC (permalink / raw)
To: Mark Rutland
Cc: Rob Herring, Shawn Guo, Fabio Estevam, kernel, Lucas Stach,
abel.vesa, daniel.baluta, agx, linux-imx, devicetree,
linux-kernel, Angus Ainslie (Purism)
Compile the Librem5 devkit device tree
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 13604e558dc1..95526ee3c27a 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -22,3 +22,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/3] arm64: librem5-devkit: Add defconfig for the Librem5 devkit
2019-03-11 23:46 [PATCH 0/3] Add support for the Purism Librem5 devkit Angus Ainslie (Purism)
2019-03-11 23:46 ` [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the " Angus Ainslie (Purism)
2019-03-11 23:46 ` [PATCH 2/3] arm64: dts: fsl: Build the Librem5 devkit devicetree Angus Ainslie (Purism)
@ 2019-03-11 23:46 ` Angus Ainslie (Purism)
2019-03-12 0:11 ` Fabio Estevam
2019-03-12 6:25 ` Daniel Baluta
2 siblings, 2 replies; 14+ messages in thread
From: Angus Ainslie (Purism) @ 2019-03-11 23:46 UTC (permalink / raw)
To: Mark Rutland
Cc: Rob Herring, Shawn Guo, Fabio Estevam, kernel, Lucas Stach,
abel.vesa, daniel.baluta, agx, linux-imx, devicetree,
linux-kernel, Angus Ainslie (Purism)
Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
arch/arm64/configs/librem5-devkit_defconfig | 534 ++++++++++++++++++++
1 file changed, 534 insertions(+)
create mode 100644 arch/arm64/configs/librem5-devkit_defconfig
diff --git a/arch/arm64/configs/librem5-devkit_defconfig b/arch/arm64/configs/librem5-devkit_defconfig
new file mode 100644
index 000000000000..98198b5335c8
--- /dev/null
+++ b/arch/arm64/configs/librem5-devkit_defconfig
@@ -0,0 +1,534 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_GENERIC_IRQ_DEBUGFS=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_PSI=y
+CONFIG_PSI_DEFAULT_DISABLED=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_PERF=y
+CONFIG_USER_NS=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_ARCH_MXC=y
+# CONFIG_ARM64_ERRATUM_1188873 is not set
+# CONFIG_ARM64_ERRATUM_1165522 is not set
+# CONFIG_ARM64_ERRATUM_1286807 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_SCHED_MC=y
+CONFIG_NR_CPUS=64
+CONFIG_SECCOMP=y
+# CONFIG_ARM64_SVE is not set
+CONFIG_COMPAT=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_ENERGY_MODEL=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_ARM_SCPI_PROTOCOL=y
+# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set
+CONFIG_ACPI=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_ARM64_CRYPTO=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=m
+CONFIG_CRYPTO_SHA2_ARM64_CE=m
+CONFIG_CRYPTO_SHA512_ARM64_CE=m
+CONFIG_CRYPTO_SHA3_ARM64=m
+CONFIG_CRYPTO_SM3_ARM64_CE=m
+CONFIG_CRYPTO_SM4_ARM64_CE=m
+CONFIG_CRYPTO_GHASH_ARM64_CE=m
+CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=m
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=m
+CONFIG_CRYPTO_CHACHA20_NEON=m
+CONFIG_CRYPTO_NHPOLY1305_NEON=m
+CONFIG_CRYPTO_AES_ARM64_BS=m
+CONFIG_JUMP_LABEL=y
+# CONFIG_VMAP_STACK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MQ_IOSCHED_DEADLINE=m
+CONFIG_MQ_IOSCHED_KYBER=m
+CONFIG_IOSCHED_BFQ=m
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_KSM=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_CMA=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_TLS=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_INET_RAW_DIAG=m
+CONFIG_IPV6=m
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_LOG_NETDEV=m
+CONFIG_NF_CONNTRACK_EVENTS=y
+# CONFIG_NF_CT_PROTO_DCCP is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CT_PROTO_UDPLITE is not set
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NF_SOCKET_IPV4=m
+CONFIG_NF_TPROXY_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_NF_SOCKET_IPV6=m
+CONFIG_NF_TPROXY_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_SRH=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_LLC2=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_BPF_JIT=y
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_BNEP=m
+CONFIG_BT_HIDP=m
+CONFIG_BT_LEDS=y
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIUART_BCM=y
+CONFIG_BT_HCIUART_QCA=y
+CONFIG_BT_HCIVHCI=m
+CONFIG_NET_9P=y
+CONFIG_NET_9P_VIRTIO=y
+CONFIG_FAILOVER=y
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_IOV=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCIE_XILINX=y
+CONFIG_PCI_XGENE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_FW_LOADER_USER_HELPER=y
+CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
+CONFIG_DEBUG_DRIVER=y
+CONFIG_IMX_WEIM=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_GNSS=m
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SRAM=y
+CONFIG_EEPROM_EE1004=m
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_IMX=m
+# CONFIG_ATA_SFF is not set
+CONFIG_NETDEVICES=y
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_TUN=m
+CONFIG_VETH=m
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_AURORA is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CAVIUM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+CONFIG_FEC=y
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_HUAWEI is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_SOCIONEXT is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_POLLDEV=y
+CONFIG_INPUT_MATRIXKMAP=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_IMX=m
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_EXAR is not set
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_DEV_BUS=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_IMX_RNGC=m
+# CONFIG_HW_RANDOM_CAVIUM is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_IMX_LPI2C=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_SLAVE=y
+CONFIG_SPI=y
+CONFIG_SPI_MEM=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_FSL_LPSPI=y
+CONFIG_SPI_IMX=m
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=m
+CONFIG_SPMI=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_SINGLE=y
+CONFIG_PINCTRL_MAX77620=y
+CONFIG_PINCTRL_IMX8MQ=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_XGENE=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_MAX77620=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_CHARGER_BQ25890=y
+CONFIG_SENSORS_ARM_SCPI=y
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_INA2XX=m
+CONFIG_THERMAL_WRITABLE_TRIPS=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_CPU_THERMAL=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_IMX_THERMAL=y
+CONFIG_QORIQ_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=m
+CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_ROHM_BD718XX=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_BD718XX=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX77620=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_IMX_PXP=m
+CONFIG_DRM=y
+CONFIG_DRM_I2C_NXP_TDA9950=m
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_I2C_ADV7511=y
+CONFIG_DRM_HISI_KIRIN=m
+CONFIG_DRM_MXSFB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_BACKLIGHT_GENERIC=m
+CONFIG_BACKLIGHT_LP855X=m
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+# CONFIG_HID_REDRAGON is not set
+CONFIG_HID_MULTITOUCH=y
+CONFIG_USB=m
+CONFIG_USB_OTG=y
+CONFIG_USB_OTG_FSM=m
+CONFIG_USB_XHCI_HCD=m
+CONFIG_USB_EHCI_HCD=m
+CONFIG_USB_EHCI_MXC=m
+CONFIG_USB_EHCI_HCD_PLATFORM=m
+CONFIG_USB_ACM=m
+CONFIG_USB_STORAGE=m
+CONFIG_USB_STORAGE_REALTEK=m
+CONFIG_USB_STORAGE_DATAFAB=m
+CONFIG_USB_STORAGE_FREECOM=m
+CONFIG_USB_STORAGE_ISD200=m
+CONFIG_USB_STORAGE_USBAT=m
+CONFIG_USB_STORAGE_SDDR09=m
+CONFIG_USB_STORAGE_SDDR55=m
+CONFIG_USB_STORAGE_JUMPSHOT=m
+CONFIG_USB_STORAGE_ALAUDA=m
+CONFIG_USB_STORAGE_ONETOUCH=m
+CONFIG_USB_STORAGE_KARMA=m
+CONFIG_USB_STORAGE_CYPRESS_ATACB=m
+CONFIG_USB_STORAGE_ENE_UB6250=m
+CONFIG_USB_UAS=m
+CONFIG_USB_DWC3=m
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_SIMPLE=m
+CONFIG_USB_SERIAL_FTDI_SIO=m
+CONFIG_USB_SERIAL_PL2303=m
+CONFIG_USB_SERIAL_QCAUX=m
+CONFIG_USB_SERIAL_QUALCOMM=m
+CONFIG_USB_SERIAL_SIERRAWIRELESS=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_MXS_PHY=m
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=m
+CONFIG_USB_FSL_USB2=m
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_CONFIGFS_F_HID=y
+CONFIG_USB_CONFIGFS_F_UVC=y
+CONFIG_USB_CONFIGFS_F_PRINTER=y
+CONFIG_USB_ETH=m
+CONFIG_USB_G_NCM=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FUNCTIONFS=m
+CONFIG_USB_FUNCTIONFS_RNDIS=y
+CONFIG_USB_FUNCTIONFS_GENERIC=y
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+CONFIG_USB_G_ACM_MS=m
+CONFIG_USB_G_MULTI=m
+CONFIG_TYPEC=m
+CONFIG_TYPEC_TCPM=m
+CONFIG_TYPEC_TCPCI=m
+CONFIG_TYPEC_RT1711H=m
+CONFIG_TYPEC_UCSI=m
+CONFIG_UCSI_ACPI=m
+CONFIG_USB_ULPI_BUS=m
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SPI=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_M41T80=y
+CONFIG_RTC_DRV_S5M=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_PL031=y
+CONFIG_RTC_DRV_SNVS=y
+CONFIG_DMADEVICES=y
+CONFIG_IMX_SDMA=m
+# CONFIG_MX3_IPU is not set
+# CONFIG_VIRTIO_MENU is not set
+CONFIG_STAGING=y
+CONFIG_COMMON_CLK_VERSATILE=y
+# CONFIG_COMMON_CLK_XGENE is not set
+CONFIG_CLK_IMX8MQ=y
+# CONFIG_HISILICON_ERRATUM_161010101 is not set
+# CONFIG_ARM64_ERRATUM_858921 is not set
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_MAILBOX=y
+CONFIG_ARM_MHU=y
+CONFIG_IMX_MBOX=y
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_V3=y
+CONFIG_RPMSG_VIRTIO=y
+CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_PHY_XGENE=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_HUGETLBFS=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_EFIVAR_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+# CONFIG_NFS_V2 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+CONFIG_SUNRPC_DEBUG=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_KEYS=y
+CONFIG_SECURITY=y
+# CONFIG_INTEGRITY is not set
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_OFB=m
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_STREEBOG=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_CAST5=y
+CONFIG_CRYPTO_CAST6=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_SERPENT=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_ASYMMETRIC_KEY_TYPE=y
+CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
+CONFIG_X509_CERTIFICATE_PARSER=y
+CONFIG_PKCS7_MESSAGE_PARSER=y
+CONFIG_SYSTEM_TRUSTED_KEYRING=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC64=y
+CONFIG_LIBCRC32C=m
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=320
+CONFIG_PRINTK_TIME=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
+# CONFIG_RUNTIME_TESTING_MENU is not set
+CONFIG_MEMTEST=y
+# CONFIG_STRICT_DEVMEM is not set
--
2.17.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit
2019-03-11 23:46 ` [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the " Angus Ainslie (Purism)
@ 2019-03-12 0:10 ` Fabio Estevam
2019-03-12 13:18 ` Angus Ainslie
2019-03-12 17:59 ` Guido Günther
2019-03-13 19:06 ` Rob Herring
2 siblings, 1 reply; 14+ messages in thread
From: Fabio Estevam @ 2019-03-12 0:10 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Mark Rutland, Rob Herring, Shawn Guo, Sascha Hauer, Lucas Stach,
Abel Vesa, Daniel Baluta, Guido Günther, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
On Mon, Mar 11, 2019 at 8:47 PM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
> +/ {
> + model = "Purism Librem 5 devkit 1.0";
> + compatible = "fsl,librem5-devkit", "fsl,imx8mq";
This board is not manufactured by FSL/NXP, so it should be
"purism,librem5-devkit", "fsl,imx8mq" instead.
You should also add an entry for the purism vendor entry in
Documentation/devicetree/bindings/vendor-prefixes.txt in a separate
patch.
> +
> + chosen {
> + stdout-path = &uart1;
> + };
> +
> + reg_usdhc2_vmmc: regulator-vsd-3v3 {
The usual format would be:
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
> + compatible = "regulator-fixed";
> + regulator-name = "VSD_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
Always on? It would be better to pass this regulator inside the mmc node.
> + };
> +
> + reg_pwr_en: pwr_en {
reg_pwr_en: regulator-pwr-en {
> + compatible = "regulator-fixed";
> + regulator-name = "PWR_EN";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
Same here. No need for "regulator-always-on" as it is controlled by
the gyroscope.
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + fsl,magic-packet;
> + status = "okay";
> + phy-supply = <®_pwr_en>;
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
You pass @0 and use reg = <1>, which is a mismatch. Building it with
W=1 would have warned you about this mismatch.
> + at803x,led-act-blind-workaround;
> + at803x,eee-disabled;
> + power-supply = <®_pwr_en>;
> + };
> + };
> +};
> +
> +&iomuxc {
> + imx8m-som {
No need for this imx8m-som level.
> + pinctrl_nc: ncgrp {
Not a very descriptive naming.
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x00
> + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
> + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
> + >;
> + };
> +
> + pinctrl_up: upgrp {
Same here. Also, this is not used. Please remove it.
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x00
> + >;
> + };
> +
> + pinctrl_csi1: csi1grp {
This is not used at the moment. Please remove it and re-add it when
CSI gets supported.
> + fsl,pins = <
> + /* CSI_nRST */
> + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x11
> + /* CSI_PWDN */
> + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
> + /* CLK01 */
> + MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x19
> + >;
> + };
> +
> + pinctrl_pwr_en: pwr_engrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
> + >;
> + };
> +
> + pinctrl_wwan: wwan_grp {
Not used. Please remove this one and all unused pinctrl nodes.
> +&i2c1 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + pmic: bd71837@4b {
Node names should be generic: pmic@4b
> + typec_ptn5100: ptn5110@52 {
Same here.
> + charger: charger@6b { /* bq25896 */
> + compatible = "ti,bq25890";
> + reg = <0x6b>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_charger>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> + ti,battery-regulation-voltage = <4192000>; // 4.192V
> + ti,charge-current = <1600000>; // 1.6 A
> + ti,termination-current = <66000>; // 66mA
> + ti,precharge-current = <1300000>; // 1.3A
> + ti,minimum-sys-voltage = <2750000>; // 2.75V
> + ti,boost-voltage = <5000000>; // 5V
> + ti,boost-max-current = <50000>; // 50mA
No // style comments, please/
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>, <&pinctrl_imu>;
> + status = "okay";
> +
> + lsm9d: lsm9d@6a {
> + compatible = "st,lsm9ds1-gyro";
I don't find this binding.
> + reg = <0x6a>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
> + power-supply = <®_pwr_en>;
> + };
> +};
> +&uart4 { /* BT */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
> + fsl,uart-has-rtscts;
uart-has-rtscts is preferred.
> + /* resets = <&modem_reset>; */
Please remove this line instead of commenting it out.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] arm64: dts: fsl: Build the Librem5 devkit devicetree
2019-03-11 23:46 ` [PATCH 2/3] arm64: dts: fsl: Build the Librem5 devkit devicetree Angus Ainslie (Purism)
@ 2019-03-12 0:10 ` Fabio Estevam
2019-03-12 6:24 ` Daniel Baluta
1 sibling, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2019-03-12 0:10 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Mark Rutland, Rob Herring, Shawn Guo, Sascha Hauer, Lucas Stach,
Abel Vesa, Daniel Baluta, Guido Günther, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
On Mon, Mar 11, 2019 at 8:47 PM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> Compile the Librem5 devkit device tree
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 13604e558dc1..95526ee3c27a 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -22,3 +22,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
>
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
This should be part of the previous patch that adds the dts.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] arm64: librem5-devkit: Add defconfig for the Librem5 devkit
2019-03-11 23:46 ` [PATCH 3/3] arm64: librem5-devkit: Add defconfig for the Librem5 devkit Angus Ainslie (Purism)
@ 2019-03-12 0:11 ` Fabio Estevam
2019-03-12 6:25 ` Daniel Baluta
1 sibling, 0 replies; 14+ messages in thread
From: Fabio Estevam @ 2019-03-12 0:11 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Mark Rutland, Rob Herring, Shawn Guo, Sascha Hauer, Lucas Stach,
Abel Vesa, Daniel Baluta, Guido Günther, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
On Mon, Mar 11, 2019 at 8:47 PM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
No commit log?
Not sure if we want to add a new defconfig for a single board.
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/3] arm64: dts: fsl: Build the Librem5 devkit devicetree
2019-03-11 23:46 ` [PATCH 2/3] arm64: dts: fsl: Build the Librem5 devkit devicetree Angus Ainslie (Purism)
2019-03-12 0:10 ` Fabio Estevam
@ 2019-03-12 6:24 ` Daniel Baluta
1 sibling, 0 replies; 14+ messages in thread
From: Daniel Baluta @ 2019-03-12 6:24 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Mark Rutland, Rob Herring, Shawn Guo, Fabio Estevam,
Pengutronix Kernel Team, Lucas Stach, Abel Vesa, Daniel Baluta,
agx, dl-linux-imx, Devicetree List, Linux Kernel Mailing List
On Tue, Mar 12, 2019 at 1:48 AM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> Compile the Librem5 devkit device tree
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 13604e558dc1..95526ee3c27a 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -22,3 +22,4 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
>
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
This should be in alphabetical order. So move this immediately
after imx8mq-evk.dtb
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/3] arm64: librem5-devkit: Add defconfig for the Librem5 devkit
2019-03-11 23:46 ` [PATCH 3/3] arm64: librem5-devkit: Add defconfig for the Librem5 devkit Angus Ainslie (Purism)
2019-03-12 0:11 ` Fabio Estevam
@ 2019-03-12 6:25 ` Daniel Baluta
1 sibling, 0 replies; 14+ messages in thread
From: Daniel Baluta @ 2019-03-12 6:25 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Mark Rutland, Rob Herring, Shawn Guo, Fabio Estevam,
Pengutronix Kernel Team, Lucas Stach, Abel Vesa, Daniel Baluta,
agx, dl-linux-imx, Devicetree List, Linux Kernel Mailing List
On Tue, Mar 12, 2019 at 1:47 AM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
Hi Angus,
My impression was that for arm64 world there will be only one
defconfig. So, I'm not
sure if this patch would be acceptable.
thanks,
Daniel.
> ---
> arch/arm64/configs/librem5-devkit_defconfig | 534 ++++++++++++++++++++
> 1 file changed, 534 insertions(+)
> create mode 100644 arch/arm64/configs/librem5-devkit_defconfig
>
> diff --git a/arch/arm64/configs/librem5-devkit_defconfig b/arch/arm64/configs/librem5-devkit_defconfig
> new file mode 100644
> index 000000000000..98198b5335c8
> --- /dev/null
> +++ b/arch/arm64/configs/librem5-devkit_defconfig
> @@ -0,0 +1,534 @@
> +CONFIG_SYSVIPC=y
> +CONFIG_POSIX_MQUEUE=y
> +CONFIG_AUDIT=y
> +CONFIG_GENERIC_IRQ_DEBUGFS=y
> +CONFIG_NO_HZ_IDLE=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_PREEMPT=y
> +CONFIG_BSD_PROCESS_ACCT=y
> +CONFIG_BSD_PROCESS_ACCT_V3=y
> +CONFIG_TASKSTATS=y
> +CONFIG_TASK_DELAY_ACCT=y
> +CONFIG_TASK_XACCT=y
> +CONFIG_TASK_IO_ACCOUNTING=y
> +CONFIG_PSI=y
> +CONFIG_PSI_DEFAULT_DISABLED=y
> +CONFIG_IKCONFIG=y
> +CONFIG_IKCONFIG_PROC=y
> +CONFIG_MEMCG=y
> +CONFIG_MEMCG_SWAP=y
> +CONFIG_BLK_CGROUP=y
> +CONFIG_CGROUP_PIDS=y
> +CONFIG_CGROUP_HUGETLB=y
> +CONFIG_CPUSETS=y
> +CONFIG_CGROUP_DEVICE=y
> +CONFIG_CGROUP_CPUACCT=y
> +CONFIG_CGROUP_PERF=y
> +CONFIG_USER_NS=y
> +CONFIG_SCHED_AUTOGROUP=y
> +CONFIG_RELAY=y
> +CONFIG_BLK_DEV_INITRD=y
> +CONFIG_KALLSYMS_ALL=y
> +# CONFIG_COMPAT_BRK is not set
> +CONFIG_PROFILING=y
> +CONFIG_ARCH_MXC=y
> +# CONFIG_ARM64_ERRATUM_1188873 is not set
> +# CONFIG_ARM64_ERRATUM_1165522 is not set
> +# CONFIG_ARM64_ERRATUM_1286807 is not set
> +CONFIG_ARM64_VA_BITS_48=y
> +CONFIG_SCHED_MC=y
> +CONFIG_NR_CPUS=64
> +CONFIG_SECCOMP=y
> +# CONFIG_ARM64_SVE is not set
> +CONFIG_COMPAT=y
> +CONFIG_PM_DEBUG=y
> +CONFIG_PM_TEST_SUSPEND=y
> +CONFIG_ENERGY_MODEL=y
> +CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_STAT=y
> +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
> +CONFIG_CPU_FREQ_GOV_POWERSAVE=y
> +CONFIG_CPU_FREQ_GOV_USERSPACE=y
> +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
> +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
> +CONFIG_CPUFREQ_DT=y
> +CONFIG_ARM_SCPI_PROTOCOL=y
> +# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set
> +CONFIG_ACPI=y
> +CONFIG_VIRTUALIZATION=y
> +CONFIG_ARM64_CRYPTO=y
> +CONFIG_CRYPTO_SHA256_ARM64=y
> +CONFIG_CRYPTO_SHA1_ARM64_CE=m
> +CONFIG_CRYPTO_SHA2_ARM64_CE=m
> +CONFIG_CRYPTO_SHA512_ARM64_CE=m
> +CONFIG_CRYPTO_SHA3_ARM64=m
> +CONFIG_CRYPTO_SM3_ARM64_CE=m
> +CONFIG_CRYPTO_SM4_ARM64_CE=m
> +CONFIG_CRYPTO_GHASH_ARM64_CE=m
> +CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
> +CONFIG_CRYPTO_AES_ARM64_CE=y
> +CONFIG_CRYPTO_AES_ARM64_CE_CCM=m
> +CONFIG_CRYPTO_AES_ARM64_CE_BLK=m
> +CONFIG_CRYPTO_CHACHA20_NEON=m
> +CONFIG_CRYPTO_NHPOLY1305_NEON=m
> +CONFIG_CRYPTO_AES_ARM64_BS=m
> +CONFIG_JUMP_LABEL=y
> +# CONFIG_VMAP_STACK is not set
> +CONFIG_MODULES=y
> +CONFIG_MODULE_UNLOAD=y
> +CONFIG_MQ_IOSCHED_DEADLINE=m
> +CONFIG_MQ_IOSCHED_KYBER=m
> +CONFIG_IOSCHED_BFQ=m
> +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> +CONFIG_KSM=y
> +CONFIG_TRANSPARENT_HUGEPAGE=y
> +CONFIG_CMA=y
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_TLS=m
> +CONFIG_INET=y
> +CONFIG_IP_MULTICAST=y
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_IP_PNP_BOOTP=y
> +CONFIG_INET_RAW_DIAG=m
> +CONFIG_IPV6=m
> +CONFIG_NETFILTER=y
> +CONFIG_NF_CONNTRACK=m
> +CONFIG_NF_LOG_NETDEV=m
> +CONFIG_NF_CONNTRACK_EVENTS=y
> +# CONFIG_NF_CT_PROTO_DCCP is not set
> +# CONFIG_NF_CT_PROTO_SCTP is not set
> +# CONFIG_NF_CT_PROTO_UDPLITE is not set
> +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
> +CONFIG_NETFILTER_XT_TARGET_LOG=m
> +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
> +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
> +CONFIG_NETFILTER_XT_MATCH_OSF=m
> +CONFIG_NF_SOCKET_IPV4=m
> +CONFIG_NF_TPROXY_IPV4=m
> +CONFIG_IP_NF_IPTABLES=m
> +CONFIG_IP_NF_FILTER=m
> +CONFIG_IP_NF_TARGET_REJECT=m
> +CONFIG_IP_NF_NAT=m
> +CONFIG_IP_NF_TARGET_MASQUERADE=m
> +CONFIG_IP_NF_MANGLE=m
> +CONFIG_NF_SOCKET_IPV6=m
> +CONFIG_NF_TPROXY_IPV6=m
> +CONFIG_IP6_NF_IPTABLES=m
> +CONFIG_IP6_NF_MATCH_SRH=m
> +CONFIG_IP6_NF_FILTER=m
> +CONFIG_IP6_NF_TARGET_REJECT=m
> +CONFIG_IP6_NF_MANGLE=m
> +CONFIG_IP6_NF_NAT=m
> +CONFIG_IP6_NF_TARGET_MASQUERADE=m
> +CONFIG_BRIDGE=m
> +CONFIG_BRIDGE_VLAN_FILTERING=y
> +CONFIG_VLAN_8021Q=m
> +CONFIG_VLAN_8021Q_GVRP=y
> +CONFIG_VLAN_8021Q_MVRP=y
> +CONFIG_LLC2=y
> +CONFIG_DNS_RESOLVER=y
> +CONFIG_BPF_JIT=y
> +CONFIG_BT=m
> +CONFIG_BT_RFCOMM=m
> +CONFIG_BT_BNEP=m
> +CONFIG_BT_HIDP=m
> +CONFIG_BT_LEDS=y
> +CONFIG_BT_HCIUART=m
> +CONFIG_BT_HCIUART_BCSP=y
> +CONFIG_BT_HCIUART_ATH3K=y
> +CONFIG_BT_HCIUART_3WIRE=y
> +CONFIG_BT_HCIUART_BCM=y
> +CONFIG_BT_HCIUART_QCA=y
> +CONFIG_BT_HCIVHCI=m
> +CONFIG_NET_9P=y
> +CONFIG_NET_9P_VIRTIO=y
> +CONFIG_FAILOVER=y
> +CONFIG_PCI=y
> +CONFIG_PCIEPORTBUS=y
> +CONFIG_PCI_IOV=y
> +CONFIG_PCI_HOST_GENERIC=y
> +CONFIG_PCIE_XILINX=y
> +CONFIG_PCI_XGENE=y
> +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
> +CONFIG_FW_LOADER_USER_HELPER=y
> +CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
> +CONFIG_DEBUG_DRIVER=y
> +CONFIG_IMX_WEIM=y
> +CONFIG_VEXPRESS_CONFIG=y
> +CONFIG_GNSS=m
> +CONFIG_BLK_DEV_LOOP=y
> +CONFIG_SRAM=y
> +CONFIG_EEPROM_EE1004=m
> +# CONFIG_SCSI_PROC_FS is not set
> +CONFIG_BLK_DEV_SD=y
> +CONFIG_SCSI_SAS_LIBSAS=y
> +CONFIG_SCSI_SAS_ATA=y
> +CONFIG_ATA=y
> +CONFIG_SATA_AHCI=y
> +CONFIG_SATA_AHCI_PLATFORM=y
> +CONFIG_AHCI_IMX=m
> +# CONFIG_ATA_SFF is not set
> +CONFIG_NETDEVICES=y
> +CONFIG_MACVLAN=m
> +CONFIG_MACVTAP=m
> +CONFIG_TUN=m
> +CONFIG_VETH=m
> +# CONFIG_NET_VENDOR_3COM is not set
> +# CONFIG_NET_VENDOR_ADAPTEC is not set
> +# CONFIG_NET_VENDOR_AGERE is not set
> +# CONFIG_NET_VENDOR_ALACRITECH is not set
> +# CONFIG_NET_VENDOR_ALTEON is not set
> +# CONFIG_NET_VENDOR_AMAZON is not set
> +# CONFIG_NET_VENDOR_AMD is not set
> +# CONFIG_NET_VENDOR_AQUANTIA is not set
> +# CONFIG_NET_VENDOR_ARC is not set
> +# CONFIG_NET_VENDOR_ATHEROS is not set
> +# CONFIG_NET_VENDOR_AURORA is not set
> +# CONFIG_NET_VENDOR_BROADCOM is not set
> +# CONFIG_NET_VENDOR_BROCADE is not set
> +# CONFIG_NET_VENDOR_CAVIUM is not set
> +# CONFIG_NET_VENDOR_CHELSIO is not set
> +# CONFIG_NET_VENDOR_CISCO is not set
> +# CONFIG_NET_VENDOR_CORTINA is not set
> +# CONFIG_NET_VENDOR_DLINK is not set
> +# CONFIG_NET_VENDOR_EMULEX is not set
> +# CONFIG_NET_VENDOR_EZCHIP is not set
> +CONFIG_FEC=y
> +# CONFIG_NET_VENDOR_HISILICON is not set
> +# CONFIG_NET_VENDOR_HP is not set
> +# CONFIG_NET_VENDOR_HUAWEI is not set
> +# CONFIG_NET_VENDOR_INTEL is not set
> +# CONFIG_NET_VENDOR_MARVELL is not set
> +# CONFIG_NET_VENDOR_MELLANOX is not set
> +# CONFIG_NET_VENDOR_MICREL is not set
> +# CONFIG_NET_VENDOR_MICROCHIP is not set
> +# CONFIG_NET_VENDOR_MICROSEMI is not set
> +# CONFIG_NET_VENDOR_MYRI is not set
> +# CONFIG_NET_VENDOR_NATSEMI is not set
> +# CONFIG_NET_VENDOR_NETRONOME is not set
> +# CONFIG_NET_VENDOR_NI is not set
> +# CONFIG_NET_VENDOR_NVIDIA is not set
> +# CONFIG_NET_VENDOR_OKI is not set
> +# CONFIG_NET_VENDOR_QLOGIC is not set
> +# CONFIG_NET_VENDOR_QUALCOMM is not set
> +# CONFIG_NET_VENDOR_REALTEK is not set
> +# CONFIG_NET_VENDOR_ROCKER is not set
> +# CONFIG_NET_VENDOR_SAMSUNG is not set
> +# CONFIG_NET_VENDOR_SEEQ is not set
> +# CONFIG_NET_VENDOR_SOLARFLARE is not set
> +# CONFIG_NET_VENDOR_SILAN is not set
> +# CONFIG_NET_VENDOR_SIS is not set
> +# CONFIG_NET_VENDOR_SMSC is not set
> +# CONFIG_NET_VENDOR_SOCIONEXT is not set
> +# CONFIG_NET_VENDOR_STMICRO is not set
> +# CONFIG_NET_VENDOR_SUN is not set
> +# CONFIG_NET_VENDOR_SYNOPSYS is not set
> +# CONFIG_NET_VENDOR_TEHUTI is not set
> +# CONFIG_NET_VENDOR_TI is not set
> +# CONFIG_NET_VENDOR_VIA is not set
> +# CONFIG_NET_VENDOR_WIZNET is not set
> +# CONFIG_WLAN is not set
> +CONFIG_INPUT_POLLDEV=y
> +CONFIG_INPUT_MATRIXKMAP=y
> +CONFIG_INPUT_MOUSEDEV=y
> +CONFIG_INPUT_MOUSEDEV_PSAUX=y
> +CONFIG_INPUT_EVDEV=y
> +CONFIG_KEYBOARD_GPIO=y
> +CONFIG_KEYBOARD_IMX=m
> +# CONFIG_SERIO_SERPORT is not set
> +CONFIG_LEGACY_PTY_COUNT=16
> +CONFIG_SERIAL_8250=y
> +CONFIG_SERIAL_8250_CONSOLE=y
> +# CONFIG_SERIAL_8250_EXAR is not set
> +CONFIG_SERIAL_8250_DW=y
> +CONFIG_SERIAL_OF_PLATFORM=y
> +CONFIG_SERIAL_AMBA_PL011=y
> +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
> +CONFIG_SERIAL_IMX=y
> +CONFIG_SERIAL_IMX_CONSOLE=y
> +CONFIG_SERIAL_XILINX_PS_UART=y
> +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
> +CONFIG_SERIAL_FSL_LPUART=y
> +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
> +CONFIG_SERIAL_DEV_BUS=y
> +CONFIG_VIRTIO_CONSOLE=y
> +CONFIG_HW_RANDOM=y
> +CONFIG_HW_RANDOM_IMX_RNGC=m
> +# CONFIG_HW_RANDOM_CAVIUM is not set
> +CONFIG_I2C_CHARDEV=y
> +CONFIG_I2C_MUX_PCA954x=y
> +CONFIG_I2C_DESIGNWARE_PLATFORM=y
> +CONFIG_I2C_IMX=y
> +CONFIG_I2C_IMX_LPI2C=y
> +CONFIG_I2C_CROS_EC_TUNNEL=y
> +CONFIG_I2C_SLAVE=y
> +CONFIG_SPI=y
> +CONFIG_SPI_MEM=y
> +CONFIG_SPI_BITBANG=y
> +CONFIG_SPI_FSL_LPSPI=y
> +CONFIG_SPI_IMX=m
> +CONFIG_SPI_PL022=y
> +CONFIG_SPI_SPIDEV=m
> +CONFIG_SPMI=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCTRL_SINGLE=y
> +CONFIG_PINCTRL_MAX77620=y
> +CONFIG_PINCTRL_IMX8MQ=y
> +CONFIG_GPIOLIB=y
> +CONFIG_GPIO_SYSFS=y
> +CONFIG_GPIO_DWAPB=y
> +CONFIG_GPIO_PL061=y
> +CONFIG_GPIO_XGENE=y
> +CONFIG_GPIO_PCA953X=y
> +CONFIG_GPIO_PCA953X_IRQ=y
> +CONFIG_GPIO_MAX77620=y
> +CONFIG_POWER_RESET_VEXPRESS=y
> +CONFIG_POWER_RESET_XGENE=y
> +CONFIG_POWER_RESET_SYSCON=y
> +CONFIG_CHARGER_BQ25890=y
> +CONFIG_SENSORS_ARM_SCPI=y
> +CONFIG_SENSORS_LM90=m
> +CONFIG_SENSORS_INA2XX=m
> +CONFIG_THERMAL_WRITABLE_TRIPS=y
> +CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
> +CONFIG_CPU_THERMAL=y
> +CONFIG_THERMAL_EMULATION=y
> +CONFIG_IMX_THERMAL=y
> +CONFIG_QORIQ_THERMAL=y
> +CONFIG_WATCHDOG=y
> +CONFIG_IMX2_WDT=m
> +CONFIG_MFD_CROS_EC=y
> +CONFIG_MFD_MAX77620=y
> +CONFIG_MFD_SEC_CORE=y
> +CONFIG_MFD_ROHM_BD718XX=y
> +CONFIG_REGULATOR=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> +CONFIG_REGULATOR_BD718XX=y
> +CONFIG_REGULATOR_GPIO=y
> +CONFIG_REGULATOR_MAX77620=y
> +CONFIG_REGULATOR_PFUZE100=y
> +CONFIG_REGULATOR_PWM=y
> +CONFIG_REGULATOR_QCOM_SPMI=y
> +CONFIG_REGULATOR_S2MPS11=y
> +CONFIG_MEDIA_SUPPORT=y
> +CONFIG_MEDIA_CAMERA_SUPPORT=y
> +CONFIG_MEDIA_CONTROLLER=y
> +CONFIG_VIDEO_V4L2_SUBDEV_API=y
> +CONFIG_V4L_PLATFORM_DRIVERS=y
> +CONFIG_V4L_MEM2MEM_DRIVERS=y
> +CONFIG_VIDEO_IMX_PXP=m
> +CONFIG_DRM=y
> +CONFIG_DRM_I2C_NXP_TDA9950=m
> +CONFIG_DRM_NOUVEAU=m
> +CONFIG_DRM_PANEL_SIMPLE=m
> +CONFIG_DRM_I2C_ADV7511=y
> +CONFIG_DRM_HISI_KIRIN=m
> +CONFIG_DRM_MXSFB=y
> +CONFIG_FB_ARMCLCD=y
> +CONFIG_BACKLIGHT_GENERIC=m
> +CONFIG_BACKLIGHT_LP855X=m
> +CONFIG_LOGO=y
> +# CONFIG_LOGO_LINUX_MONO is not set
> +# CONFIG_LOGO_LINUX_VGA16 is not set
> +# CONFIG_HID_REDRAGON is not set
> +CONFIG_HID_MULTITOUCH=y
> +CONFIG_USB=m
> +CONFIG_USB_OTG=y
> +CONFIG_USB_OTG_FSM=m
> +CONFIG_USB_XHCI_HCD=m
> +CONFIG_USB_EHCI_HCD=m
> +CONFIG_USB_EHCI_MXC=m
> +CONFIG_USB_EHCI_HCD_PLATFORM=m
> +CONFIG_USB_ACM=m
> +CONFIG_USB_STORAGE=m
> +CONFIG_USB_STORAGE_REALTEK=m
> +CONFIG_USB_STORAGE_DATAFAB=m
> +CONFIG_USB_STORAGE_FREECOM=m
> +CONFIG_USB_STORAGE_ISD200=m
> +CONFIG_USB_STORAGE_USBAT=m
> +CONFIG_USB_STORAGE_SDDR09=m
> +CONFIG_USB_STORAGE_SDDR55=m
> +CONFIG_USB_STORAGE_JUMPSHOT=m
> +CONFIG_USB_STORAGE_ALAUDA=m
> +CONFIG_USB_STORAGE_ONETOUCH=m
> +CONFIG_USB_STORAGE_KARMA=m
> +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
> +CONFIG_USB_STORAGE_ENE_UB6250=m
> +CONFIG_USB_UAS=m
> +CONFIG_USB_DWC3=m
> +CONFIG_USB_SERIAL=m
> +CONFIG_USB_SERIAL_GENERIC=y
> +CONFIG_USB_SERIAL_SIMPLE=m
> +CONFIG_USB_SERIAL_FTDI_SIO=m
> +CONFIG_USB_SERIAL_PL2303=m
> +CONFIG_USB_SERIAL_QCAUX=m
> +CONFIG_USB_SERIAL_QUALCOMM=m
> +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
> +CONFIG_USB_SERIAL_OPTION=m
> +CONFIG_USB_MXS_PHY=m
> +CONFIG_USB_ULPI=y
> +CONFIG_USB_GADGET=m
> +CONFIG_USB_FSL_USB2=m
> +CONFIG_USB_CONFIGFS=m
> +CONFIG_USB_CONFIGFS_SERIAL=y
> +CONFIG_USB_CONFIGFS_ACM=y
> +CONFIG_USB_CONFIGFS_OBEX=y
> +CONFIG_USB_CONFIGFS_NCM=y
> +CONFIG_USB_CONFIGFS_ECM=y
> +CONFIG_USB_CONFIGFS_ECM_SUBSET=y
> +CONFIG_USB_CONFIGFS_RNDIS=y
> +CONFIG_USB_CONFIGFS_EEM=y
> +CONFIG_USB_CONFIGFS_MASS_STORAGE=y
> +CONFIG_USB_CONFIGFS_F_LB_SS=y
> +CONFIG_USB_CONFIGFS_F_FS=y
> +CONFIG_USB_CONFIGFS_F_HID=y
> +CONFIG_USB_CONFIGFS_F_UVC=y
> +CONFIG_USB_CONFIGFS_F_PRINTER=y
> +CONFIG_USB_ETH=m
> +CONFIG_USB_G_NCM=m
> +CONFIG_USB_GADGETFS=m
> +CONFIG_USB_FUNCTIONFS=m
> +CONFIG_USB_FUNCTIONFS_RNDIS=y
> +CONFIG_USB_FUNCTIONFS_GENERIC=y
> +CONFIG_USB_MASS_STORAGE=m
> +CONFIG_USB_G_SERIAL=m
> +CONFIG_USB_G_PRINTER=m
> +CONFIG_USB_CDC_COMPOSITE=m
> +CONFIG_USB_G_ACM_MS=m
> +CONFIG_USB_G_MULTI=m
> +CONFIG_TYPEC=m
> +CONFIG_TYPEC_TCPM=m
> +CONFIG_TYPEC_TCPCI=m
> +CONFIG_TYPEC_RT1711H=m
> +CONFIG_TYPEC_UCSI=m
> +CONFIG_UCSI_ACPI=m
> +CONFIG_USB_ULPI_BUS=m
> +CONFIG_MMC=y
> +CONFIG_MMC_BLOCK_MINORS=32
> +CONFIG_MMC_ARMMMCI=y
> +CONFIG_MMC_SDHCI=y
> +CONFIG_MMC_SDHCI_PLTFM=y
> +CONFIG_MMC_SDHCI_ESDHC_IMX=y
> +CONFIG_MMC_SPI=y
> +CONFIG_NEW_LEDS=y
> +CONFIG_LEDS_CLASS=y
> +CONFIG_LEDS_GPIO=y
> +CONFIG_LEDS_PWM=y
> +CONFIG_LEDS_SYSCON=y
> +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> +CONFIG_LEDS_TRIGGER_CPU=y
> +CONFIG_RTC_CLASS=y
> +CONFIG_RTC_DRV_MAX77686=y
> +CONFIG_RTC_DRV_M41T80=y
> +CONFIG_RTC_DRV_S5M=y
> +CONFIG_RTC_DRV_DS3232=y
> +CONFIG_RTC_DRV_EFI=y
> +CONFIG_RTC_DRV_PL031=y
> +CONFIG_RTC_DRV_SNVS=y
> +CONFIG_DMADEVICES=y
> +CONFIG_IMX_SDMA=m
> +# CONFIG_MX3_IPU is not set
> +# CONFIG_VIRTIO_MENU is not set
> +CONFIG_STAGING=y
> +CONFIG_COMMON_CLK_VERSATILE=y
> +# CONFIG_COMMON_CLK_XGENE is not set
> +CONFIG_CLK_IMX8MQ=y
> +# CONFIG_HISILICON_ERRATUM_161010101 is not set
> +# CONFIG_ARM64_ERRATUM_858921 is not set
> +CONFIG_ARM_TIMER_SP804=y
> +CONFIG_MAILBOX=y
> +CONFIG_ARM_MHU=y
> +CONFIG_IMX_MBOX=y
> +CONFIG_ARM_SMMU=y
> +CONFIG_ARM_SMMU_V3=y
> +CONFIG_RPMSG_VIRTIO=y
> +CONFIG_IIO=y
> +CONFIG_PWM=y
> +CONFIG_RESET_CONTROLLER=y
> +CONFIG_PHY_XGENE=y
> +CONFIG_EXT2_FS=y
> +CONFIG_EXT3_FS=y
> +CONFIG_EXT4_FS_POSIX_ACL=y
> +CONFIG_FANOTIFY=y
> +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
> +CONFIG_AUTOFS4_FS=y
> +CONFIG_FUSE_FS=m
> +CONFIG_CUSE=m
> +CONFIG_VFAT_FS=y
> +CONFIG_TMPFS=y
> +CONFIG_HUGETLBFS=y
> +CONFIG_CONFIGFS_FS=y
> +CONFIG_EFIVAR_FS=y
> +CONFIG_SQUASHFS=y
> +CONFIG_NFS_FS=y
> +# CONFIG_NFS_V2 is not set
> +CONFIG_ROOT_NFS=y
> +# CONFIG_RPCSEC_GSS_KRB5 is not set
> +CONFIG_SUNRPC_DEBUG=y
> +CONFIG_NLS_CODEPAGE_437=y
> +CONFIG_NLS_ISO8859_1=y
> +CONFIG_KEYS=y
> +CONFIG_SECURITY=y
> +# CONFIG_INTEGRITY is not set
> +CONFIG_CRYPTO_RSA=y
> +CONFIG_CRYPTO_ECDH=y
> +CONFIG_CRYPTO_CRYPTD=y
> +CONFIG_CRYPTO_AUTHENC=y
> +CONFIG_CRYPTO_TEST=m
> +CONFIG_CRYPTO_CCM=y
> +CONFIG_CRYPTO_GCM=y
> +CONFIG_CRYPTO_CHACHA20POLY1305=y
> +CONFIG_CRYPTO_ECHAINIV=y
> +CONFIG_CRYPTO_CBC=y
> +CONFIG_CRYPTO_CTS=y
> +CONFIG_CRYPTO_LRW=y
> +CONFIG_CRYPTO_OFB=m
> +CONFIG_CRYPTO_XTS=y
> +CONFIG_CRYPTO_CMAC=y
> +CONFIG_CRYPTO_MD4=y
> +CONFIG_CRYPTO_MD5=y
> +CONFIG_CRYPTO_RMD128=m
> +CONFIG_CRYPTO_RMD160=m
> +CONFIG_CRYPTO_RMD256=m
> +CONFIG_CRYPTO_RMD320=m
> +CONFIG_CRYPTO_SHA1=y
> +CONFIG_CRYPTO_SHA512=y
> +CONFIG_CRYPTO_STREEBOG=m
> +CONFIG_CRYPTO_TGR192=m
> +CONFIG_CRYPTO_WP512=m
> +CONFIG_CRYPTO_ARC4=y
> +CONFIG_CRYPTO_BLOWFISH=y
> +CONFIG_CRYPTO_CAMELLIA=y
> +CONFIG_CRYPTO_CAST5=y
> +CONFIG_CRYPTO_CAST6=y
> +CONFIG_CRYPTO_DES=y
> +CONFIG_CRYPTO_SERPENT=y
> +CONFIG_CRYPTO_TWOFISH=y
> +CONFIG_CRYPTO_DEFLATE=y
> +CONFIG_CRYPTO_LZO=y
> +CONFIG_CRYPTO_ANSI_CPRNG=y
> +CONFIG_ASYMMETRIC_KEY_TYPE=y
> +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
> +CONFIG_X509_CERTIFICATE_PARSER=y
> +CONFIG_PKCS7_MESSAGE_PARSER=y
> +CONFIG_SYSTEM_TRUSTED_KEYRING=y
> +CONFIG_CRC_T10DIF=y
> +CONFIG_CRC64=y
> +CONFIG_LIBCRC32C=m
> +CONFIG_DMA_CMA=y
> +CONFIG_CMA_SIZE_MBYTES=320
> +CONFIG_PRINTK_TIME=y
> +CONFIG_MAGIC_SYSRQ=y
> +CONFIG_DEBUG_KERNEL=y
> +CONFIG_DETECT_HUNG_TASK=y
> +# CONFIG_SCHED_DEBUG is not set
> +# CONFIG_DEBUG_PREEMPT is not set
> +# CONFIG_FTRACE is not set
> +# CONFIG_RUNTIME_TESTING_MENU is not set
> +CONFIG_MEMTEST=y
> +# CONFIG_STRICT_DEVMEM is not set
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit
2019-03-12 0:10 ` Fabio Estevam
@ 2019-03-12 13:18 ` Angus Ainslie
0 siblings, 0 replies; 14+ messages in thread
From: Angus Ainslie @ 2019-03-12 13:18 UTC (permalink / raw)
To: Fabio Estevam
Cc: Mark Rutland, Rob Herring, Shawn Guo, Sascha Hauer, Lucas Stach,
Abel Vesa, Daniel Baluta, Guido Günther, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
Hi Fabio,
On 2019-03-11 17:10, Fabio Estevam wrote:
> On Mon, Mar 11, 2019 at 8:47 PM Angus Ainslie (Purism) <angus@akkea.ca>
> wrote:
>
>> +/ {
>> + model = "Purism Librem 5 devkit 1.0";
>> + compatible = "fsl,librem5-devkit", "fsl,imx8mq";
>
> This board is not manufactured by FSL/NXP, so it should be
> "purism,librem5-devkit", "fsl,imx8mq" instead.
>
> You should also add an entry for the purism vendor entry in
> Documentation/devicetree/bindings/vendor-prefixes.txt in a separate
> patch.
>
Thanks I'll add it in there.
>> +
>> + chosen {
>> + stdout-path = &uart1;
>> + };
>> +
>> + reg_usdhc2_vmmc: regulator-vsd-3v3 {
>
> The usual format would be:
>
> reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
>
Ok
>
>> + compatible = "regulator-fixed";
>> + regulator-name = "VSD_3V3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + regulator-always-on;
>
> Always on? It would be better to pass this regulator inside the mmc
> node.
>
This GPIO is a #disable line for the WLAN and if it goes low the module
doesn't recover. Until we get the WLAN driver working after disable it's
best to leave it always on.
>> + };
>> +
>> + reg_pwr_en: pwr_en {
>
> reg_pwr_en: regulator-pwr-en {
>
Ok
>> + compatible = "regulator-fixed";
>> + regulator-name = "PWR_EN";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + regulator-always-on;
>
> Same here. No need for "regulator-always-on" as it is controlled by
> the gyroscope.
>
This controls a regulator that feeds 80% of the peripherals on the board
and we don't have all of the drivers in the devicetree yet. Shutting
this off would during runtime would break the board so for now it needs
to stay always on.
>> +&fec1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_fec1>;
>> + phy-mode = "rgmii-id";
>> + phy-handle = <ðphy0>;
>> + fsl,magic-packet;
>> + status = "okay";
>> + phy-supply = <®_pwr_en>;
>> +
>> + mdio {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + ethphy0: ethernet-phy@0 {
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + reg = <1>;
>
> You pass @0 and use reg = <1>, which is a mismatch. Building it with
> W=1 would have warned you about this mismatch.
>
Thanks I'll fix that
>> + at803x,led-act-blind-workaround;
>> + at803x,eee-disabled;
>> + power-supply = <®_pwr_en>;
>> + };
>> + };
>> +};
>> +
>> +&iomuxc {
>> + imx8m-som {
>
> No need for this imx8m-som level.
>
>
>> + pinctrl_nc: ncgrp {
>
> Not a very descriptive naming.
>
Ok , this was my list of not connected pins but it should be removed.
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x00
>> + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL
>> 0x4000007f
>> + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA
>> 0x4000007f
>> + >;
>> + };
>> +
>> + pinctrl_up: upgrp {
>
> Same here. Also, this is not used. Please remove it.
>
Ok
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2
>> 0x00
>> + >;
>> + };
>> +
>> + pinctrl_csi1: csi1grp {
>
> This is not used at the moment. Please remove it and re-add it when
> CSI gets supported.
>
Ok
>> + fsl,pins = <
>> + /* CSI_nRST */
>> + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6
>> 0x11
>> + /* CSI_PWDN */
>> + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7
>> 0x19
>> + /* CLK01 */
>> + MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1
>> 0x19
>> + >;
>> + };
>> +
>> + pinctrl_pwr_en: pwr_engrp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8
>> 0x06
>> + >;
>> + };
>> +
>> + pinctrl_wwan: wwan_grp {
>
> Not used. Please remove this one and all unused pinctrl nodes.
>
This one should have been used but I'll go through and checked the rest
as well.
>> +&i2c1 {
>> + clock-frequency = <400000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c1>;
>> + status = "okay";
>> +
>> + pmic: bd71837@4b {
>
> Node names should be generic: pmic@4b
>
>> + typec_ptn5100: ptn5110@52 {
>
> Same here.
>
Ok
>> + charger: charger@6b { /* bq25896 */
>> + compatible = "ti,bq25890";
>> + reg = <0x6b>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_charger>;
>> + interrupt-parent = <&gpio3>;
>> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
>> + ti,battery-regulation-voltage = <4192000>; // 4.192V
>> + ti,charge-current = <1600000>; // 1.6 A
>> + ti,termination-current = <66000>; // 66mA
>> + ti,precharge-current = <1300000>; // 1.3A
>> + ti,minimum-sys-voltage = <2750000>; // 2.75V
>> + ti,boost-voltage = <5000000>; // 5V
>> + ti,boost-max-current = <50000>; // 50mA
>
> No // style comments, please/
>
Ok
>> +&i2c3 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c3>, <&pinctrl_imu>;
>> + status = "okay";
>> +
>> + lsm9d: lsm9d@6a {
>> + compatible = "st,lsm9ds1-gyro";
>
> I don't find this binding.
>
Thanks
>> + reg = <0x6a>;
>> + interrupt-parent = <&gpio3>;
>> + interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
>> + power-supply = <®_pwr_en>;
>> + };
>> +};
>
>> +&uart4 { /* BT */
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
>> + fsl,uart-has-rtscts;
>
> uart-has-rtscts is preferred.
>
>> + /* resets = <&modem_reset>; */
>
> Please remove this line instead of commenting it out.
Ok
Thanks
Angus
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit
2019-03-11 23:46 ` [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the " Angus Ainslie (Purism)
2019-03-12 0:10 ` Fabio Estevam
@ 2019-03-12 17:59 ` Guido Günther
2019-03-12 18:59 ` Angus Ainslie
2019-03-13 19:06 ` Rob Herring
2 siblings, 1 reply; 14+ messages in thread
From: Guido Günther @ 2019-03-12 17:59 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Mark Rutland, Rob Herring, Shawn Guo, Fabio Estevam, kernel,
Lucas Stach, abel.vesa, daniel.baluta, linux-imx, devicetree,
linux-kernel
Hi,
On Mon, Mar 11, 2019 at 04:46:53PM -0700, Angus Ainslie (Purism) wrote:
> This is the development kit for the Librem 5. The current level of support
> yields a working console and is able to boot userspace from the network
> or eMMC.
>
> Additional subsystems that are active :
>
> - Both USB ports
> - SD card socket
> - WWAN modem
Why not add the LCD backlight and the touch controller as well?
Cheers,
-- Guido
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
> ---
> .../dts/freescale/imx8mq-librem5-devkit.dts | 804 ++++++++++++++++++
> 1 file changed, 804 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> new file mode 100644
> index 000000000000..da9221c4200c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> @@ -0,0 +1,804 @@
> +/* SPDX-License-Identifier: GPL-2.0+
> + *
> + * Copyright 2018-2019 Purism SPC
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mq.dtsi"
> +#include "dt-bindings/usb/pd.h"
> +
> +/ {
> + model = "Purism Librem 5 devkit 1.0";
> + compatible = "fsl,librem5-devkit", "fsl,imx8mq";
> +
> + chosen {
> + stdout-path = &uart1;
> + };
> +
> + reg_usdhc2_vmmc: regulator-vsd-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "VSD_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + };
> +
> + reg_pwr_en: pwr_en {
> + compatible = "regulator-fixed";
> + regulator-name = "PWR_EN";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + };
> +
> + pmic_osc: pmic_osc {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "pmic_osc";
> + };
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + fsl,magic-packet;
> + status = "okay";
> + phy-supply = <®_pwr_en>;
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + at803x,led-act-blind-workaround;
> + at803x,eee-disabled;
> + power-supply = <®_pwr_en>;
> + };
> + };
> +};
> +
> +&iomuxc {
> + imx8m-som {
> + pinctrl_nc: ncgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x00
> + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
> + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
> + >;
> + };
> +
> + pinctrl_up: upgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x00
> + >;
> + };
> +
> + pinctrl_csi1: csi1grp {
> + fsl,pins = <
> + /* CSI_nRST */
> + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x11
> + /* CSI_PWDN */
> + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
> + /* CLK01 */
> + MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x19
> + >;
> + };
> +
> + pinctrl_pwr_en: pwr_engrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
> + >;
> + };
> +
> + pinctrl_wwan: wwan_grp {
> + fsl,pins = <
> + /* nWWAN_DISABLE */
> + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09
> + /* nWoWWAN */
> + MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80
> + /* WWAN_RESET */
> + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
> + >;
> + };
> +
> + pinctrl_dsi: dsigrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x16
> + >;
> + };
> +
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
> + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
> + >;
> + };
> +
> + pinctrl_hdmi: hdmigrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x16
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
> + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000001f
> + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000001f
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
> + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
> + >;
> + };
> +
> + pinctrl_pcie0: pcie0grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
> + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
> + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16
> + >;
> + };
> +
> + pinctrl_pcie1: pcie1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x16
> + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
> + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16
> + >;
> + };
> +
> +
> + pinctrl_typec: typecgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
> + MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
> + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
> + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
> + MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
> + MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
> + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
> + MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
> + MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
> + MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
> + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
> + >;
> + };
> +
> + pinctrl_bt: btgrp {
> + fsl,pins = <
> + /* nBT_DISABLE */
> + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
> + /* BT_HOST_WAKE */
> + MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10
> + >;
> + };
> +
> + pinctrl_modem_reset: modem_reset {
> + fsl,pins = <
> + /* WWAN_RESET */
> + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> + /* WIFI_WAKE */
> + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
> + >;
> + };
> +
> + pinctrl_sai2: sai2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
> + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
> + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
> + MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
> + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
> + >;
> + };
> +
> + pinctrl_sai5: sai5grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
> + MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
> + MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
> + MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
> + >;
> + };
> +
> + pinctrl_sai6: sai6grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
> + MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
> + MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
> + MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
> + >;
> + };
> +
> + pinctrl_spdif1: spdif1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
> + MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1 {
> + fsl,pins = <
> + /* DSI_BL_PWM */
> + MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6
> + >;
> + };
> +
> + pinctrl_micsel: micselgrp {
> + fsl,pins = <
> + /* mic sel */
> + MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6
> + >;
> + };
> +
> + pinctrl_haptic: hapticgrp {
> + fsl,pins = <
> + /* nHAPTIC */
> + MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0xc6
> + >;
> + };
> +
> + pinctrl_mute: mute {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x86 /* MUTE */
> + >;
> + };
> +
> + pinctrl_pwm4: pwm4 {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0xc6
> + >;
> + };
> +
> + pinctrl_prox: prox_nint {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80
> + >;
> + };
> +
> + pinctrl_charger: charger_nirq {
> + fsl,pins = <
> + /* CHRG_nINT */
> + MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80
> + >;
> + };
> +
> + pinctrl_rtc: rtcirq {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80
> + >;
> + };
> +
> + pinctrl_pmic: pmic_int {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80
> + >;
> + };
> +
> + pinctrl_spi1: spi1 {
> + fsl,pins = <
> + MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x0f
> + MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x0f
> + MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x0f
> + MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x09
> + >;
> + };
> +
> + pinctrl_imu: imugrp {
> + fsl,pins = <
> + /* IMU_INT */
> + MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8
> + >;
> + };
> +
> + pinctrl_gpio_leds: gpioleds {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
> + >;
> + };
> +
> + pinctrl_gpio_keys: gpiokeys {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
> + MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
> + /* HP_DET */
> + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180
> + >;
> + };
> +
> + pinctrl_goodix_ts: gt5688 {
> + fsl,pins = <
> + /* TOUCH INT */
> + MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16
> + /* TOUCH RST */
> + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
> + >;
> + };
> +
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + pmic: bd71837@4b {
> + reg = <0x4b>;
> + compatible = "rohm,bd71837";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + clocks = <&pmic_osc>;
> + clock-names = "osc";
> + clock-output-names = "pmic_clk";
> + interrupt-parent = <&gpio1>;
> + interrupts = <3 GPIO_ACTIVE_LOW>;
> + interrupt-names = "irq";
> + rohm,reset-snvs-powered;
> +
> + gpo {
> + /* 0b0000_1100 all gpos with cmos output mode */
> + rohm,drv = <0x0C>;
> + };
> +
> + regulators {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + buck1_reg: BUCK1 {
> + reg = <0>;
> + regulator-name = "buck1";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <1250>;
> + rohm,dvs-run-voltage = <900000>;
> + rohm,dvs-idle-voltage = <850000>;
> + rohm,dvs-suspend-voltage = <800000>;
> + };
> +
> + buck2_reg: BUCK2 {
> + reg = <1>;
> + regulator-name = "buck2";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <1250>;
> + rohm,dvs-run-voltage = <1000000>;
> + rohm,dvs-idle-voltage = <900000>;
> + };
> +
> + buck3_reg: BUCK3 {
> + reg = <2>;
> + regulator-name = "buck3";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-boot-on;
> + rohm,dvs-run-voltage = <1000000>;
> + };
> +
> + buck4_reg: BUCK4 {
> + reg = <3>;
> + regulator-name = "buck4";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-boot-on;
> + rohm,dvs-run-voltage = <1000000>;
> + };
> +
> + buck5_reg: BUCK5 {
> + reg = <4>;
> + regulator-name = "buck5";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck6_reg: BUCK6 {
> + reg = <5>;
> + regulator-name = "buck6";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck7_reg: BUCK7 {
> + reg = <6>;
> + regulator-name = "buck7";
> + regulator-min-microvolt = <1605000>;
> + regulator-max-microvolt = <1995000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck8_reg: BUCK8 {
> + reg = <7>;
> + regulator-name = "buck8";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1400000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo1_reg: LDO1 {
> + reg = <8>;
> + regulator-name = "ldo1";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo2_reg: LDO2 {
> + reg = <9>;
> + regulator-name = "ldo2";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo3_reg: LDO3 {
> + reg = <10>;
> + regulator-name = "ldo3";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo4_reg: LDO4 {
> + reg = <11>;
> + regulator-name = "ldo4";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo5_reg: LDO5 {
> + reg = <12>;
> + regulator-name = "ldo5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo6_reg: LDO6 {
> + reg = <13>;
> + regulator-name = "ldo6";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo7_reg: LDO7 {
> + reg = <14>;
> + regulator-name = "ldo7";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + typec_ptn5100: ptn5110@52 {
> + compatible = "nxp,ptn5110";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_typec>;
> + reg = <0x52>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
> + ss-sel-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
> + usb_con: connector {
> + compatible = "usb-c-connector";
> + label = "USB-C";
> + data-role = "dual";
> + power-role = "dual";
> + try-power-role = "sink";
> + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
> + sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
> + PDO_VAR(5000, 12000, 2000)>;
> + op-sink-microwatt = <10000000>;
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + usb_con_hs: endpoint {
> + remote-endpoint = <&typec_hs>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + usb_con_ss: endpoint {
> + remote-endpoint = <&typec_ss>;
> + };
> + };
> + };
> + };
> +
> + };
> +
> + charger: charger@6b { /* bq25896 */
> + compatible = "ti,bq25890";
> + reg = <0x6b>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_charger>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> + ti,battery-regulation-voltage = <4192000>; // 4.192V
> + ti,charge-current = <1600000>; // 1.6 A
> + ti,termination-current = <66000>; // 66mA
> + ti,precharge-current = <1300000>; // 1.3A
> + ti,minimum-sys-voltage = <2750000>; // 2.75V
> + ti,boost-voltage = <5000000>; // 5V
> + ti,boost-max-current = <50000>; // 50mA
> + };
> +
> + rtc@68 {
> + pinctrl-names = "default";
> + compatible = "microcrystal,rv4162";
> + reg = <0x68>;
> + pinctrl-0 = <&pinctrl_rtc>;
> + interrupt-parent = <&gpio4>;
> + interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "disabled";
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>, <&pinctrl_imu>;
> + status = "okay";
> +
> + lsm9d: lsm9d@6a {
> + compatible = "st,lsm9ds1-gyro";
> + reg = <0x6a>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
> + power-supply = <®_pwr_en>;
> + };
> +};
> +
> +&usb3_phy0 {
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + typec_hs: endpoint {
> + remote-endpoint = <&usb_con_hs>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + typec_ss: endpoint {
> + remote-endpoint = <&usb_con_ss>;
> + };
> + };
> +};
> +
> +&usb_dwc3_0 {
> + status = "okay";
> + extcon = <&typec_ptn5100>;
> + dr_mode = "otg";
> +};
> +
> +&usb3_phy1 {
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +};
> +
> +&usb_dwc3_1 {
> + status = "okay";
> + dr_mode = "host";
> +};
> +
> +&uart1 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + status = "okay";
> +};
> +
> +&uart4 { /* BT */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
> + fsl,uart-has-rtscts;
> + /* resets = <&modem_reset>; */
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit
2019-03-12 17:59 ` Guido Günther
@ 2019-03-12 18:59 ` Angus Ainslie
2019-03-13 17:57 ` Guido Günther
0 siblings, 1 reply; 14+ messages in thread
From: Angus Ainslie @ 2019-03-12 18:59 UTC (permalink / raw)
To: Guido Günther
Cc: Mark Rutland, Rob Herring, Shawn Guo, Fabio Estevam, kernel,
Lucas Stach, abel.vesa, daniel.baluta, linux-imx, devicetree,
linux-kernel
On 2019-03-12 10:59, Guido Günther wrote:
> Hi,
> On Mon, Mar 11, 2019 at 04:46:53PM -0700, Angus Ainslie (Purism) wrote:
>> This is the development kit for the Librem 5. The current level of
>> support
>> yields a working console and is able to boot userspace from the
>> network
>> or eMMC.
>>
>> Additional subsystems that are active :
>>
>> - Both USB ports
>> - SD card socket
>> - WWAN modem
>
> Why not add the LCD backlight and the touch controller as well?
I planned to leave those out until we have the display subsystem working
on mainline.
Angus
> Cheers,
> -- Guido
>
>>
>> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
>> ---
>> .../dts/freescale/imx8mq-librem5-devkit.dts | 804
>> ++++++++++++++++++
>> 1 file changed, 804 insertions(+)
>> create mode 100644
>> arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
>>
>> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
>> b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
>> new file mode 100644
>> index 000000000000..da9221c4200c
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
>> @@ -0,0 +1,804 @@
>> +/* SPDX-License-Identifier: GPL-2.0+
>> + *
>> + * Copyright 2018-2019 Purism SPC
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "imx8mq.dtsi"
>> +#include "dt-bindings/usb/pd.h"
>> +
>> +/ {
>> + model = "Purism Librem 5 devkit 1.0";
>> + compatible = "fsl,librem5-devkit", "fsl,imx8mq";
>> +
>> + chosen {
>> + stdout-path = &uart1;
>> + };
>> +
>> + reg_usdhc2_vmmc: regulator-vsd-3v3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "VSD_3V3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + regulator-always-on;
>> + };
>> +
>> + reg_pwr_en: pwr_en {
>> + compatible = "regulator-fixed";
>> + regulator-name = "PWR_EN";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
>> + enable-active-high;
>> + regulator-always-on;
>> + };
>> +
>> + pmic_osc: pmic_osc {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <32768>;
>> + clock-output-names = "pmic_osc";
>> + };
>> +};
>> +
>> +&fec1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_fec1>;
>> + phy-mode = "rgmii-id";
>> + phy-handle = <ðphy0>;
>> + fsl,magic-packet;
>> + status = "okay";
>> + phy-supply = <®_pwr_en>;
>> +
>> + mdio {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + ethphy0: ethernet-phy@0 {
>> + compatible = "ethernet-phy-ieee802.3-c22";
>> + reg = <1>;
>> + at803x,led-act-blind-workaround;
>> + at803x,eee-disabled;
>> + power-supply = <®_pwr_en>;
>> + };
>> + };
>> +};
>> +
>> +&iomuxc {
>> + imx8m-som {
>> + pinctrl_nc: ncgrp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x00
>> + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
>> + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
>> + >;
>> + };
>> +
>> + pinctrl_up: upgrp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x00
>> + >;
>> + };
>> +
>> + pinctrl_csi1: csi1grp {
>> + fsl,pins = <
>> + /* CSI_nRST */
>> + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x11
>> + /* CSI_PWDN */
>> + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
>> + /* CLK01 */
>> + MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x19
>> + >;
>> + };
>> +
>> + pinctrl_pwr_en: pwr_engrp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
>> + >;
>> + };
>> +
>> + pinctrl_wwan: wwan_grp {
>> + fsl,pins = <
>> + /* nWWAN_DISABLE */
>> + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09
>> + /* nWoWWAN */
>> + MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80
>> + /* WWAN_RESET */
>> + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
>> + >;
>> + };
>> +
>> + pinctrl_dsi: dsigrp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x16
>> + >;
>> + };
>> +
>> + pinctrl_fec1: fec1grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
>> + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
>> + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
>> + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
>> + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
>> + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
>> + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
>> + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
>> + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
>> + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
>> + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
>> + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
>> + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
>> + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>> + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
>> + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
>> + >;
>> + };
>> +
>> + pinctrl_hdmi: hdmigrp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x16
>> + >;
>> + };
>> +
>> + pinctrl_i2c1: i2c1grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
>> + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
>> + >;
>> + };
>> +
>> + pinctrl_i2c2: i2c2grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000001f
>> + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000001f
>> + >;
>> + };
>> +
>> + pinctrl_i2c3: i2c3grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
>> + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
>> + >;
>> + };
>> +
>> + pinctrl_pcie0: pcie0grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
>> + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
>> + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16
>> + >;
>> + };
>> +
>> + pinctrl_pcie1: pcie1grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x16
>> + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
>> + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16
>> + >;
>> + };
>> +
>> +
>> + pinctrl_typec: typecgrp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
>> + MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
>> + >;
>> + };
>> +
>> + pinctrl_uart1: uart1grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
>> + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
>> + >;
>> + };
>> +
>> + pinctrl_uart2: uart2grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
>> + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
>> + MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
>> + MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
>> + >;
>> + };
>> +
>> + pinctrl_uart3: uart3grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
>> + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
>> + >;
>> + };
>> +
>> + pinctrl_uart4: uart4grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
>> + MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
>> + MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
>> + MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
>> + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
>> + >;
>> + };
>> +
>> + pinctrl_bt: btgrp {
>> + fsl,pins = <
>> + /* nBT_DISABLE */
>> + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
>> + /* BT_HOST_WAKE */
>> + MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10
>> + >;
>> + };
>> +
>> + pinctrl_modem_reset: modem_reset {
>> + fsl,pins = <
>> + /* WWAN_RESET */
>> + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1: usdhc1grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
>> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
>> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
>> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
>> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
>> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
>> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
>> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
>> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
>> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
>> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
>> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_gpio: usdhc2grpgpio {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>> + /* WIFI_WAKE */
>> + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2: usdhc2grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
>> + >;
>> + };
>> +
>> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
>> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
>> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
>> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
>> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
>> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
>> + >;
>> + };
>> +
>> + pinctrl_sai2: sai2grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
>> + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
>> + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
>> + MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
>> + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
>> + >;
>> + };
>> +
>> + pinctrl_sai5: sai5grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
>> + MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
>> + MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
>> + MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
>> + >;
>> + };
>> +
>> + pinctrl_sai6: sai6grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
>> + MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
>> + MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
>> + MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
>> + >;
>> + };
>> +
>> + pinctrl_spdif1: spdif1grp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
>> + MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
>> + >;
>> + };
>> +
>> + pinctrl_wdog: wdoggrp {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>> + >;
>> + };
>> +
>> + pinctrl_pwm1: pwm1 {
>> + fsl,pins = <
>> + /* DSI_BL_PWM */
>> + MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6
>> + >;
>> + };
>> +
>> + pinctrl_micsel: micselgrp {
>> + fsl,pins = <
>> + /* mic sel */
>> + MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6
>> + >;
>> + };
>> +
>> + pinctrl_haptic: hapticgrp {
>> + fsl,pins = <
>> + /* nHAPTIC */
>> + MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0xc6
>> + >;
>> + };
>> +
>> + pinctrl_mute: mute {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x86 /* MUTE */
>> + >;
>> + };
>> +
>> + pinctrl_pwm4: pwm4 {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0xc6
>> + >;
>> + };
>> +
>> + pinctrl_prox: prox_nint {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80
>> + >;
>> + };
>> +
>> + pinctrl_charger: charger_nirq {
>> + fsl,pins = <
>> + /* CHRG_nINT */
>> + MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80
>> + >;
>> + };
>> +
>> + pinctrl_rtc: rtcirq {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80
>> + >;
>> + };
>> +
>> + pinctrl_pmic: pmic_int {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80
>> + >;
>> + };
>> +
>> + pinctrl_spi1: spi1 {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x0f
>> + MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x0f
>> + MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x0f
>> + MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x09
>> + >;
>> + };
>> +
>> + pinctrl_imu: imugrp {
>> + fsl,pins = <
>> + /* IMU_INT */
>> + MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8
>> + >;
>> + };
>> +
>> + pinctrl_gpio_leds: gpioleds {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
>> + >;
>> + };
>> +
>> + pinctrl_gpio_keys: gpiokeys {
>> + fsl,pins = <
>> + MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
>> + MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
>> + /* HP_DET */
>> + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180
>> + >;
>> + };
>> +
>> + pinctrl_goodix_ts: gt5688 {
>> + fsl,pins = <
>> + /* TOUCH INT */
>> + MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16
>> + /* TOUCH RST */
>> + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
>> + >;
>> + };
>> +
>> + };
>> +};
>> +
>> +&i2c1 {
>> + clock-frequency = <400000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c1>;
>> + status = "okay";
>> +
>> + pmic: bd71837@4b {
>> + reg = <0x4b>;
>> + compatible = "rohm,bd71837";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_pmic>;
>> + clocks = <&pmic_osc>;
>> + clock-names = "osc";
>> + clock-output-names = "pmic_clk";
>> + interrupt-parent = <&gpio1>;
>> + interrupts = <3 GPIO_ACTIVE_LOW>;
>> + interrupt-names = "irq";
>> + rohm,reset-snvs-powered;
>> +
>> + gpo {
>> + /* 0b0000_1100 all gpos with cmos output mode */
>> + rohm,drv = <0x0C>;
>> + };
>> +
>> + regulators {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + buck1_reg: BUCK1 {
>> + reg = <0>;
>> + regulator-name = "buck1";
>> + regulator-min-microvolt = <700000>;
>> + regulator-max-microvolt = <1300000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + regulator-ramp-delay = <1250>;
>> + rohm,dvs-run-voltage = <900000>;
>> + rohm,dvs-idle-voltage = <850000>;
>> + rohm,dvs-suspend-voltage = <800000>;
>> + };
>> +
>> + buck2_reg: BUCK2 {
>> + reg = <1>;
>> + regulator-name = "buck2";
>> + regulator-min-microvolt = <700000>;
>> + regulator-max-microvolt = <1300000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + regulator-ramp-delay = <1250>;
>> + rohm,dvs-run-voltage = <1000000>;
>> + rohm,dvs-idle-voltage = <900000>;
>> + };
>> +
>> + buck3_reg: BUCK3 {
>> + reg = <2>;
>> + regulator-name = "buck3";
>> + regulator-min-microvolt = <700000>;
>> + regulator-max-microvolt = <1300000>;
>> + regulator-boot-on;
>> + rohm,dvs-run-voltage = <1000000>;
>> + };
>> +
>> + buck4_reg: BUCK4 {
>> + reg = <3>;
>> + regulator-name = "buck4";
>> + regulator-min-microvolt = <700000>;
>> + regulator-max-microvolt = <1300000>;
>> + regulator-boot-on;
>> + rohm,dvs-run-voltage = <1000000>;
>> + };
>> +
>> + buck5_reg: BUCK5 {
>> + reg = <4>;
>> + regulator-name = "buck5";
>> + regulator-min-microvolt = <700000>;
>> + regulator-max-microvolt = <1350000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + buck6_reg: BUCK6 {
>> + reg = <5>;
>> + regulator-name = "buck6";
>> + regulator-min-microvolt = <3000000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + buck7_reg: BUCK7 {
>> + reg = <6>;
>> + regulator-name = "buck7";
>> + regulator-min-microvolt = <1605000>;
>> + regulator-max-microvolt = <1995000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + buck8_reg: BUCK8 {
>> + reg = <7>;
>> + regulator-name = "buck8";
>> + regulator-min-microvolt = <800000>;
>> + regulator-max-microvolt = <1400000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + ldo1_reg: LDO1 {
>> + reg = <8>;
>> + regulator-name = "ldo1";
>> + regulator-min-microvolt = <3000000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + ldo2_reg: LDO2 {
>> + reg = <9>;
>> + regulator-name = "ldo2";
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <900000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + ldo3_reg: LDO3 {
>> + reg = <10>;
>> + regulator-name = "ldo3";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + ldo4_reg: LDO4 {
>> + reg = <11>;
>> + regulator-name = "ldo4";
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + ldo5_reg: LDO5 {
>> + reg = <12>;
>> + regulator-name = "ldo5";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + ldo6_reg: LDO6 {
>> + reg = <13>;
>> + regulator-name = "ldo6";
>> + regulator-min-microvolt = <900000>;
>> + regulator-max-microvolt = <1800000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> +
>> + ldo7_reg: LDO7 {
>> + reg = <14>;
>> + regulator-name = "ldo7";
>> + regulator-min-microvolt = <1800000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-boot-on;
>> + regulator-always-on;
>> + };
>> + };
>> + };
>> +
>> + typec_ptn5100: ptn5110@52 {
>> + compatible = "nxp,ptn5110";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_typec>;
>> + reg = <0x52>;
>> + interrupt-parent = <&gpio3>;
>> + interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
>> + ss-sel-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
>> + usb_con: connector {
>> + compatible = "usb-c-connector";
>> + label = "USB-C";
>> + data-role = "dual";
>> + power-role = "dual";
>> + try-power-role = "sink";
>> + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
>> + sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
>> + PDO_VAR(5000, 12000, 2000)>;
>> + op-sink-microwatt = <10000000>;
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + port@0 {
>> + reg = <0>;
>> + usb_con_hs: endpoint {
>> + remote-endpoint = <&typec_hs>;
>> + };
>> + };
>> + port@1 {
>> + reg = <1>;
>> + usb_con_ss: endpoint {
>> + remote-endpoint = <&typec_ss>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + };
>> +
>> + charger: charger@6b { /* bq25896 */
>> + compatible = "ti,bq25890";
>> + reg = <0x6b>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_charger>;
>> + interrupt-parent = <&gpio3>;
>> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
>> + ti,battery-regulation-voltage = <4192000>; // 4.192V
>> + ti,charge-current = <1600000>; // 1.6 A
>> + ti,termination-current = <66000>; // 66mA
>> + ti,precharge-current = <1300000>; // 1.3A
>> + ti,minimum-sys-voltage = <2750000>; // 2.75V
>> + ti,boost-voltage = <5000000>; // 5V
>> + ti,boost-max-current = <50000>; // 50mA
>> + };
>> +
>> + rtc@68 {
>> + pinctrl-names = "default";
>> + compatible = "microcrystal,rv4162";
>> + reg = <0x68>;
>> + pinctrl-0 = <&pinctrl_rtc>;
>> + interrupt-parent = <&gpio4>;
>> + interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
>> + };
>> +};
>> +
>> +&i2c2 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c2>;
>> + status = "disabled";
>> +};
>> +
>> +&i2c3 {
>> + clock-frequency = <100000>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_i2c3>, <&pinctrl_imu>;
>> + status = "okay";
>> +
>> + lsm9d: lsm9d@6a {
>> + compatible = "st,lsm9ds1-gyro";
>> + reg = <0x6a>;
>> + interrupt-parent = <&gpio3>;
>> + interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
>> + power-supply = <®_pwr_en>;
>> + };
>> +};
>> +
>> +&usb3_phy0 {
>> + status = "okay";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + port@0 {
>> + reg = <0>;
>> + typec_hs: endpoint {
>> + remote-endpoint = <&usb_con_hs>;
>> + };
>> + };
>> + port@1 {
>> + reg = <1>;
>> + typec_ss: endpoint {
>> + remote-endpoint = <&usb_con_ss>;
>> + };
>> + };
>> +};
>> +
>> +&usb_dwc3_0 {
>> + status = "okay";
>> + extcon = <&typec_ptn5100>;
>> + dr_mode = "otg";
>> +};
>> +
>> +&usb3_phy1 {
>> + status = "okay";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +};
>> +
>> +&usb_dwc3_1 {
>> + status = "okay";
>> + dr_mode = "host";
>> +};
>> +
>> +&uart1 { /* console */
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart1>;
>> + status = "okay";
>> +};
>> +
>> +&uart3 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart3>;
>> + status = "okay";
>> +};
>> +
>> +&uart4 { /* BT */
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
>> + fsl,uart-has-rtscts;
>> + /* resets = <&modem_reset>; */
>> + status = "okay";
>> +};
>> +
>> +&usdhc1 {
>> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> + pinctrl-0 = <&pinctrl_usdhc1>;
>> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
>> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
>> + bus-width = <8>;
>> + non-removable;
>> + status = "okay";
>> +};
>> +
>> +&wdog1 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_wdog>;
>> + fsl,ext-reset-output;
>> + status = "okay";
>> +};
>> +
>> --
>> 2.17.1
>>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit
2019-03-12 18:59 ` Angus Ainslie
@ 2019-03-13 17:57 ` Guido Günther
0 siblings, 0 replies; 14+ messages in thread
From: Guido Günther @ 2019-03-13 17:57 UTC (permalink / raw)
To: Angus Ainslie
Cc: Mark Rutland, Rob Herring, Shawn Guo, Fabio Estevam, kernel,
Lucas Stach, abel.vesa, daniel.baluta, linux-imx, devicetree,
linux-kernel
Hi,
On Tue, Mar 12, 2019 at 11:59:10AM -0700, Angus Ainslie wrote:
> On 2019-03-12 10:59, Guido Günther wrote:
> > Hi,
> > On Mon, Mar 11, 2019 at 04:46:53PM -0700, Angus Ainslie (Purism) wrote:
> > > This is the development kit for the Librem 5. The current level of
> > > support
> > > yields a working console and is able to boot userspace from the
> > > network
> > > or eMMC.
> > >
> > > Additional subsystems that are active :
> > >
> > > - Both USB ports
> > > - SD card socket
> > > - WWAN modem
> >
> > Why not add the LCD backlight and the touch controller as well?
>
> I planned to leave those out until we have the display subsystem working on
> mainline.
I wouldn't leave out anything with known working drivers.
Cheers,
-- Guido
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the Librem5 devkit
2019-03-11 23:46 ` [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the " Angus Ainslie (Purism)
2019-03-12 0:10 ` Fabio Estevam
2019-03-12 17:59 ` Guido Günther
@ 2019-03-13 19:06 ` Rob Herring
2 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2019-03-13 19:06 UTC (permalink / raw)
To: Angus Ainslie (Purism)
Cc: Mark Rutland, Shawn Guo, Fabio Estevam, Sascha Hauer,
Lucas Stach, Abel Vesa, Daniel Baluta, agx, NXP Linux Team,
devicetree, linux-kernel
On Mon, Mar 11, 2019 at 6:47 PM Angus Ainslie (Purism) <angus@akkea.ca> wrote:
>
> This is the development kit for the Librem 5. The current level of support
> yields a working console and is able to boot userspace from the network
> or eMMC.
>
> Additional subsystems that are active :
>
> - Both USB ports
> - SD card socket
> - WWAN modem
>
> Signed-off-by: Angus Ainslie (Purism) <angus@akkea.ca>
> ---
> .../dts/freescale/imx8mq-librem5-devkit.dts | 804 ++++++++++++++++++
> 1 file changed, 804 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> new file mode 100644
> index 000000000000..da9221c4200c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> @@ -0,0 +1,804 @@
> +/* SPDX-License-Identifier: GPL-2.0+
> + *
> + * Copyright 2018-2019 Purism SPC
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8mq.dtsi"
> +#include "dt-bindings/usb/pd.h"
> +
> +/ {
> + model = "Purism Librem 5 devkit 1.0";
> + compatible = "fsl,librem5-devkit", "fsl,imx8mq";
> +
> + chosen {
> + stdout-path = &uart1;
> + };
> +
> + reg_usdhc2_vmmc: regulator-vsd-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "VSD_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + };
> +
> + reg_pwr_en: pwr_en {
regulator-pwr-en {
> + compatible = "regulator-fixed";
> + regulator-name = "PWR_EN";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + regulator-always-on;
> + };
> +
> + pmic_osc: pmic_osc {
Don't use '_' in node names.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "pmic_osc";
> + };
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + fsl,magic-packet;
> + status = "okay";
> + phy-supply = <®_pwr_en>;
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + at803x,led-act-blind-workaround;
> + at803x,eee-disabled;
These are not documented. The format is vendor,property-name and
at803x is not a vendor.
IIRC, there's a common property for eee-disabled.
> + power-supply = <®_pwr_en>;
> + };
> + };
> +};
> +
> +&iomuxc {
> + imx8m-som {
> + pinctrl_nc: ncgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0x00
> + MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
> + MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
> + >;
> + };
> +
> + pinctrl_up: upgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0x00
> + >;
> + };
> +
> + pinctrl_csi1: csi1grp {
> + fsl,pins = <
> + /* CSI_nRST */
> + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x11
> + /* CSI_PWDN */
> + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
> + /* CLK01 */
> + MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x19
> + >;
> + };
> +
> + pinctrl_pwr_en: pwr_engrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x06
> + >;
> + };
> +
> + pinctrl_wwan: wwan_grp {
> + fsl,pins = <
> + /* nWWAN_DISABLE */
> + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x09
> + /* nWoWWAN */
> + MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x80
> + /* WWAN_RESET */
> + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
> + >;
> + };
> +
> + pinctrl_dsi: dsigrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13 0x16
> + >;
> + };
> +
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
> + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
> + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x1f
> + >;
> + };
> +
> + pinctrl_hdmi: hdmigrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x16
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000001f
> + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000001f
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000001f
> + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000001f
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000001f
> + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000001f
> + >;
> + };
> +
> + pinctrl_pcie0: pcie0grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16
> + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
> + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x16
> + >;
> + };
> +
> + pinctrl_pcie1: pcie1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x16
> + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
> + MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x16
> + >;
> + };
> +
> +
> + pinctrl_typec: typecgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12 0x16
> + MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x80
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
> + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
> + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
> + MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
> + MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49
> + MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x49
> + MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x49
> + MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x49
> + MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x49
> + MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x49
> + >;
> + };
> +
> + pinctrl_bt: btgrp {
> + fsl,pins = <
> + /* nBT_DISABLE */
> + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x16
> + /* BT_HOST_WAKE */
> + MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x10
> + >;
> + };
> +
> + pinctrl_modem_reset: modem_reset {
> + fsl,pins = <
> + /* WWAN_RESET */
> + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
> + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
> + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
> + >;
> + };
> +
> + pinctrl_usdhc2_gpio: usdhc2grpgpio {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
> + /* WIFI_WAKE */
> + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd
> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd
> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd
> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
> + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
> + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcf
> + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcf
> + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcf
> + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcf
> + >;
> + };
> +
> + pinctrl_sai2: sai2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
> + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
> + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
> + MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
> + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
> + >;
> + };
> +
> + pinctrl_sai5: sai5grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6
> + MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6
> + MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6
> + MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6
> + >;
> + };
> +
> + pinctrl_sai6: sai6grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0 0xd6
> + MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC 0xd6
> + MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK 0xd6
> + MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0 0xd6
> + >;
> + };
> +
> + pinctrl_spdif1: spdif1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
> + MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> + >;
> + };
> +
> + pinctrl_pwm1: pwm1 {
> + fsl,pins = <
> + /* DSI_BL_PWM */
> + MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6
> + >;
> + };
> +
> + pinctrl_micsel: micselgrp {
> + fsl,pins = <
> + /* mic sel */
> + MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0xc6
> + >;
> + };
> +
> + pinctrl_haptic: hapticgrp {
> + fsl,pins = <
> + /* nHAPTIC */
> + MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT 0xc6
> + >;
> + };
> +
> + pinctrl_mute: mute {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3 0x86 /* MUTE */
> + >;
> + };
> +
> + pinctrl_pwm4: pwm4 {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT 0xc6
> + >;
> + };
> +
> + pinctrl_prox: prox_nint {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x80
> + >;
> + };
> +
> + pinctrl_charger: charger_nirq {
> + fsl,pins = <
> + /* CHRG_nINT */
> + MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x80
> + >;
> + };
> +
> + pinctrl_rtc: rtcirq {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x80
> + >;
> + };
> +
> + pinctrl_pmic: pmic_int {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x80
> + >;
> + };
> +
> + pinctrl_spi1: spi1 {
> + fsl,pins = <
> + MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x0f
> + MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x0f
> + MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x0f
> + MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x09
> + >;
> + };
> +
> + pinctrl_imu: imugrp {
> + fsl,pins = <
> + /* IMU_INT */
> + MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x8
> + >;
> + };
> +
> + pinctrl_gpio_leds: gpioleds {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16
> + >;
> + };
> +
> + pinctrl_gpio_keys: gpiokeys {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
> + MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22 0x16
> + /* HP_DET */
> + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x180
> + >;
> + };
> +
> + pinctrl_goodix_ts: gt5688 {
> + fsl,pins = <
> + /* TOUCH INT */
> + MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x16
> + /* TOUCH RST */
> + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
> + >;
> + };
> +
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + pmic: bd71837@4b {
> + reg = <0x4b>;
> + compatible = "rohm,bd71837";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + clocks = <&pmic_osc>;
> + clock-names = "osc";
> + clock-output-names = "pmic_clk";
> + interrupt-parent = <&gpio1>;
> + interrupts = <3 GPIO_ACTIVE_LOW>;
> + interrupt-names = "irq";
> + rohm,reset-snvs-powered;
> +
> + gpo {
> + /* 0b0000_1100 all gpos with cmos output mode */
> + rohm,drv = <0x0C>;
> + };
> +
> + regulators {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + buck1_reg: BUCK1 {
> + reg = <0>;
> + regulator-name = "buck1";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <1250>;
> + rohm,dvs-run-voltage = <900000>;
> + rohm,dvs-idle-voltage = <850000>;
> + rohm,dvs-suspend-voltage = <800000>;
> + };
> +
> + buck2_reg: BUCK2 {
> + reg = <1>;
> + regulator-name = "buck2";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <1250>;
> + rohm,dvs-run-voltage = <1000000>;
> + rohm,dvs-idle-voltage = <900000>;
> + };
> +
> + buck3_reg: BUCK3 {
> + reg = <2>;
> + regulator-name = "buck3";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-boot-on;
> + rohm,dvs-run-voltage = <1000000>;
> + };
> +
> + buck4_reg: BUCK4 {
> + reg = <3>;
> + regulator-name = "buck4";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-boot-on;
> + rohm,dvs-run-voltage = <1000000>;
> + };
> +
> + buck5_reg: BUCK5 {
> + reg = <4>;
> + regulator-name = "buck5";
> + regulator-min-microvolt = <700000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck6_reg: BUCK6 {
> + reg = <5>;
> + regulator-name = "buck6";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck7_reg: BUCK7 {
> + reg = <6>;
> + regulator-name = "buck7";
> + regulator-min-microvolt = <1605000>;
> + regulator-max-microvolt = <1995000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + buck8_reg: BUCK8 {
> + reg = <7>;
> + regulator-name = "buck8";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1400000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo1_reg: LDO1 {
> + reg = <8>;
> + regulator-name = "ldo1";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo2_reg: LDO2 {
> + reg = <9>;
> + regulator-name = "ldo2";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo3_reg: LDO3 {
> + reg = <10>;
> + regulator-name = "ldo3";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo4_reg: LDO4 {
> + reg = <11>;
> + regulator-name = "ldo4";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo5_reg: LDO5 {
> + reg = <12>;
> + regulator-name = "ldo5";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo6_reg: LDO6 {
> + reg = <13>;
> + regulator-name = "ldo6";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + ldo7_reg: LDO7 {
> + reg = <14>;
> + regulator-name = "ldo7";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> + };
> + };
> +
> + typec_ptn5100: ptn5110@52 {
> + compatible = "nxp,ptn5110";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_typec>;
> + reg = <0x52>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
> + ss-sel-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
Not documented.
> + usb_con: connector {
> + compatible = "usb-c-connector";
> + label = "USB-C";
> + data-role = "dual";
> + power-role = "dual";
> + try-power-role = "sink";
> + source-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)>;
> + sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_USB_COMM)
> + PDO_VAR(5000, 12000, 2000)>;
> + op-sink-microwatt = <10000000>;
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + usb_con_hs: endpoint {
> + remote-endpoint = <&typec_hs>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + usb_con_ss: endpoint {
> + remote-endpoint = <&typec_ss>;
> + };
> + };
> + };
> + };
> +
> + };
> +
> + charger: charger@6b { /* bq25896 */
> + compatible = "ti,bq25890";
> + reg = <0x6b>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_charger>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
> + ti,battery-regulation-voltage = <4192000>; // 4.192V
> + ti,charge-current = <1600000>; // 1.6 A
> + ti,termination-current = <66000>; // 66mA
> + ti,precharge-current = <1300000>; // 1.3A
> + ti,minimum-sys-voltage = <2750000>; // 2.75V
> + ti,boost-voltage = <5000000>; // 5V
> + ti,boost-max-current = <50000>; // 50mA
> + };
> +
> + rtc@68 {
> + pinctrl-names = "default";
> + compatible = "microcrystal,rv4162";
> + reg = <0x68>;
> + pinctrl-0 = <&pinctrl_rtc>;
> + interrupt-parent = <&gpio4>;
> + interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
> + };
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "disabled";
> +};
> +
> +&i2c3 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>, <&pinctrl_imu>;
> + status = "okay";
> +
> + lsm9d: lsm9d@6a {
gyroscope@6a
> + compatible = "st,lsm9ds1-gyro";
> + reg = <0x6a>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
> + power-supply = <®_pwr_en>;
> + };
> +};
> +
> +&usb3_phy0 {
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@0 {
> + reg = <0>;
> + typec_hs: endpoint {
> + remote-endpoint = <&usb_con_hs>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + typec_ss: endpoint {
> + remote-endpoint = <&usb_con_ss>;
> + };
> + };
> +};
> +
> +&usb_dwc3_0 {
> + status = "okay";
> + extcon = <&typec_ptn5100>;
> + dr_mode = "otg";
> +};
> +
> +&usb3_phy1 {
> + status = "okay";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +};
> +
> +&usb_dwc3_1 {
> + status = "okay";
> + dr_mode = "host";
> +};
> +
> +&uart1 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + status = "okay";
> +};
> +
> +&uart4 { /* BT */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_bt>;
> + fsl,uart-has-rtscts;
> + /* resets = <&modem_reset>; */
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + bus-width = <8>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2019-03-13 19:06 UTC | newest]
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2019-03-11 23:46 [PATCH 0/3] Add support for the Purism Librem5 devkit Angus Ainslie (Purism)
2019-03-11 23:46 ` [PATCH 1/3] arm64: dts: fsl: librem5: Add a device tree for the " Angus Ainslie (Purism)
2019-03-12 0:10 ` Fabio Estevam
2019-03-12 13:18 ` Angus Ainslie
2019-03-12 17:59 ` Guido Günther
2019-03-12 18:59 ` Angus Ainslie
2019-03-13 17:57 ` Guido Günther
2019-03-13 19:06 ` Rob Herring
2019-03-11 23:46 ` [PATCH 2/3] arm64: dts: fsl: Build the Librem5 devkit devicetree Angus Ainslie (Purism)
2019-03-12 0:10 ` Fabio Estevam
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2019-03-11 23:46 ` [PATCH 3/3] arm64: librem5-devkit: Add defconfig for the Librem5 devkit Angus Ainslie (Purism)
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