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* [PATCH] dmaengine: sprd: Support two-stage dma interrupt
@ 2022-09-30  5:53 Cixi Geng
  2022-09-30  6:42 ` Baolin Wang
  0 siblings, 1 reply; 3+ messages in thread
From: Cixi Geng @ 2022-09-30  5:53 UTC (permalink / raw)
  To: vkoul, orsonzhai, baolin.wang, zhang.lyra; +Cc: dmaengine, linux-kernel

From: Cixi Geng <cixi.geng1@unisoc.com>

Audio need to request Audio CP global dma interrupt, so Audio CP
DMA should support two-stage interrupt to adapte it.
It will occur interrupt when two-stage dma channel transfer done.

Signed-off-by: Cixi Geng <cixi.geng1@unisoc.com>
---
 drivers/dma/sprd-dma.c       |  8 ++++----
 include/linux/dma/sprd-dma.h | 12 ++++++++++++
 2 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c
index 474d3ba8ec9f..7a9ade422a00 100644
--- a/drivers/dma/sprd-dma.c
+++ b/drivers/dma/sprd-dma.c
@@ -441,7 +441,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
 		val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
 		val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
 		val |= SPRD_DMA_GLB_2STAGE_EN;
-		if (schan->int_type != SPRD_DMA_NO_INT)
+		if (schan->int_type != SPRD_DMA_SRC_CHN0_INT)
 			val |= SPRD_DMA_GLB_SRC_INT;
 
 		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
@@ -451,7 +451,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
 		val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
 		val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
 		val |= SPRD_DMA_GLB_2STAGE_EN;
-		if (schan->int_type != SPRD_DMA_NO_INT)
+		if (schan->int_type != SPRD_DMA_SRC_CHN1_INT)
 			val |= SPRD_DMA_GLB_SRC_INT;
 
 		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
@@ -461,7 +461,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
 		val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
 			SPRD_DMA_GLB_DEST_CHN_MASK;
 		val |= SPRD_DMA_GLB_2STAGE_EN;
-		if (schan->int_type != SPRD_DMA_NO_INT)
+		if (schan->int_type != SPRD_DMA_DST_CHN0_INT)
 			val |= SPRD_DMA_GLB_DEST_INT;
 
 		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
@@ -471,7 +471,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
 		val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
 			SPRD_DMA_GLB_DEST_CHN_MASK;
 		val |= SPRD_DMA_GLB_2STAGE_EN;
-		if (schan->int_type != SPRD_DMA_NO_INT)
+		if (schan->int_type != SPRD_DMA_DST_CHN1_INT)
 			val |= SPRD_DMA_GLB_DEST_INT;
 
 		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
diff --git a/include/linux/dma/sprd-dma.h b/include/linux/dma/sprd-dma.h
index d09c6f6f6da5..26de41d6d915 100644
--- a/include/linux/dma/sprd-dma.h
+++ b/include/linux/dma/sprd-dma.h
@@ -101,6 +101,14 @@ enum sprd_dma_req_mode {
  * is done.
  * @SPRD_DMA_CFGERR_INT: configure error interrupt when configuration is
  * incorrect.
+ * @SPRD_DMA_SRC_CHN0_INT: interrupt occurred when source channel0
+ * transfer is done.
+ * @SPRD_DMA_SRC_CHN1_INT: interrupt occurred when source channel1
+ * transfer is done.
+ * @SPRD_DMA_DST_CHN0_INT: interrupt occurred when destination channel0
+ * transfer is done.
+ * @SPRD_DMA_DST_CHN1_INT: interrupt occurred when destination channel1
+ * transfer is done.
  */
 enum sprd_dma_int_type {
 	SPRD_DMA_NO_INT,
@@ -112,6 +120,10 @@ enum sprd_dma_int_type {
 	SPRD_DMA_TRANS_BLK_INT,
 	SPRD_DMA_LIST_INT,
 	SPRD_DMA_CFGERR_INT,
+	SPRD_DMA_SRC_CHN0_INT,
+	SPRD_DMA_SRC_CHN1_INT,
+	SPRD_DMA_DST_CHN0_INT,
+	SPRD_DMA_DST_CHN1_INT,
 };
 
 /*
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread
* Re: [PATCH] dmaengine: sprd: Support two-stage dma interrupt
  2022-09-30  5:53 [PATCH] dmaengine: sprd: Support two-stage dma interrupt Cixi Geng
@ 2022-09-30  6:42 ` Baolin Wang
  2022-10-02 16:53   ` Cixi Geng
  0 siblings, 1 reply; 3+ messages in thread
From: Baolin Wang @ 2022-09-30  6:42 UTC (permalink / raw)
  To: Cixi Geng, vkoul, orsonzhai, zhang.lyra; +Cc: dmaengine, linux-kernel

Hi Cixi,

On 9/30/2022 1:53 PM, Cixi Geng wrote:
> From: Cixi Geng <cixi.geng1@unisoc.com>
> 
> Audio need to request Audio CP global dma interrupt, so Audio CP
> DMA should support two-stage interrupt to adapte it.
> It will occur interrupt when two-stage dma channel transfer done.

If the AP does not want the interrupt, why not just set SPRD_DMA_NO_INT?

I am struggling to understand the whole requirement, could you elaborate?

> 
> Signed-off-by: Cixi Geng <cixi.geng1@unisoc.com>
> ---
>   drivers/dma/sprd-dma.c       |  8 ++++----
>   include/linux/dma/sprd-dma.h | 12 ++++++++++++
>   2 files changed, 16 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c
> index 474d3ba8ec9f..7a9ade422a00 100644
> --- a/drivers/dma/sprd-dma.c
> +++ b/drivers/dma/sprd-dma.c
> @@ -441,7 +441,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
>   		val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
>   		val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
>   		val |= SPRD_DMA_GLB_2STAGE_EN;
> -		if (schan->int_type != SPRD_DMA_NO_INT)
> +		if (schan->int_type != SPRD_DMA_SRC_CHN0_INT)
>   			val |= SPRD_DMA_GLB_SRC_INT;

That does not make sense to me. If user configues the interrupt type as 
SPRD_DMA_NO_INT, the code will still enable the source interrupt.

If user configures the interrupt type as SPRD_DMA_SRC_CHN0_INT, you will 
disable the source interrupt? Confusing...

>   		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
> @@ -451,7 +451,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
>   		val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
>   		val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
>   		val |= SPRD_DMA_GLB_2STAGE_EN;
> -		if (schan->int_type != SPRD_DMA_NO_INT)
> +		if (schan->int_type != SPRD_DMA_SRC_CHN1_INT)
>   			val |= SPRD_DMA_GLB_SRC_INT;
>   
>   		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
> @@ -461,7 +461,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
>   		val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
>   			SPRD_DMA_GLB_DEST_CHN_MASK;
>   		val |= SPRD_DMA_GLB_2STAGE_EN;
> -		if (schan->int_type != SPRD_DMA_NO_INT)
> +		if (schan->int_type != SPRD_DMA_DST_CHN0_INT)
>   			val |= SPRD_DMA_GLB_DEST_INT;
>   
>   		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
> @@ -471,7 +471,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
>   		val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
>   			SPRD_DMA_GLB_DEST_CHN_MASK;
>   		val |= SPRD_DMA_GLB_2STAGE_EN;
> -		if (schan->int_type != SPRD_DMA_NO_INT)
> +		if (schan->int_type != SPRD_DMA_DST_CHN1_INT)
>   			val |= SPRD_DMA_GLB_DEST_INT;
>   
>   		sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
> diff --git a/include/linux/dma/sprd-dma.h b/include/linux/dma/sprd-dma.h
> index d09c6f6f6da5..26de41d6d915 100644
> --- a/include/linux/dma/sprd-dma.h
> +++ b/include/linux/dma/sprd-dma.h
> @@ -101,6 +101,14 @@ enum sprd_dma_req_mode {
>    * is done.
>    * @SPRD_DMA_CFGERR_INT: configure error interrupt when configuration is
>    * incorrect.
> + * @SPRD_DMA_SRC_CHN0_INT: interrupt occurred when source channel0
> + * transfer is done.
> + * @SPRD_DMA_SRC_CHN1_INT: interrupt occurred when source channel1
> + * transfer is done.
> + * @SPRD_DMA_DST_CHN0_INT: interrupt occurred when destination channel0
> + * transfer is done.
> + * @SPRD_DMA_DST_CHN1_INT: interrupt occurred when destination channel1
> + * transfer is done.
>    */
>   enum sprd_dma_int_type {
>   	SPRD_DMA_NO_INT,
> @@ -112,6 +120,10 @@ enum sprd_dma_int_type {
>   	SPRD_DMA_TRANS_BLK_INT,
>   	SPRD_DMA_LIST_INT,
>   	SPRD_DMA_CFGERR_INT,
> +	SPRD_DMA_SRC_CHN0_INT,
> +	SPRD_DMA_SRC_CHN1_INT,
> +	SPRD_DMA_DST_CHN0_INT,
> +	SPRD_DMA_DST_CHN1_INT,
>   };
>   
>   /*

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] dmaengine: sprd: Support two-stage dma interrupt
  2022-09-30  6:42 ` Baolin Wang
@ 2022-10-02 16:53   ` Cixi Geng
  0 siblings, 0 replies; 3+ messages in thread
From: Cixi Geng @ 2022-10-02 16:53 UTC (permalink / raw)
  To: Baolin Wang; +Cc: vkoul, orsonzhai, zhang.lyra, dmaengine, linux-kernel

Baolin Wang <baolin.wang@linux.alibaba.com> 于2022年9月30日周五 14:42写道：
>
> Hi Cixi,
>
> On 9/30/2022 1:53 PM, Cixi Geng wrote:
> > From: Cixi Geng <cixi.geng1@unisoc.com>
> >
> > Audio need to request Audio CP global dma interrupt, so Audio CP
> > DMA should support two-stage interrupt to adapte it.
> > It will occur interrupt when two-stage dma channel transfer done.
>
> If the AP does not want the interrupt, why not just set SPRD_DMA_NO_INT?
>
> I am struggling to understand the whole requirement, could you elaborate?
>
The AP should deal with the interrupt. I wrote the wrong conditions.
AP handle different interrupts about the 2-stage dma channel.
> >
> > Signed-off-by: Cixi Geng <cixi.geng1@unisoc.com>
> > ---
> >   drivers/dma/sprd-dma.c       |  8 ++++----
> >   include/linux/dma/sprd-dma.h | 12 ++++++++++++
> >   2 files changed, 16 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/dma/sprd-dma.c b/drivers/dma/sprd-dma.c
> > index 474d3ba8ec9f..7a9ade422a00 100644
> > --- a/drivers/dma/sprd-dma.c
> > +++ b/drivers/dma/sprd-dma.c
> > @@ -441,7 +441,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
> >               val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
> >               val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
> >               val |= SPRD_DMA_GLB_2STAGE_EN;
> > -             if (schan->int_type != SPRD_DMA_NO_INT)
> > +             if (schan->int_type != SPRD_DMA_SRC_CHN0_INT)
> >                       val |= SPRD_DMA_GLB_SRC_INT;
>
> That does not make sense to me. If user configues the interrupt type as
> SPRD_DMA_NO_INT, the code will still enable the source interrupt.
>
> If user configures the interrupt type as SPRD_DMA_SRC_CHN0_INT, you will
> disable the source interrupt? Confusing...
Sorry, the condition should be  (schan->int_type & SPRD_DMA_SRC_CHN0_INT)
I will fixed it next vesion.
>
> >               sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
> > @@ -451,7 +451,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
> >               val = chn & SPRD_DMA_GLB_SRC_CHN_MASK;
> >               val |= BIT(schan->trg_mode - 1) << SPRD_DMA_GLB_TRG_OFFSET;
> >               val |= SPRD_DMA_GLB_2STAGE_EN;
> > -             if (schan->int_type != SPRD_DMA_NO_INT)
> > +             if (schan->int_type != SPRD_DMA_SRC_CHN1_INT)
> >                       val |= SPRD_DMA_GLB_SRC_INT;
> >
> >               sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
> > @@ -461,7 +461,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
> >               val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
> >                       SPRD_DMA_GLB_DEST_CHN_MASK;
> >               val |= SPRD_DMA_GLB_2STAGE_EN;
> > -             if (schan->int_type != SPRD_DMA_NO_INT)
> > +             if (schan->int_type != SPRD_DMA_DST_CHN0_INT)
> >                       val |= SPRD_DMA_GLB_DEST_INT;
> >
> >               sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP1, val, val);
> > @@ -471,7 +471,7 @@ static int sprd_dma_set_2stage_config(struct sprd_dma_chn *schan)
> >               val = (chn << SPRD_DMA_GLB_DEST_CHN_OFFSET) &
> >                       SPRD_DMA_GLB_DEST_CHN_MASK;
> >               val |= SPRD_DMA_GLB_2STAGE_EN;
> > -             if (schan->int_type != SPRD_DMA_NO_INT)
> > +             if (schan->int_type != SPRD_DMA_DST_CHN1_INT)
> >                       val |= SPRD_DMA_GLB_DEST_INT;
> >
> >               sprd_dma_glb_update(sdev, SPRD_DMA_GLB_2STAGE_GRP2, val, val);
> > diff --git a/include/linux/dma/sprd-dma.h b/include/linux/dma/sprd-dma.h
> > index d09c6f6f6da5..26de41d6d915 100644
> > --- a/include/linux/dma/sprd-dma.h
> > +++ b/include/linux/dma/sprd-dma.h
> > @@ -101,6 +101,14 @@ enum sprd_dma_req_mode {
> >    * is done.
> >    * @SPRD_DMA_CFGERR_INT: configure error interrupt when configuration is
> >    * incorrect.
> > + * @SPRD_DMA_SRC_CHN0_INT: interrupt occurred when source channel0
> > + * transfer is done.
> > + * @SPRD_DMA_SRC_CHN1_INT: interrupt occurred when source channel1
> > + * transfer is done.
> > + * @SPRD_DMA_DST_CHN0_INT: interrupt occurred when destination channel0
> > + * transfer is done.
> > + * @SPRD_DMA_DST_CHN1_INT: interrupt occurred when destination channel1
> > + * transfer is done.
> >    */
> >   enum sprd_dma_int_type {
> >       SPRD_DMA_NO_INT,
> > @@ -112,6 +120,10 @@ enum sprd_dma_int_type {
> >       SPRD_DMA_TRANS_BLK_INT,
> >       SPRD_DMA_LIST_INT,
> >       SPRD_DMA_CFGERR_INT,
> > +     SPRD_DMA_SRC_CHN0_INT,
> > +     SPRD_DMA_SRC_CHN1_INT,
> > +     SPRD_DMA_DST_CHN0_INT,
> > +     SPRD_DMA_DST_CHN1_INT,
> >   };
> >
> >   /*

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-10-02 16:54 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-30  5:53 [PATCH] dmaengine: sprd: Support two-stage dma interrupt Cixi Geng
2022-09-30  6:42 ` Baolin Wang
2022-10-02 16:53   ` Cixi Geng

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