[v2 1/3] usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)

[v2 1/3] usb: dwc2: Add support for STM32F429/439/469 USB OTG HS/FS in FS mode (internal PHY)

[Bruno Herrera]

This patch introduces a new parameter to activate USB OTG HS/FS core embedded 
phy transciver. The STM32F4x9 SoC uses the GGPIO register to enable the transciver.

Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
---
 drivers/usb/dwc2/core.h   |  4 ++++
 drivers/usb/dwc2/hcd.c    | 21 ++++++++++++++-----
 drivers/usb/dwc2/hw.h     |  2 ++
 drivers/usb/dwc2/params.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 73 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 9548d3e..e3199c5 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
@@ -430,6 +430,9 @@ enum dwc2_ep0_state {
  *			needed.
  *			0 - No (default)
  *			1 - Yes
+ * @activate_transceiver: Activate internal transceiver using GGPIO register.
+ *			0 - Deactivate the transceiver (default)
+ *			1 - Activate the transceiver
  * @g_dma:              Enables gadget dma usage (default: autodetect).
  * @g_dma_desc:         Enables gadget descriptor DMA (default: autodetect).
  * @g_rx_fifo_size:	The periodic rx fifo size for the device, in
@@ -501,6 +504,7 @@ struct dwc2_core_params {
 	int uframe_sched;
 	int external_id_pin_ctl;
 	int hibernation;
+	int activate_transceiver;
 
 	/*
 	 * The following parameters are *only* set via device
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 911c3b3..6bc27f1 100644
--- a/drivers/usb/dwc2/hcd.c
+++ b/drivers/usb/dwc2/hcd.c
@@ -118,7 +118,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
 
 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 {
-	u32 usbcfg, i2cctl;
+	u32 usbcfg, ggpio, i2cctl;
 	int retval = 0;
 
 	/*
@@ -142,6 +142,17 @@ static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 				return retval;
 			}
 		}
+
+		ggpio = dwc2_readl(hsotg->regs + GGPIO);
+		if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN) &&
+		    (hsotg->params.activate_transceiver > 0)) {
+			dev_dbg(hsotg->dev, "Activating transceiver\n");
+			/* STM32F4xx uses the GGPIO register as general core
+			 * configuration register.
+			 */
+			ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
+			dwc2_writel(ggpio, hsotg->regs + GGPIO);
+		}
 	}
 
 	/*
@@ -941,7 +952,7 @@ static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
  *
  * In slave mode, checks for a free request queue entry, then sets the Channel
  * Enable and Channel Disable bits of the Host Channel Characteristics
- * register of the specified channel to intiate the halt. If there is no free
+ * register of the specified channel to initiate the halt. If there is no free
  * request queue entry, sets only the Channel Disable bit of the HCCHARn
  * register to flush requests for this channel. In the latter case, sets a
  * flag to indicate that the host channel needs to be halted when a request
@@ -2359,9 +2370,9 @@ static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
 	dwc2_flush_rx_fifo(hsotg);
 
 	/* Clear Host Set HNP Enable in the OTG Control Register */
-	otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
-	otgctl &= ~GOTGCTL_HSTSETHNPEN;
-	dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
+	//otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
+	//otgctl &= ~GOTGCTL_HSTSETHNPEN;
+	//dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
 
 	if (hsotg->params.dma_desc_enable <= 0) {
 		int num_channels, i;
diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h
index 5be056b..a84e93b 100644
--- a/drivers/usb/dwc2/hw.h
+++ b/drivers/usb/dwc2/hw.h
@@ -225,6 +225,8 @@
 
 #define GPVNDCTL			HSOTG_REG(0x0034)
 #define GGPIO				HSOTG_REG(0x0038)
+#define GGPIO_STM32_OTG_GCCFG_PWRDWN	(1 << 16)
+
 #define GUID				HSOTG_REG(0x003c)
 #define GSNPSID				HSOTG_REG(0x0040)
 #define GHWCFG1				HSOTG_REG(0x0044)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index a786256..a8fdcfc 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -192,6 +192,37 @@ static const struct dwc2_core_params params_amlogic = {
 	.hibernation			= -1,
 };
 
+static const struct dwc2_core_params params_stm32f4_otgfs = {
+	.otg_cap			= DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE,
+	.otg_ver			= -1,
+	.dma_desc_enable		= 0,
+	.dma_desc_fs_enable		= 0,
+	.speed				= DWC2_SPEED_PARAM_FULL,
+	.enable_dynamic_fifo		= -1,
+	.en_multiple_tx_fifo		= -1,
+	.host_rx_fifo_size		= 128,	/* 128 DWORDs */
+	.host_nperio_tx_fifo_size	= 96,	/* 96 DWORDs */
+	.host_perio_tx_fifo_size	= 96,	/* 96 DWORDs */
+	.max_transfer_size		= -1,
+	.max_packet_count		= 256,
+	.host_channels			= -1,
+	.phy_type			= DWC2_PHY_TYPE_PARAM_FS,
+	.phy_utmi_width			= -1,
+	.phy_ulpi_ddr			= -1,
+	.phy_ulpi_ext_vbus		= -1,
+	.i2c_enable			= 0,
+	.ulpi_fs_ls			= -1,
+	.host_support_fs_ls_low_power	= -1,
+	.host_ls_low_power_phy_clk	= -1,
+	.ts_dline			= -1,
+	.reload_ctl			= -1,
+	.ahbcfg				= -1,
+	.uframe_sched			= 0,
+	.external_id_pin_ctl		= -1,
+	.hibernation			= -1,
+	.activate_transceiver		= 1,
+};
+
 static const struct dwc2_core_params params_default = {
 	.otg_cap			= -1,
 	.otg_ver			= -1,
@@ -240,6 +271,8 @@ const struct of_device_id dwc2_of_match_table[] = {
 	{ .compatible = "amlogic,meson8b-usb", .data = &params_amlogic },
 	{ .compatible = "amlogic,meson-gxbb-usb", .data = &params_amlogic },
 	{ .compatible = "amcc,dwc-otg", .data = NULL },
+	{ .compatible = "st,stm32f4xx-fsotg", .data = &params_stm32f4_otgfs },
+	{ .compatible = "st,stm32f4xx-hsotg", .data = NULL },
 	{},
 };
 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
@@ -1056,6 +1089,23 @@ static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
 	hsotg->params.hibernation = val;
 }
 
+static void dwc2_set_param_activate_transceiver(struct dwc2_hsotg *hsotg,
+		int val)
+{
+	if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
+		if (val >= 0) {
+			dev_err(hsotg->dev,
+				"'%d' invalid for parameter activate transceiver\n",
+				val);
+			dev_err(hsotg->dev, "activate transceiver must be 0 or 1\n");
+		}
+		val = 0;
+		dev_dbg(hsotg->dev, "Setting activate transceiver to %d\n", val);
+	}
+
+	hsotg->params.activate_transceiver = val;
+}
+
 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 {
 	int i;
@@ -1170,6 +1220,7 @@ static void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
 	dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
 	dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
 	dwc2_set_param_hibernation(hsotg, params->hibernation);
+	dwc2_set_param_activate_transceiver(hsotg, params->activate_transceiver);
 
 	/*
 	 * Set devicetree-only parameters. These parameters do not
-- 
2.10.1 (Apple Git-78)

[v2 2/3] ARM: dts: STM32 Add USB FS host mode support

[Bruno Herrera]

This patch adds the USB pins and nodes for USB HS/FS cores working at FS speed,
using embedded PHY.

Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
---
 arch/arm/boot/dts/stm32f429-disco.dts | 30 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/stm32f429.dtsi      | 35 ++++++++++++++++++++++++++++++++++-
 arch/arm/boot/dts/stm32f469-disco.dts | 30 ++++++++++++++++++++++++++++++
 3 files changed, 94 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 7d0415e..374c5ed 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -88,6 +88,16 @@
 			gpios = <&gpioa 0 0>;
 		};
 	};
+
+	/* This turns on vbus for otg for host mode (dwc2) */
+	vcc5v_otg: vcc5v-otg-regulator {
+		compatible = "regulator-fixed";
+		gpio = <&gpioc 4 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbotg_pwren_h>;
+		regulator-name = "vcc5_host1";
+		regulator-always-on;
+	};
 };
 
 &clk_hse {
@@ -99,3 +109,23 @@
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&usbotg_hs {
+	compatible = "st,stm32-fsotg", "snps,dwc2";
+	dr_mode = "host";
+	pinctrl-0 = <&usbotg_fs_pins_b>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pinctrl {
+	usb-host {
+		usbotg_pwren_h: usbotg-pwren-h {
+			pins {
+				pinmux = <STM32F429_PC4_FUNC_GPIO>;
+				bias-disable;
+				drive-push-pull;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index e4dae0e..bc07aa8 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -206,7 +206,7 @@
 			reg = <0x40007000 0x400>;
 		};
 
-		pin-controller {
+		pinctrl: pin-controller {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "st,stm32f429-pinctrl";
@@ -316,6 +316,30 @@
 				};
 			};
 
+			usbotg_fs_pins_a: usbotg_fs@0 {
+				pins {
+					pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
+						 <STM32F429_PA11_FUNC_OTG_FS_DM>,
+						 <STM32F429_PA12_FUNC_OTG_FS_DP>;
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+			usbotg_fs_pins_b: usbotg_fs@1 {
+				pins {
+					pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
+						 <STM32F429_PB14_FUNC_OTG_HS_DM>,
+						 <STM32F429_PB15_FUNC_OTG_HS_DP>;
+					bias-disable;
+					drive-push-pull;
+					slew-rate = <2>;
+				};
+			};
+
+
+
 			usbotg_hs_pins_a: usbotg_hs@0 {
 				pins {
 					pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
@@ -420,6 +444,15 @@
 			status = "disabled";
 		};
 
+		usbotg_fs: usb@50000000 {
+			compatible = "st,stm32f4xx-fsotg", "snps,dwc2";
+			reg = <0x50000000 0x40000>;
+			interrupts = <67>;
+			clocks = <&rcc 0 39>;
+			clock-names = "otg";
+			status = "disabled";
+		};
+
 		rng: rng@50060800 {
 			compatible = "st,stm32-rng";
 			reg = <0x50060800 0x400>;
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 8877c00..8ae6763 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -68,6 +68,17 @@
 	soc {
 		dma-ranges = <0xc0000000 0x0 0x10000000>;
 	};
+
+	/* This turns on vbus for otg for host mode (dwc2) */
+	vcc5v_otg: vcc5v-otg-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpiob 2 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&usbotg_pwren_h>;
+		regulator-name = "vcc5_host1";
+		regulator-always-on;
+	};
 };
 
 &rcc {
@@ -81,3 +92,22 @@
 &usart3 {
 	status = "okay";
 };
+
+&usbotg_fs {
+	dr_mode = "host";
+	pinctrl-0 = <&usbotg_fs_pins_a>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pinctrl {
+	usb-host {
+		usbotg_pwren_h: usbotg-pwren-h {
+			pins {
+				pinmux = <STM32F429_PB2_FUNC_GPIO>;
+				bias-disable;
+				drive-push-pull;
+			};
+		};
+	};
+};
-- 
2.10.1 (Apple Git-78)

[v2 3/3] dt-bindings: Document the STM32 USB OTG DWC2 core binding

[Bruno Herrera]

This patch adds the documentation for STM32F4x9 USB OTG FS/HS compatible strings.

Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
---
 Documentation/devicetree/bindings/usb/dwc2.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc2.txt b/Documentation/devicetree/bindings/usb/dwc2.txt
index 6c7c2bce..637223a 100644
--- a/Documentation/devicetree/bindings/usb/dwc2.txt
+++ b/Documentation/devicetree/bindings/usb/dwc2.txt
@@ -14,6 +14,10 @@ Required properties:
   - "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
   - "amcc,dwc-otg": The DWC2 USB controller instance in AMCC Canyonlands 460EX SoCs;
   - snps,dwc2: A generic DWC2 USB controller with default parameters.
+  - "st,stm32f4xx-fsotg": The DWC2 USB FS/HS controller instance in STM32F4xx SoCs
+  configured in FS mode;
+  - "st,stm32f4xx-hsotg": The DWC2 USB HS controller instance in STM32F4xx SoCs
+  configured in HS mode;
 - reg : Should contain 1 register range (address and length)
 - interrupts : Should contain 1 interrupt
 - clocks: clock provider specifier
-- 
2.10.1 (Apple Git-78)

Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support

[Alexandre Torgue]

Hi Bruno,

On 01/16/2017 03:09 AM, Bruno Herrera wrote:
> This patch adds the USB pins and nodes for USB HS/FS cores working at FS speed,
> using embedded PHY.
>
> Signed-off-by: Bruno Herrera <bruherrera@gmail.com>

Sorry, but what is patch 1 & pacth 3 status ?

For this one, can split it in 3 patches (one patch for SOC and one for 
each board) please.


> ---
>  arch/arm/boot/dts/stm32f429-disco.dts | 30 ++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/stm32f429.dtsi      | 35 ++++++++++++++++++++++++++++++++++-
>  arch/arm/boot/dts/stm32f469-disco.dts | 30 ++++++++++++++++++++++++++++++
>  3 files changed, 94 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
> index 7d0415e..374c5ed 100644
> --- a/arch/arm/boot/dts/stm32f429-disco.dts
> +++ b/arch/arm/boot/dts/stm32f429-disco.dts
> @@ -88,6 +88,16 @@
>  			gpios = <&gpioa 0 0>;
>  		};
>  	};
> +
> +	/* This turns on vbus for otg for host mode (dwc2) */
> +	vcc5v_otg: vcc5v-otg-regulator {
> +		compatible = "regulator-fixed";
> +		gpio = <&gpioc 4 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&usbotg_pwren_h>;
> +		regulator-name = "vcc5_host1";
> +		regulator-always-on;
> +	};
>  };
>
>  &clk_hse {
> @@ -99,3 +109,23 @@
>  	pinctrl-names = "default";
>  	status = "okay";
>  };
> +
> +&usbotg_hs {
> +	compatible = "st,stm32-fsotg", "snps,dwc2";
> +	dr_mode = "host";
> +	pinctrl-0 = <&usbotg_fs_pins_b>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&pinctrl {
> +	usb-host {
> +		usbotg_pwren_h: usbotg-pwren-h {
> +			pins {
> +				pinmux = <STM32F429_PC4_FUNC_GPIO>;
> +				bias-disable;
> +				drive-push-pull;
> +			};
> +		};
> +	};
> +};

Pinctrl muxing has to be defined/declared in stm32f429.dtsi


> diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
> index e4dae0e..bc07aa8 100644
> --- a/arch/arm/boot/dts/stm32f429.dtsi
> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> @@ -206,7 +206,7 @@
>  			reg = <0x40007000 0x400>;
>  		};
>
> -		pin-controller {
> +		pinctrl: pin-controller {
>  			#address-cells = <1>;
>  			#size-cells = <1>;
>  			compatible = "st,stm32f429-pinctrl";
> @@ -316,6 +316,30 @@
>  				};
>  			};
>
> +			usbotg_fs_pins_a: usbotg_fs@0 {
> +				pins {
> +					pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
> +						 <STM32F429_PA11_FUNC_OTG_FS_DM>,
> +						 <STM32F429_PA12_FUNC_OTG_FS_DP>;
> +					bias-disable;
> +					drive-push-pull;
> +					slew-rate = <2>;
> +				};
> +			};
> +
> +			usbotg_fs_pins_b: usbotg_fs@1 {
> +				pins {
> +					pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
> +						 <STM32F429_PB14_FUNC_OTG_HS_DM>,
> +						 <STM32F429_PB15_FUNC_OTG_HS_DP>;
> +					bias-disable;
> +					drive-push-pull;
> +					slew-rate = <2>;
> +				};
> +			};
> +
> +
> +
>  			usbotg_hs_pins_a: usbotg_hs@0 {
>  				pins {
>  					pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
> @@ -420,6 +444,15 @@
>  			status = "disabled";
>  		};
>
> +		usbotg_fs: usb@50000000 {
> +			compatible = "st,stm32f4xx-fsotg", "snps,dwc2";
> +			reg = <0x50000000 0x40000>;
> +			interrupts = <67>;
> +			clocks = <&rcc 0 39>;
> +			clock-names = "otg";
> +			status = "disabled";
> +		};
> +
>  		rng: rng@50060800 {
>  			compatible = "st,stm32-rng";
>  			reg = <0x50060800 0x400>;
> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
> index 8877c00..8ae6763 100644
> --- a/arch/arm/boot/dts/stm32f469-disco.dts
> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
> @@ -68,6 +68,17 @@
>  	soc {
>  		dma-ranges = <0xc0000000 0x0 0x10000000>;
>  	};
> +
> +	/* This turns on vbus for otg for host mode (dwc2) */
> +	vcc5v_otg: vcc5v-otg-regulator {
> +		compatible = "regulator-fixed";
> +		enable-active-high;
> +		gpio = <&gpiob 2 0>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&usbotg_pwren_h>;
> +		regulator-name = "vcc5_host1";
> +		regulator-always-on;
> +	};
>  };
>
>  &rcc {
> @@ -81,3 +92,22 @@
>  &usart3 {
>  	status = "okay";
>  };
> +
> +&usbotg_fs {
> +	dr_mode = "host";
> +	pinctrl-0 = <&usbotg_fs_pins_a>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&pinctrl {
> +	usb-host {
> +		usbotg_pwren_h: usbotg-pwren-h {
> +			pins {
> +				pinmux = <STM32F429_PB2_FUNC_GPIO>;
> +				bias-disable;
> +				drive-push-pull;
> +			};
> +		};
> +	};
> +};
Same. Note that if you have 2 configuration for one feature (like it is 
here for "usbotg_pwren_h"), you could index it. Not that I'm adding a 
dedidacted pinctroller for stm32f469.

Br
Alex
>

Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support

[Bruno Herrera]

Hi Alex,

On Mon, Jan 16, 2017 at 6:57 AM, Alexandre Torgue
<alexandre.torgue@st.com> wrote:
> Hi Bruno,
>
> On 01/16/2017 03:09 AM, Bruno Herrera wrote:
>>
>> This patch adds the USB pins and nodes for USB HS/FS cores working at FS
>> speed,
>> using embedded PHY.
>>
>> Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
>
>
> Sorry, but what is patch 1 & pacth 3 status ?

My bad, I'll add the status of the patch series version 3.
>
> For this one, can split it in 3 patches (one patch for SOC and one for each
> board) please.
>

No problem.
>
>
>> ---
>>  arch/arm/boot/dts/stm32f429-disco.dts | 30 ++++++++++++++++++++++++++++++
>>  arch/arm/boot/dts/stm32f429.dtsi      | 35
>> ++++++++++++++++++++++++++++++++++-
>>  arch/arm/boot/dts/stm32f469-disco.dts | 30 ++++++++++++++++++++++++++++++
>>  3 files changed, 94 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
>> b/arch/arm/boot/dts/stm32f429-disco.dts
>> index 7d0415e..374c5ed 100644
>> --- a/arch/arm/boot/dts/stm32f429-disco.dts
>> +++ b/arch/arm/boot/dts/stm32f429-disco.dts
>> @@ -88,6 +88,16 @@
>>                         gpios = <&gpioa 0 0>;
>>                 };
>>         };
>> +
>> +       /* This turns on vbus for otg for host mode (dwc2) */
>> +       vcc5v_otg: vcc5v-otg-regulator {
>> +               compatible = "regulator-fixed";
>> +               gpio = <&gpioc 4 0>;
>> +               pinctrl-names = "default";
>> +               pinctrl-0 = <&usbotg_pwren_h>;
>> +               regulator-name = "vcc5_host1";
>> +               regulator-always-on;
>> +       };
>>  };
>>
>>  &clk_hse {
>> @@ -99,3 +109,23 @@
>>         pinctrl-names = "default";
>>         status = "okay";
>>  };
>> +
>> +&usbotg_hs {
>> +       compatible = "st,stm32-fsotg", "snps,dwc2";
>> +       dr_mode = "host";
>> +       pinctrl-0 = <&usbotg_fs_pins_b>;
>> +       pinctrl-names = "default";
>> +       status = "okay";
>> +};
>> +
>> +&pinctrl {
>> +       usb-host {
>> +               usbotg_pwren_h: usbotg-pwren-h {
>> +                       pins {
>> +                               pinmux = <STM32F429_PC4_FUNC_GPIO>;
>> +                               bias-disable;
>> +                               drive-push-pull;
>> +                       };
>> +               };
>> +       };
>> +};
>
>
> Pinctrl muxing has to be defined/declared in stm32f429.dtsi
>
This is board specific logic and it vary from board to board, should
it be defined here?
>
>
>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>> b/arch/arm/boot/dts/stm32f429.dtsi
>> index e4dae0e..bc07aa8 100644
>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>> @@ -206,7 +206,7 @@
>>                         reg = <0x40007000 0x400>;
>>                 };
>>
>> -               pin-controller {
>> +               pinctrl: pin-controller {
>>                         #address-cells = <1>;
>>                         #size-cells = <1>;
>>                         compatible = "st,stm32f429-pinctrl";
>> @@ -316,6 +316,30 @@
>>                                 };
>>                         };
>>
>> +                       usbotg_fs_pins_a: usbotg_fs@0 {
>> +                               pins {
>> +                                       pinmux =
>> <STM32F429_PA10_FUNC_OTG_FS_ID>,
>> +
>> <STM32F429_PA11_FUNC_OTG_FS_DM>,
>> +
>> <STM32F429_PA12_FUNC_OTG_FS_DP>;
>> +                                       bias-disable;
>> +                                       drive-push-pull;
>> +                                       slew-rate = <2>;
>> +                               };
>> +                       };
>> +
>> +                       usbotg_fs_pins_b: usbotg_fs@1 {
>> +                               pins {
>> +                                       pinmux =
>> <STM32F429_PB12_FUNC_OTG_HS_ID>,
>> +
>> <STM32F429_PB14_FUNC_OTG_HS_DM>,
>> +
>> <STM32F429_PB15_FUNC_OTG_HS_DP>;
>> +                                       bias-disable;
>> +                                       drive-push-pull;
>> +                                       slew-rate = <2>;
>> +                               };
>> +                       };
>> +
>> +
>> +
>>                         usbotg_hs_pins_a: usbotg_hs@0 {
>>                                 pins {
>>                                         pinmux =
>> <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
>> @@ -420,6 +444,15 @@
>>                         status = "disabled";
>>                 };
>>
>> +               usbotg_fs: usb@50000000 {
>> +                       compatible = "st,stm32f4xx-fsotg", "snps,dwc2";
>> +                       reg = <0x50000000 0x40000>;
>> +                       interrupts = <67>;
>> +                       clocks = <&rcc 0 39>;
>> +                       clock-names = "otg";
>> +                       status = "disabled";
>> +               };
>> +
>>                 rng: rng@50060800 {
>>                         compatible = "st,stm32-rng";
>>                         reg = <0x50060800 0x400>;
>> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
>> b/arch/arm/boot/dts/stm32f469-disco.dts
>> index 8877c00..8ae6763 100644
>> --- a/arch/arm/boot/dts/stm32f469-disco.dts
>> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
>> @@ -68,6 +68,17 @@
>>         soc {
>>                 dma-ranges = <0xc0000000 0x0 0x10000000>;
>>         };
>> +
>> +       /* This turns on vbus for otg for host mode (dwc2) */
>> +       vcc5v_otg: vcc5v-otg-regulator {
>> +               compatible = "regulator-fixed";
>> +               enable-active-high;
>> +               gpio = <&gpiob 2 0>;
>> +               pinctrl-names = "default";
>> +               pinctrl-0 = <&usbotg_pwren_h>;
>> +               regulator-name = "vcc5_host1";
>> +               regulator-always-on;
>> +       };
>>  };
>>
>>  &rcc {
>> @@ -81,3 +92,22 @@
>>  &usart3 {
>>         status = "okay";
>>  };
>> +
>> +&usbotg_fs {
>> +       dr_mode = "host";
>> +       pinctrl-0 = <&usbotg_fs_pins_a>;
>> +       pinctrl-names = "default";
>> +       status = "okay";
>> +};
>> +
>> +&pinctrl {
>> +       usb-host {
>> +               usbotg_pwren_h: usbotg-pwren-h {
>> +                       pins {
>> +                               pinmux = <STM32F429_PB2_FUNC_GPIO>;
>> +                               bias-disable;
>> +                               drive-push-pull;
>> +                       };
>> +               };
>> +       };
>> +};
>
> Same. Note that if you have 2 configuration for one feature (like it is here
> for "usbotg_pwren_h"), you could index it. Not that I'm adding a dedidacted
> pinctroller for stm32f469.
>
Sorry, but I dont know what you mean by index here.
The usbotg_pwren_h (VBUS ENABLE) is attached in different port/pins
for each board.

Br.,


> Br
> Alex
>>
>>
>
>

Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support

[Alexandre Torgue]

On 01/16/2017 11:26 AM, Bruno Herrera wrote:
> Hi Alex,
>
> On Mon, Jan 16, 2017 at 6:57 AM, Alexandre Torgue
> <alexandre.torgue@st.com> wrote:
>> Hi Bruno,
>>
>> On 01/16/2017 03:09 AM, Bruno Herrera wrote:
>>>
>>> This patch adds the USB pins and nodes for USB HS/FS cores working at FS
>>> speed,
>>> using embedded PHY.
>>>
>>> Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
>>
>>
>> Sorry, but what is patch 1 & pacth 3 status ?
>
> My bad, I'll add the status of the patch series version 3.
>>
>> For this one, can split it in 3 patches (one patch for SOC and one for each
>> board) please.
>>
>
> No problem.
>>
>>
>>> ---
>>>  arch/arm/boot/dts/stm32f429-disco.dts | 30 ++++++++++++++++++++++++++++++
>>>  arch/arm/boot/dts/stm32f429.dtsi      | 35
>>> ++++++++++++++++++++++++++++++++++-
>>>  arch/arm/boot/dts/stm32f469-disco.dts | 30 ++++++++++++++++++++++++++++++
>>>  3 files changed, 94 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
>>> b/arch/arm/boot/dts/stm32f429-disco.dts
>>> index 7d0415e..374c5ed 100644
>>> --- a/arch/arm/boot/dts/stm32f429-disco.dts
>>> +++ b/arch/arm/boot/dts/stm32f429-disco.dts
>>> @@ -88,6 +88,16 @@
>>>                         gpios = <&gpioa 0 0>;
>>>                 };
>>>         };
>>> +
>>> +       /* This turns on vbus for otg for host mode (dwc2) */
>>> +       vcc5v_otg: vcc5v-otg-regulator {
>>> +               compatible = "regulator-fixed";
>>> +               gpio = <&gpioc 4 0>;
>>> +               pinctrl-names = "default";
>>> +               pinctrl-0 = <&usbotg_pwren_h>;
>>> +               regulator-name = "vcc5_host1";
>>> +               regulator-always-on;
>>> +       };
>>>  };
>>>
>>>  &clk_hse {
>>> @@ -99,3 +109,23 @@
>>>         pinctrl-names = "default";
>>>         status = "okay";
>>>  };
>>> +
>>> +&usbotg_hs {
>>> +       compatible = "st,stm32-fsotg", "snps,dwc2";
>>> +       dr_mode = "host";
>>> +       pinctrl-0 = <&usbotg_fs_pins_b>;
>>> +       pinctrl-names = "default";
>>> +       status = "okay";
>>> +};
>>> +
>>> +&pinctrl {
>>> +       usb-host {
>>> +               usbotg_pwren_h: usbotg-pwren-h {
>>> +                       pins {
>>> +                               pinmux = <STM32F429_PC4_FUNC_GPIO>;
>>> +                               bias-disable;
>>> +                               drive-push-pull;
>>> +                       };
>>> +               };
>>> +       };
>>> +};
>>
>>
>> Pinctrl muxing has to be defined/declared in stm32f429.dtsi
>>
> This is board specific logic and it vary from board to board, should
> it be defined here?

Pinmuxing definition is a SOC part (as it is a possibility offered by 
SOC). Pinmuxing choice is board specific.

Regarding your code, it should not boot. Ex for disco:

  +               gpio = <&gpiob 2 0>;
 >>> +               pinctrl-names = "default";
 >>> +               pinctrl-0 = <&usbotg_pwren_h>;

+

   usb-host {
 >>> +               usbotg_pwren_h: usbotg-pwren-h {
 >>> +                       pins {
 >>> +                               pinmux = <STM32F429_PB2_FUNC_GPIO>;

Indeed, you are declaring two time the pin PB2 (one time through pinctrl 
and one other time through gpiolib). in strict mode you can't request 2 
times the same Pin.
I assume that your driver want controls this GPIO (request/set direction 
/ set, get value ...). in this case you only need to declare this part:

gpio = <&gpiob 2 0>;

The GPIO lib will deal with pinctrl framework for you.
And in this case, yes gpio declaration is board specific so this part 
will be in board file.

Let me know, if I'm not enough clear.

Regards
Alex




>>
>>
>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>>> b/arch/arm/boot/dts/stm32f429.dtsi
>>> index e4dae0e..bc07aa8 100644
>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>>> @@ -206,7 +206,7 @@
>>>                         reg = <0x40007000 0x400>;
>>>                 };
>>>
>>> -               pin-controller {
>>> +               pinctrl: pin-controller {
>>>                         #address-cells = <1>;
>>>                         #size-cells = <1>;
>>>                         compatible = "st,stm32f429-pinctrl";
>>> @@ -316,6 +316,30 @@
>>>                                 };
>>>                         };
>>>
>>> +                       usbotg_fs_pins_a: usbotg_fs@0 {
>>> +                               pins {
>>> +                                       pinmux =
>>> <STM32F429_PA10_FUNC_OTG_FS_ID>,
>>> +
>>> <STM32F429_PA11_FUNC_OTG_FS_DM>,
>>> +
>>> <STM32F429_PA12_FUNC_OTG_FS_DP>;
>>> +                                       bias-disable;
>>> +                                       drive-push-pull;
>>> +                                       slew-rate = <2>;
>>> +                               };
>>> +                       };
>>> +
>>> +                       usbotg_fs_pins_b: usbotg_fs@1 {
>>> +                               pins {
>>> +                                       pinmux =
>>> <STM32F429_PB12_FUNC_OTG_HS_ID>,
>>> +
>>> <STM32F429_PB14_FUNC_OTG_HS_DM>,
>>> +
>>> <STM32F429_PB15_FUNC_OTG_HS_DP>;
>>> +                                       bias-disable;
>>> +                                       drive-push-pull;
>>> +                                       slew-rate = <2>;
>>> +                               };
>>> +                       };
>>> +
>>> +
>>> +
>>>                         usbotg_hs_pins_a: usbotg_hs@0 {
>>>                                 pins {
>>>                                         pinmux =
>>> <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
>>> @@ -420,6 +444,15 @@
>>>                         status = "disabled";
>>>                 };
>>>
>>> +               usbotg_fs: usb@50000000 {
>>> +                       compatible = "st,stm32f4xx-fsotg", "snps,dwc2";
>>> +                       reg = <0x50000000 0x40000>;
>>> +                       interrupts = <67>;
>>> +                       clocks = <&rcc 0 39>;
>>> +                       clock-names = "otg";
>>> +                       status = "disabled";
>>> +               };
>>> +
>>>                 rng: rng@50060800 {
>>>                         compatible = "st,stm32-rng";
>>>                         reg = <0x50060800 0x400>;
>>> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
>>> b/arch/arm/boot/dts/stm32f469-disco.dts
>>> index 8877c00..8ae6763 100644
>>> --- a/arch/arm/boot/dts/stm32f469-disco.dts
>>> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
>>> @@ -68,6 +68,17 @@
>>>         soc {
>>>                 dma-ranges = <0xc0000000 0x0 0x10000000>;
>>>         };
>>> +
>>> +       /* This turns on vbus for otg for host mode (dwc2) */
>>> +       vcc5v_otg: vcc5v-otg-regulator {
>>> +               compatible = "regulator-fixed";
>>> +               enable-active-high;
>>> +               gpio = <&gpiob 2 0>;
>>> +               pinctrl-names = "default";
>>> +               pinctrl-0 = <&usbotg_pwren_h>;
>>> +               regulator-name = "vcc5_host1";
>>> +               regulator-always-on;
>>> +       };
>>>  };
>>>
>>>  &rcc {
>>> @@ -81,3 +92,22 @@
>>>  &usart3 {
>>>         status = "okay";
>>>  };
>>> +
>>> +&usbotg_fs {
>>> +       dr_mode = "host";
>>> +       pinctrl-0 = <&usbotg_fs_pins_a>;
>>> +       pinctrl-names = "default";
>>> +       status = "okay";
>>> +};
>>> +
>>> +&pinctrl {
>>> +       usb-host {
>>> +               usbotg_pwren_h: usbotg-pwren-h {
>>> +                       pins {
>>> +                               pinmux = <STM32F429_PB2_FUNC_GPIO>;
>>> +                               bias-disable;
>>> +                               drive-push-pull;
>>> +                       };
>>> +               };
>>> +       };
>>> +};
>>
>> Same. Note that if you have 2 configuration for one feature (like it is here
>> for "usbotg_pwren_h"), you could index it. Not that I'm adding a dedidacted
>> pinctroller for stm32f469.
>>
> Sorry, but I dont know what you mean by index here.
> The usbotg_pwren_h (VBUS ENABLE) is attached in different port/pins
> for each board.
>
> Br.,
>
>
>> Br
>> Alex
>>>
>>>
>>
>>

Re: [v2 2/3] ARM: dts: STM32 Add USB FS host mode support

[Bruno Herrera]

On Mon, Jan 16, 2017 at 9:47 AM, Alexandre Torgue
<alexandre.torgue@st.com> wrote:
>
>
> On 01/16/2017 11:26 AM, Bruno Herrera wrote:
>>
>> Hi Alex,
>>
>> On Mon, Jan 16, 2017 at 6:57 AM, Alexandre Torgue
>> <alexandre.torgue@st.com> wrote:
>>>
>>> Hi Bruno,
>>>
>>> On 01/16/2017 03:09 AM, Bruno Herrera wrote:
>>>>
>>>>
>>>> This patch adds the USB pins and nodes for USB HS/FS cores working at FS
>>>> speed,
>>>> using embedded PHY.
>>>>
>>>> Signed-off-by: Bruno Herrera <bruherrera@gmail.com>
>>>
>>>
>>>
>>> Sorry, but what is patch 1 & pacth 3 status ?
>>
>>
>> My bad, I'll add the status of the patch series version 3.
>>>
>>>
>>> For this one, can split it in 3 patches (one patch for SOC and one for
>>> each
>>> board) please.
>>>
>>
>> No problem.
>>>
>>>
>>>
>>>> ---
>>>>  arch/arm/boot/dts/stm32f429-disco.dts | 30
>>>> ++++++++++++++++++++++++++++++
>>>>  arch/arm/boot/dts/stm32f429.dtsi      | 35
>>>> ++++++++++++++++++++++++++++++++++-
>>>>  arch/arm/boot/dts/stm32f469-disco.dts | 30
>>>> ++++++++++++++++++++++++++++++
>>>>  3 files changed, 94 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/stm32f429-disco.dts
>>>> b/arch/arm/boot/dts/stm32f429-disco.dts
>>>> index 7d0415e..374c5ed 100644
>>>> --- a/arch/arm/boot/dts/stm32f429-disco.dts
>>>> +++ b/arch/arm/boot/dts/stm32f429-disco.dts
>>>> @@ -88,6 +88,16 @@
>>>>                         gpios = <&gpioa 0 0>;
>>>>                 };
>>>>         };
>>>> +
>>>> +       /* This turns on vbus for otg for host mode (dwc2) */
>>>> +       vcc5v_otg: vcc5v-otg-regulator {
>>>> +               compatible = "regulator-fixed";
>>>> +               gpio = <&gpioc 4 0>;
>>>> +               pinctrl-names = "default";
>>>> +               pinctrl-0 = <&usbotg_pwren_h>;
>>>> +               regulator-name = "vcc5_host1";
>>>> +               regulator-always-on;
>>>> +       };
>>>>  };
>>>>
>>>>  &clk_hse {
>>>> @@ -99,3 +109,23 @@
>>>>         pinctrl-names = "default";
>>>>         status = "okay";
>>>>  };
>>>> +
>>>> +&usbotg_hs {
>>>> +       compatible = "st,stm32-fsotg", "snps,dwc2";
>>>> +       dr_mode = "host";
>>>> +       pinctrl-0 = <&usbotg_fs_pins_b>;
>>>> +       pinctrl-names = "default";
>>>> +       status = "okay";
>>>> +};
>>>> +
>>>> +&pinctrl {
>>>> +       usb-host {
>>>> +               usbotg_pwren_h: usbotg-pwren-h {
>>>> +                       pins {
>>>> +                               pinmux = <STM32F429_PC4_FUNC_GPIO>;
>>>> +                               bias-disable;
>>>> +                               drive-push-pull;
>>>> +                       };
>>>> +               };
>>>> +       };
>>>> +};
>>>
>>>
>>>
>>> Pinctrl muxing has to be defined/declared in stm32f429.dtsi
>>>
>> This is board specific logic and it vary from board to board, should
>> it be defined here?
>
>
> Pinmuxing definition is a SOC part (as it is a possibility offered by SOC).
> Pinmuxing choice is board specific.
>
> Regarding your code, it should not boot. Ex for disco:
>
>  +               gpio = <&gpiob 2 0>;
>>>> +               pinctrl-names = "default";
>>>> +               pinctrl-0 = <&usbotg_pwren_h>;
>
> +
>
>   usb-host {
>>>> +               usbotg_pwren_h: usbotg-pwren-h {
>>>> +                       pins {
>>>> +                               pinmux = <STM32F429_PB2_FUNC_GPIO>;
>
> Indeed, you are declaring two time the pin PB2 (one time through pinctrl and
> one other time through gpiolib). in strict mode you can't request 2 times
> the same Pin.
> I assume that your driver want controls this GPIO (request/set direction /
> set, get value ...). in this case you only need to declare this part:
>
> gpio = <&gpiob 2 0>;
>
> The GPIO lib will deal with pinctrl framework for you.
> And in this case, yes gpio declaration is board specific so this part will
> be in board file.
>
> Let me know, if I'm not enough clear.

Thats very clear! Thanks for bringing.
I'll retest without the pinctrl.

br,
Bruno

>
> Regards
> Alex
>
>
>
>
>
>>>
>>>
>>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>>>> b/arch/arm/boot/dts/stm32f429.dtsi
>>>> index e4dae0e..bc07aa8 100644
>>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>>>> @@ -206,7 +206,7 @@
>>>>                         reg = <0x40007000 0x400>;
>>>>                 };
>>>>
>>>> -               pin-controller {
>>>> +               pinctrl: pin-controller {
>>>>                         #address-cells = <1>;
>>>>                         #size-cells = <1>;
>>>>                         compatible = "st,stm32f429-pinctrl";
>>>> @@ -316,6 +316,30 @@
>>>>                                 };
>>>>                         };
>>>>
>>>> +                       usbotg_fs_pins_a: usbotg_fs@0 {
>>>> +                               pins {
>>>> +                                       pinmux =
>>>> <STM32F429_PA10_FUNC_OTG_FS_ID>,
>>>> +
>>>> <STM32F429_PA11_FUNC_OTG_FS_DM>,
>>>> +
>>>> <STM32F429_PA12_FUNC_OTG_FS_DP>;
>>>> +                                       bias-disable;
>>>> +                                       drive-push-pull;
>>>> +                                       slew-rate = <2>;
>>>> +                               };
>>>> +                       };
>>>> +
>>>> +                       usbotg_fs_pins_b: usbotg_fs@1 {
>>>> +                               pins {
>>>> +                                       pinmux =
>>>> <STM32F429_PB12_FUNC_OTG_HS_ID>,
>>>> +
>>>> <STM32F429_PB14_FUNC_OTG_HS_DM>,
>>>> +
>>>> <STM32F429_PB15_FUNC_OTG_HS_DP>;
>>>> +                                       bias-disable;
>>>> +                                       drive-push-pull;
>>>> +                                       slew-rate = <2>;
>>>> +                               };
>>>> +                       };
>>>> +
>>>> +
>>>> +
>>>>                         usbotg_hs_pins_a: usbotg_hs@0 {
>>>>                                 pins {
>>>>                                         pinmux =
>>>> <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
>>>> @@ -420,6 +444,15 @@
>>>>                         status = "disabled";
>>>>                 };
>>>>
>>>> +               usbotg_fs: usb@50000000 {
>>>> +                       compatible = "st,stm32f4xx-fsotg", "snps,dwc2";
>>>> +                       reg = <0x50000000 0x40000>;
>>>> +                       interrupts = <67>;
>>>> +                       clocks = <&rcc 0 39>;
>>>> +                       clock-names = "otg";
>>>> +                       status = "disabled";
>>>> +               };
>>>> +
>>>>                 rng: rng@50060800 {
>>>>                         compatible = "st,stm32-rng";
>>>>                         reg = <0x50060800 0x400>;
>>>> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
>>>> b/arch/arm/boot/dts/stm32f469-disco.dts
>>>> index 8877c00..8ae6763 100644
>>>> --- a/arch/arm/boot/dts/stm32f469-disco.dts
>>>> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
>>>> @@ -68,6 +68,17 @@
>>>>         soc {
>>>>                 dma-ranges = <0xc0000000 0x0 0x10000000>;
>>>>         };
>>>> +
>>>> +       /* This turns on vbus for otg for host mode (dwc2) */
>>>> +       vcc5v_otg: vcc5v-otg-regulator {
>>>> +               compatible = "regulator-fixed";
>>>> +               enable-active-high;
>>>> +               gpio = <&gpiob 2 0>;
>>>> +               pinctrl-names = "default";
>>>> +               pinctrl-0 = <&usbotg_pwren_h>;
>>>> +               regulator-name = "vcc5_host1";
>>>> +               regulator-always-on;
>>>> +       };
>>>>  };
>>>>
>>>>  &rcc {
>>>> @@ -81,3 +92,22 @@
>>>>  &usart3 {
>>>>         status = "okay";
>>>>  };
>>>> +
>>>> +&usbotg_fs {
>>>> +       dr_mode = "host";
>>>> +       pinctrl-0 = <&usbotg_fs_pins_a>;
>>>> +       pinctrl-names = "default";
>>>> +       status = "okay";
>>>> +};
>>>> +
>>>> +&pinctrl {
>>>> +       usb-host {
>>>> +               usbotg_pwren_h: usbotg-pwren-h {
>>>> +                       pins {
>>>> +                               pinmux = <STM32F429_PB2_FUNC_GPIO>;
>>>> +                               bias-disable;
>>>> +                               drive-push-pull;
>>>> +                       };
>>>> +               };
>>>> +       };
>>>> +};
>>>
>>>
>>> Same. Note that if you have 2 configuration for one feature (like it is
>>> here
>>> for "usbotg_pwren_h"), you could index it. Not that I'm adding a
>>> dedidacted
>>> pinctroller for stm32f469.
>>>
>> Sorry, but I dont know what you mean by index here.
>> The usbotg_pwren_h (VBUS ENABLE) is attached in different port/pins
>> for each board.
>>
>> Br.,
>>
>>
>>> Br
>>> Alex
>>>>
>>>>
>>>>
>>>
>>>
>