From: Rob Clark <robdclark@gmail.com>
To: Jonathan Marek <jonathan@marek.ca>
Cc: Christoph Hellwig <hch@lst.de>,
Jordan Crouse <jcrouse@codeaurora.org>,
freedreno <freedreno@lists.freedesktop.org>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<linux-arm-msm@vger.kernel.org>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<dri-devel@lists.freedesktop.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
Date: Sun, 29 Nov 2020 10:51:08 -0800 [thread overview]
Message-ID: <CAF6AEGs488Ju2jg6TpkkiH-7fBK8f-HgQ210jmGf-Oghb-Jv2g@mail.gmail.com> (raw)
In-Reply-To: <b798d954-d0b5-d968-f03c-b3fe9ffd08fc@marek.ca>
On Mon, Nov 16, 2020 at 9:55 AM Jonathan Marek <jonathan@marek.ca> wrote:
>
> On 11/16/20 12:50 PM, Rob Clark wrote:
> > On Mon, Nov 16, 2020 at 9:33 AM Christoph Hellwig <hch@lst.de> wrote:
> >>
> >> On Sat, Nov 14, 2020 at 03:07:20PM -0500, Jonathan Marek wrote:
> >>> qcom's vulkan driver has nonCoherentAtomSize=1, and it looks like
> >>> dma_sync_single_for_cpu() does deal in some way with the partial cache line
> >>> case, although I'm not sure that means we can have a nonCoherentAtomSize=1.
> >>
> >> No, it doesn't. You need to ensure ownership is managed at
> >> dma_get_cache_alignment() granularity.
> >
> > my guess is nonCoherentAtomSize=1 only works in the case of cache
> > coherent buffers
> >
>
> nonCoherentAtomSize doesn't apply to coherent memory (as the name
> implies), I guess qcom's driver is just wrong about having
> nonCoherentAtomSize=1.
>
> Jordan just mentioned there is at least one conformance test for this, I
> wonder if it just doesn't test it well enough, or just doesn't test the
> non-coherent memory type?
I was *assuming* (but could be wrong) that Jordan was referring to an
opencl cts test?
At any rate, it is sounding like you should add a
`MSM_PARAM_CACHE_ALIGNMENT` type of param that returns
dma_get_cache_alignment(), and then properly implement offset/end
BR,
-R
next prev parent reply other threads:[~2020-11-29 18:50 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-14 15:17 [RESEND PATCH v2 0/5] drm/msm: support for host-cached BOs Jonathan Marek
2020-11-14 15:17 ` [RESEND PATCH v2 1/5] drm/msm: add MSM_BO_CACHED_COHERENT Jonathan Marek
2020-11-14 15:17 ` [RESEND PATCH v2 2/5] dma-direct: add dma_direct_bypass() to force direct ops Jonathan Marek
2020-11-14 16:21 ` Christoph Hellwig
2020-11-14 15:17 ` [RESEND PATCH v2 3/5] drm/msm: call dma_direct_bypass() Jonathan Marek
2020-11-14 16:21 ` Christoph Hellwig
2020-11-14 15:17 ` [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance Jonathan Marek
2020-11-14 16:24 ` Christoph Hellwig
2020-11-14 18:46 ` Rob Clark
2020-11-14 18:54 ` Jonathan Marek
2020-11-14 19:39 ` Rob Clark
2020-11-14 20:07 ` Jonathan Marek
2020-11-14 20:48 ` Rob Clark
2020-11-16 17:33 ` Christoph Hellwig
2020-11-16 17:50 ` Rob Clark
2020-11-16 17:52 ` Jonathan Marek
2020-11-29 18:51 ` Rob Clark [this message]
2020-11-16 17:27 ` [Freedreno] " Jordan Crouse
2020-11-16 17:25 ` Jordan Crouse
2020-11-14 15:17 ` [RESEND PATCH v2 5/5] drm/msm: bump up the uapi version Jonathan Marek
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