* [PATCH 0/2] drm/msm/a6xx: add A640/A650 hwcg
@ 2020-06-29 23:49 Jonathan Marek
2020-06-29 23:49 ` [PATCH 1/2] drm/msm/a6xx: hwcg tables in gpulist Jonathan Marek
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Jonathan Marek @ 2020-06-29 23:49 UTC (permalink / raw)
To: freedreno
Cc: Akhil P Oommen, AngeloGioacchino Del Regno, Bjorn Andersson,
Brian Masney, Daniel Vetter, David Airlie,
open list:DRM DRIVER FOR MSM ADRENO GPU, Eric Anholt,
Jordan Crouse, open list:DRM DRIVER FOR MSM ADRENO GPU,
open list, Rob Clark, Sean Paul, Sharat Masetty, Shawn Guo,
Wambui Karuga
Initialize hardware clock-gating registers on A640 and A650 GPUs.
I put the hwcg tables in adreno_device.c, but maybe it makes more
sense to keep them in a6xx_gpu.c? (this would allow switching a5xx
to use the gpulist too.. it isn't possible to include both a6xx.xml.h
and a5xx.xml.h in adreno_device.c)
Jonathan Marek (2):
drm/msm/a6xx: hwcg tables in gpulist
drm/msm/a6xx: add A640/A650 hwcg
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 140 ++-----------
drivers/gpu/drm/msm/adreno/adreno_device.c | 219 +++++++++++++++++++++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 +
4 files changed, 251 insertions(+), 123 deletions(-)
--
2.26.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 1/2] drm/msm/a6xx: hwcg tables in gpulist
2020-06-29 23:49 [PATCH 0/2] drm/msm/a6xx: add A640/A650 hwcg Jonathan Marek
@ 2020-06-29 23:49 ` Jonathan Marek
2020-06-29 23:49 ` [PATCH 2/2] drm/msm/a6xx: add A640/A650 hwcg Jonathan Marek
2020-06-30 3:36 ` [PATCH 0/2] " Rob Clark
2 siblings, 0 replies; 4+ messages in thread
From: Jonathan Marek @ 2020-06-29 23:49 UTC (permalink / raw)
To: freedreno
Cc: Rob Clark, Sean Paul, David Airlie, Daniel Vetter, Jordan Crouse,
Sharat Masetty, Akhil P Oommen, Shawn Guo,
AngeloGioacchino Del Regno, Wambui Karuga, Brian Masney,
open list:DRM DRIVER FOR MSM ADRENO GPU,
open list:DRM DRIVER FOR MSM ADRENO GPU, open list
This will allow supporting different hwcg tables for a6xx.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 129 ++-------------------
drivers/gpu/drm/msm/adreno/adreno_device.c | 111 ++++++++++++++++++
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++
3 files changed, 127 insertions(+), 120 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 3397e5e00d1c..6cd79166a94e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -151,117 +151,6 @@ static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
a6xx_flush(gpu, ring);
}
-static const struct {
- u32 offset;
- u32 value;
-} a6xx_hwcg[] = {
- {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
- {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
- {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
- {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
- {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
- {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
- {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
- {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
- {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
- {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
- {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
- {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
- {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
- {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
- {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
- {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
- {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
- {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
- {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
- {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
- {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
- {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
- {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
- {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
- {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
- {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}
-};
-
static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -270,6 +159,9 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
unsigned int i;
u32 val;
+ if (!adreno_gpu->info->hwcg)
+ return;
+
val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
/* Don't re-program the registers if they are already correct */
@@ -279,9 +171,10 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
/* Disable SP clock before programming HWCG registers */
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
- for (i = 0; i < ARRAY_SIZE(a6xx_hwcg); i++)
- gpu_write(gpu, a6xx_hwcg[i].offset,
- state ? a6xx_hwcg[i].value : 0);
+ for (i = 0; i < adreno_gpu->info->hwcg_count; i++) {
+ const struct adreno_reglist *reg = &adreno_gpu->info->hwcg[i];
+ gpu_write(gpu, reg->offset, state ? reg->value : 0);
+ }
/* Enable SP clock */
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
@@ -437,12 +330,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
- /*
- * enable hardware clockgating
- * For now enable clock gating only for a630
- */
- if (adreno_is_a630(adreno_gpu))
- a6xx_set_hwcg(gpu, true);
+ /* enable hardware clockgating */
+ a6xx_set_hwcg(gpu, true);
/* VBIF/GBIF start*/
if (adreno_is_a640(adreno_gpu) || adreno_is_a650(adreno_gpu)) {
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 7732f03d9e3a..f5f40bc3c113 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -7,6 +7,7 @@
*/
#include "adreno_gpu.h"
+#include "a6xx.xml.h"
#define ANY_ID 0xff
@@ -14,6 +15,114 @@ bool hang_debug = false;
MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
module_param_named(hang_debug, hang_debug, bool, 0600);
+static const struct adreno_reglist a630_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}
+};
+
static const struct adreno_info gpulist[] = {
{
.rev = ADRENO_REV(2, 0, 0, 0),
@@ -200,6 +309,8 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a630_zap.mdt",
+ .hwcg = a630_hwcg,
+ .hwcg_count = ARRAY_SIZE(a630_hwcg),
}, {
.rev = ADRENO_REV(6, 4, 0, ANY_ID),
.revn = 640,
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 2f5d2c3acc3a..316a4a327c61 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -68,6 +68,11 @@ struct adreno_gpu_funcs {
int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
};
+struct adreno_reglist {
+ u32 offset;
+ u32 value;
+};
+
struct adreno_info {
struct adreno_rev rev;
uint32_t revn;
@@ -78,6 +83,8 @@ struct adreno_info {
struct msm_gpu *(*init)(struct drm_device *dev);
const char *zapfw;
u32 inactive_period;
+ const struct adreno_reglist *hwcg;
+ u32 hwcg_count;
};
const struct adreno_info *adreno_info(struct adreno_rev rev);
--
2.26.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] drm/msm/a6xx: add A640/A650 hwcg
2020-06-29 23:49 [PATCH 0/2] drm/msm/a6xx: add A640/A650 hwcg Jonathan Marek
2020-06-29 23:49 ` [PATCH 1/2] drm/msm/a6xx: hwcg tables in gpulist Jonathan Marek
@ 2020-06-29 23:49 ` Jonathan Marek
2020-06-30 3:36 ` [PATCH 0/2] " Rob Clark
2 siblings, 0 replies; 4+ messages in thread
From: Jonathan Marek @ 2020-06-29 23:49 UTC (permalink / raw)
To: freedreno
Cc: Rob Clark, Sean Paul, David Airlie, Daniel Vetter,
Sharat Masetty, Jordan Crouse, Eric Anholt, Akhil P Oommen,
AngeloGioacchino Del Regno, Shawn Guo,
open list:DRM DRIVER FOR MSM ADRENO GPU,
open list:DRM DRIVER FOR MSM ADRENO GPU, open list
Initialize hardware clock-gating registers on A640 and A650 GPUs.
At least for A650, this solves some performance issues.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++-
drivers/gpu/drm/msm/adreno/adreno_device.c | 108 +++++++++++++++++++++
3 files changed, 124 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
index 47840b73cdda..f0498faf7d0b 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h
@@ -1996,6 +1996,14 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
#define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c
+#define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d
+
+#define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120
+
+#define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121
+
+#define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122
+
#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600
#define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 6cd79166a94e..891a21c5225e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -157,15 +157,20 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
unsigned int i;
- u32 val;
+ u32 val, clock_cntl_on;
if (!adreno_gpu->info->hwcg)
return;
+ if (adreno_is_a630(adreno_gpu))
+ clock_cntl_on = 0x8aa8aa02;
+ else
+ clock_cntl_on = 0x8aa8aa82;
+
val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
/* Don't re-program the registers if they are already correct */
- if ((!state && !val) || (state && (val == 0x8aa8aa02)))
+ if ((!state && !val) || (state && (val == clock_cntl_on)))
return;
/* Disable SP clock before programming HWCG registers */
@@ -179,7 +184,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
/* Enable SP clock */
gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
- gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? 0x8aa8aa02 : 0);
+ gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
}
static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
index f5f40bc3c113..b3149ff7fa9d 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -123,6 +123,110 @@ static const struct adreno_reglist a630_hwcg[] = {
{REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555}
};
+static const struct adreno_reglist a640_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+};
+
+static const struct adreno_reglist a650_hwcg[] = {
+ {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
+ {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
+ {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
+ {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
+ {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
+ {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
+ {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
+ {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
+ {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
+ {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
+ {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
+ {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
+ {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
+ {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
+ {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
+ {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
+ {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
+ {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
+ {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
+ {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
+ {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
+ {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
+ {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
+ {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
+ {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
+};
+
static const struct adreno_info gpulist[] = {
{
.rev = ADRENO_REV(2, 0, 0, 0),
@@ -323,6 +427,8 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a640_zap.mdt",
+ .hwcg = a640_hwcg,
+ .hwcg_count = ARRAY_SIZE(a640_hwcg),
}, {
.rev = ADRENO_REV(6, 5, 0, ANY_ID),
.revn = 650,
@@ -335,6 +441,8 @@ static const struct adreno_info gpulist[] = {
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
.init = a6xx_gpu_init,
.zapfw = "a650_zap.mdt",
+ .hwcg = a650_hwcg,
+ .hwcg_count = ARRAY_SIZE(a650_hwcg),
},
};
--
2.26.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 0/2] drm/msm/a6xx: add A640/A650 hwcg
2020-06-29 23:49 [PATCH 0/2] drm/msm/a6xx: add A640/A650 hwcg Jonathan Marek
2020-06-29 23:49 ` [PATCH 1/2] drm/msm/a6xx: hwcg tables in gpulist Jonathan Marek
2020-06-29 23:49 ` [PATCH 2/2] drm/msm/a6xx: add A640/A650 hwcg Jonathan Marek
@ 2020-06-30 3:36 ` Rob Clark
2 siblings, 0 replies; 4+ messages in thread
From: Rob Clark @ 2020-06-30 3:36 UTC (permalink / raw)
To: Jonathan Marek
Cc: freedreno, Akhil P Oommen, AngeloGioacchino Del Regno,
Bjorn Andersson, Brian Masney, Daniel Vetter, David Airlie,
open list:DRM DRIVER FOR MSM ADRENO GPU, Eric Anholt,
Jordan Crouse, open list:DRM DRIVER FOR MSM ADRENO GPU,
open list, Sean Paul, Sharat Masetty, Shawn Guo, Wambui Karuga
On Mon, Jun 29, 2020 at 4:49 PM Jonathan Marek <jonathan@marek.ca> wrote:
>
> Initialize hardware clock-gating registers on A640 and A650 GPUs.
>
> I put the hwcg tables in adreno_device.c, but maybe it makes more
> sense to keep them in a6xx_gpu.c? (this would allow switching a5xx
> to use the gpulist too.. it isn't possible to include both a6xx.xml.h
> and a5xx.xml.h in adreno_device.c)
yeah, I've kinda tried to avoid "crossing the streams".. maybe these
should move to adreno_gpu
BR,
-R
>
> Jonathan Marek (2):
> drm/msm/a6xx: hwcg tables in gpulist
> drm/msm/a6xx: add A640/A650 hwcg
>
> drivers/gpu/drm/msm/adreno/a6xx.xml.h | 8 +
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 140 ++-----------
> drivers/gpu/drm/msm/adreno/adreno_device.c | 219 +++++++++++++++++++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 +
> 4 files changed, 251 insertions(+), 123 deletions(-)
>
> --
> 2.26.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-06-30 3:35 UTC | newest]
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2020-06-29 23:49 ` [PATCH 2/2] drm/msm/a6xx: add A640/A650 hwcg Jonathan Marek
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