* [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver @ 2018-11-18 13:50 Neil Armstrong 2018-11-18 13:50 ` [PATCH v3 2/3] soc: amlogic: Add Meson Clock Measure driver Neil Armstrong ` (4 more replies) 0 siblings, 5 replies; 9+ messages in thread From: Neil Armstrong @ 2018-11-18 13:50 UTC (permalink / raw) To: khilman; +Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal clocks frequencies. The precision is determined by stepping into the duration until the counter overflows. The debugfs shows a pretty summary and each clock can be measured individually aswell. This patchset includes the dt-bindings, driver and the DT node added to the meson-gx dtsi. Changes since v2 at [2]: - Removed all reference to GX - Added compatibles for meson8/meson8b - Used Martin's suggestions on the divider naming - Added Martin's meson8/meson8b clk id table - Added Martin's fixes to support 32bit SoCs Changes since v1 at [1]: - fixed clock names - added summary in debugfs and moved indivudual clocks into a subdirectory - added the GX table to the match data [1] https://lkml.kernel.org/r/1530624110-4687-1-git-send-email-narmstrong@baylibre.com [2] https://lkml.kernel.org/r/20181114131627.17766-1-narmstrong@baylibre.com Neil Armstrong (3): dt-bindings: amlogic: Add Internal Clock Measurer bindings soc: amlogic: Add Meson Clock Measure driver ARM64: dts: meson-gx: Add Internal Clock Measurer node .../bindings/soc/amlogic/clk-measure.txt | 18 + arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 5 + drivers/soc/amlogic/Kconfig | 8 + drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-clk-measure.c | 350 ++++++++++++++++++ 5 files changed, 382 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt create mode 100644 drivers/soc/amlogic/meson-clk-measure.c -- 2.19.1 ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 2/3] soc: amlogic: Add Meson Clock Measure driver 2018-11-18 13:50 [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver Neil Armstrong @ 2018-11-18 13:50 ` Neil Armstrong 2018-11-18 14:04 ` Martin Blumenstingl 2018-11-18 13:50 ` [PATCH v3 3/3] ARM64: dts: meson-gx: Add Internal Clock Measurer node Neil Armstrong ` (3 subsequent siblings) 4 siblings, 1 reply; 9+ messages in thread From: Neil Armstrong @ 2018-11-18 13:50 UTC (permalink / raw) To: khilman Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel, Martin Blumenstingl The Amlogic Meson SoCs embeds a clock measurer IP to measure the internal clock paths frequencies. The precision is determined by stepping into the duration until the counter overflows. The debugfs slows a pretty summary and each clock can be measured individually aswell. Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- drivers/soc/amlogic/Kconfig | 8 + drivers/soc/amlogic/Makefile | 1 + drivers/soc/amlogic/meson-clk-measure.c | 350 ++++++++++++++++++++++++ 3 files changed, 359 insertions(+) create mode 100644 drivers/soc/amlogic/meson-clk-measure.c diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig index 2f282b472912..36633bb6c8bb 100644 --- a/drivers/soc/amlogic/Kconfig +++ b/drivers/soc/amlogic/Kconfig @@ -7,6 +7,14 @@ config MESON_CANVAS help Say yes to support the canvas IP for Amlogic SoCs. +config MESON_CLK_MEASURE + bool "Amlogic Meson SoC Clock Measure driver" + depends on ARCH_MESON || COMPILE_TEST + default ARCH_MESON + help + Say yes to support of Measuring a set of internal SoC clocks + from the debugfs interface. + config MESON_GX_SOCINFO bool "Amlogic Meson GX SoC Information driver" depends on ARCH_MESON || COMPILE_TEST diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile index 0ab16d35ac36..bf2d109f61e9 100644 --- a/drivers/soc/amlogic/Makefile +++ b/drivers/soc/amlogic/Makefile @@ -1,4 +1,5 @@ obj-$(CONFIG_MESON_CANVAS) += meson-canvas.o +obj-$(CONFIG_MESON_CLK_MEASURE) += meson-clk-measure.o obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o diff --git a/drivers/soc/amlogic/meson-clk-measure.c b/drivers/soc/amlogic/meson-clk-measure.c new file mode 100644 index 000000000000..daea191a66fa --- /dev/null +++ b/drivers/soc/amlogic/meson-clk-measure.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2018 BayLibre, SAS + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/bitfield.h> +#include <linux/seq_file.h> +#include <linux/debugfs.h> +#include <linux/regmap.h> + +#define MSR_CLK_DUTY 0x0 +#define MSR_CLK_REG0 0x4 +#define MSR_CLK_REG1 0x8 +#define MSR_CLK_REG2 0xc + +#define MSR_DURATION GENMASK(15, 0) +#define MSR_ENABLE BIT(16) +#define MSR_CONT BIT(17) /* continuous measurement */ +#define MSR_INTR BIT(18) /* interrupts */ +#define MSR_RUN BIT(19) +#define MSR_CLK_SRC GENMASK(26, 20) +#define MSR_BUSY BIT(31) + +#define MSR_VAL_MASK GENMASK(15, 0) + +#define DIV_MIN 32 +#define DIV_STEP 32 +#define DIV_MAX 640 + +#define CLK_MSR_MAX 128 + +struct meson_msr_id { + struct meson_msr *priv; + unsigned int id; + const char *name; +}; + +struct meson_msr { + struct regmap *regmap; + struct meson_msr_id msr_table[CLK_MSR_MAX]; +}; + +#define CLK_MSR_ID(__id, __name) \ + [__id] = {.id = __id, .name = __name,} + +static struct meson_msr_id clk_msr_m8[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee0"), + CLK_MSR_ID(1, "ring_osc_out_ee1"), + CLK_MSR_ID(2, "ring_osc_out_ee2"), + CLK_MSR_ID(3, "a9_ring_osck"), + CLK_MSR_ID(6, "vid_pll"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(11, "eth_rmii"), + CLK_MSR_ID(13, "amclk"), + CLK_MSR_ID(14, "fec_clk_0"), + CLK_MSR_ID(15, "fec_clk_1"), + CLK_MSR_ID(16, "fec_clk_2"), + CLK_MSR_ID(18, "a9_clk_div16"), + CLK_MSR_ID(19, "hdmi_sys"), + CLK_MSR_ID(20, "rtc_osc_clk_out"), + CLK_MSR_ID(21, "i2s_clk_in_src0"), + CLK_MSR_ID(22, "clk_rmii_from_pad"), + CLK_MSR_ID(23, "hdmi_ch0_tmds"), + CLK_MSR_ID(24, "lvds_fifo"), + CLK_MSR_ID(26, "sc_clk_int"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(30, "mpll_clk_test_out"), + CLK_MSR_ID(31, "audac_clkpi"), + CLK_MSR_ID(32, "vdac"), + CLK_MSR_ID(33, "sdhc_rx"), + CLK_MSR_ID(34, "sdhc_sd"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "pcm_sclk"), + CLK_MSR_ID(40, "pcm_mclk"), + CLK_MSR_ID(41, "eth_rx_tx"), + CLK_MSR_ID(42, "pwm_d"), + CLK_MSR_ID(43, "pwm_c"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "pcm2_sclk"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "pwm_f"), + CLK_MSR_ID(49, "pwm_e"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "usb_32k_alt"), + CLK_MSR_ID(61, "gpio"), + CLK_MSR_ID(62, "vid2_pll"), + CLK_MSR_ID(63, "mipi_csi_cfg"), +}; + +static struct meson_msr_id clk_msr_gx[CLK_MSR_MAX] = { + CLK_MSR_ID(0, "ring_osc_out_ee_0"), + CLK_MSR_ID(1, "ring_osc_out_ee_1"), + CLK_MSR_ID(2, "ring_osc_out_ee_2"), + CLK_MSR_ID(3, "a53_ring_osc"), + CLK_MSR_ID(4, "gp0_pll"), + CLK_MSR_ID(6, "enci"), + CLK_MSR_ID(7, "clk81"), + CLK_MSR_ID(8, "encp"), + CLK_MSR_ID(9, "encl"), + CLK_MSR_ID(10, "vdac"), + CLK_MSR_ID(11, "rgmii_tx"), + CLK_MSR_ID(12, "pdm"), + CLK_MSR_ID(13, "amclk"), + CLK_MSR_ID(14, "fec_0"), + CLK_MSR_ID(15, "fec_1"), + CLK_MSR_ID(16, "fec_2"), + CLK_MSR_ID(17, "sys_pll_div16"), + CLK_MSR_ID(18, "sys_cpu_div16"), + CLK_MSR_ID(19, "hdmitx_sys"), + CLK_MSR_ID(20, "rtc_osc_out"), + CLK_MSR_ID(21, "i2s_in_src0"), + CLK_MSR_ID(22, "eth_phy_ref"), + CLK_MSR_ID(23, "hdmi_todig"), + CLK_MSR_ID(26, "sc_int"), + CLK_MSR_ID(28, "sar_adc"), + CLK_MSR_ID(31, "mpll_test_out"), + CLK_MSR_ID(32, "vdec"), + CLK_MSR_ID(35, "mali"), + CLK_MSR_ID(36, "hdmi_tx_pixel"), + CLK_MSR_ID(37, "i958"), + CLK_MSR_ID(38, "vdin_meas"), + CLK_MSR_ID(39, "pcm_sclk"), + CLK_MSR_ID(40, "pcm_mclk"), + CLK_MSR_ID(41, "eth_rx_or_rmii"), + CLK_MSR_ID(42, "mp0_out"), + CLK_MSR_ID(43, "fclk_div5"), + CLK_MSR_ID(44, "pwm_b"), + CLK_MSR_ID(45, "pwm_a"), + CLK_MSR_ID(46, "vpu"), + CLK_MSR_ID(47, "ddr_dpll_pt"), + CLK_MSR_ID(48, "mp1_out"), + CLK_MSR_ID(49, "mp2_out"), + CLK_MSR_ID(50, "mp3_out"), + CLK_MSR_ID(51, "nand_core"), + CLK_MSR_ID(52, "sd_emmc_b"), + CLK_MSR_ID(53, "sd_emmc_a"), + CLK_MSR_ID(55, "vid_pll_div_out"), + CLK_MSR_ID(56, "cci"), + CLK_MSR_ID(57, "wave420l_c"), + CLK_MSR_ID(58, "wave420l_b"), + CLK_MSR_ID(59, "hcodec"), + CLK_MSR_ID(60, "alt_32k"), + CLK_MSR_ID(61, "gpio_msr"), + CLK_MSR_ID(62, "hevc"), + CLK_MSR_ID(66, "vid_lock"), + CLK_MSR_ID(70, "pwm_f"), + CLK_MSR_ID(71, "pwm_e"), + CLK_MSR_ID(72, "pwm_d"), + CLK_MSR_ID(73, "pwm_c"), + CLK_MSR_ID(75, "aoclkx2_int"), + CLK_MSR_ID(76, "aoclk_int"), + CLK_MSR_ID(77, "rng_ring_osc_0"), + CLK_MSR_ID(78, "rng_ring_osc_1"), + CLK_MSR_ID(79, "rng_ring_osc_2"), + CLK_MSR_ID(80, "rng_ring_osc_3"), + CLK_MSR_ID(81, "vapb"), + CLK_MSR_ID(82, "ge2d"), +}; + +static int meson_measure_id(struct meson_msr_id *clk_msr_id, + unsigned int duration) +{ + struct meson_msr *priv = clk_msr_id->priv; + unsigned int val; + int ret; + + regmap_write(priv->regmap, MSR_CLK_REG0, 0); + + /* Set measurement duration */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_DURATION, + FIELD_PREP(MSR_DURATION, duration - 1)); + + /* Set ID */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_CLK_SRC, + FIELD_PREP(MSR_CLK_SRC, clk_msr_id->id)); + + /* Enable & Start */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, + MSR_RUN | MSR_ENABLE, + MSR_RUN | MSR_ENABLE); + + ret = regmap_read_poll_timeout(priv->regmap, MSR_CLK_REG0, + val, !(val & MSR_BUSY), 10, 10000); + if (ret) + return ret; + + /* Disable */ + regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_ENABLE, 0); + + /* Get the value in multiple of gate time counts */ + regmap_read(priv->regmap, MSR_CLK_REG2, &val); + + if (val >= MSR_VAL_MASK) + return -EINVAL; + + return DIV_ROUND_CLOSEST_ULL((val & MSR_VAL_MASK) * 1000000ULL, + duration); +} + +static int meson_measure_best_id(struct meson_msr_id *clk_msr_id, + unsigned int *precision) +{ + unsigned int duration = DIV_MAX; + int ret; + + /* Start from max duration and down to min duration */ + do { + ret = meson_measure_id(clk_msr_id, duration); + if (ret >= 0) + *precision = (2 * 1000000) / duration; + else + duration -= DIV_STEP; + } while (duration >= DIV_MIN && ret == -EINVAL); + + return ret; +} + +static int clk_msr_show(struct seq_file *s, void *data) +{ + struct meson_msr_id *clk_msr_id = s->private; + unsigned int precision = 0; + int val; + + val = meson_measure_best_id(clk_msr_id, &precision); + if (val < 0) + return val; + + seq_printf(s, "%d\t+/-%dHz\n", val, precision); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(clk_msr); + +static int clk_msr_summary_show(struct seq_file *s, void *data) +{ + struct meson_msr_id *msr_table = s->private; + unsigned int precision = 0; + int val, i; + + seq_puts(s, " clock rate precision\n"); + seq_puts(s, "---------------------------------------------\n"); + + for (i = 0 ; i < CLK_MSR_MAX ; ++i) { + if (!msr_table[i].name) + continue; + + val = meson_measure_best_id(&msr_table[i], &precision); + if (val < 0) + return val; + + seq_printf(s, " %-20s %10d +/-%dHz\n", + msr_table[i].name, val, precision); + } + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(clk_msr_summary); + +static const struct regmap_config meson_clk_msr_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .max_register = MSR_CLK_REG2, +}; + +static int meson_msr_probe(struct platform_device *pdev) +{ + const struct meson_msr_id *match_data; + struct meson_msr *priv; + struct resource *res; + struct dentry *root, *clks; + void __iomem *base; + int i; + + priv = devm_kzalloc(&pdev->dev, sizeof(struct meson_msr), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + match_data = device_get_match_data(&pdev->dev); + if (!match_data) { + dev_err(&pdev->dev, "failed to get match data\n"); + return -ENODEV; + } + + memcpy(priv->msr_table, match_data, sizeof(priv->msr_table)); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(base)) { + dev_err(&pdev->dev, "io resource mapping failed\n"); + return PTR_ERR(base); + } + + priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, + &meson_clk_msr_regmap_config); + if (IS_ERR(priv->regmap)) + return PTR_ERR(priv->regmap); + + root = debugfs_create_dir("meson-clk-msr", NULL); + clks = debugfs_create_dir("clks", root); + + debugfs_create_file("measure_summary", 0444, root, + priv->msr_table, &clk_msr_summary_fops); + + for (i = 0 ; i < CLK_MSR_MAX ; ++i) { + if (!priv->msr_table[i].name) + continue; + + priv->msr_table[i].priv = priv; + + debugfs_create_file(priv->msr_table[i].name, 0444, clks, + &priv->msr_table[i], &clk_msr_fops); + } + + return 0; +} + +static const struct of_device_id meson_msr_match_table[] = { + { + .compatible = "amlogic,meson-gx-clk-measure", + .data = (void *)clk_msr_gx, + }, + { + .compatible = "amlogic,meson8-clk-measure", + .data = (void *)clk_msr_m8, + }, + { + .compatible = "amlogic,meson8b-clk-measure", + .data = (void *)clk_msr_m8, + }, + { /* sentinel */ } +}; + +static struct platform_driver meson_msr_driver = { + .probe = meson_msr_probe, + .driver = { + .name = "meson_msr", + .of_match_table = meson_msr_match_table, + }, +}; +builtin_platform_driver(meson_msr_driver); -- 2.19.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 2/3] soc: amlogic: Add Meson Clock Measure driver 2018-11-18 13:50 ` [PATCH v3 2/3] soc: amlogic: Add Meson Clock Measure driver Neil Armstrong @ 2018-11-18 14:04 ` Martin Blumenstingl 0 siblings, 0 replies; 9+ messages in thread From: Martin Blumenstingl @ 2018-11-18 14:04 UTC (permalink / raw) To: Neil Armstrong; +Cc: khilman, linux-amlogic, linux-arm-kernel, linux-kernel On Sun, Nov 18, 2018 at 2:50 PM Neil Armstrong <narmstrong@baylibre.com> wrote: > > The Amlogic Meson SoCs embeds a clock measurer IP to measure the internal > clock paths frequencies. > The precision is determined by stepping into the duration until the counter > overflows. > The debugfs slows a pretty summary and each clock can be measured > individually aswell. > > Cc: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> I have successfully tested it on Odroid-C1: Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 3/3] ARM64: dts: meson-gx: Add Internal Clock Measurer node 2018-11-18 13:50 [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver Neil Armstrong 2018-11-18 13:50 ` [PATCH v3 2/3] soc: amlogic: Add Meson Clock Measure driver Neil Armstrong @ 2018-11-18 13:50 ` Neil Armstrong 2018-11-18 14:00 ` Martin Blumenstingl 2018-11-18 13:53 ` [PATCH v3 1/3] dt-bindings: amlogic: Add Internal Clock Measurer bindings Neil Armstrong ` (2 subsequent siblings) 4 siblings, 1 reply; 9+ messages in thread From: Neil Armstrong @ 2018-11-18 13:50 UTC (permalink / raw) To: khilman; +Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal clock paths frequencies. This patch adds the node in the top-level meson-gx dtsi. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index f1e5cdbade5e..ed336c7a98a7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -262,6 +262,11 @@ status = "disabled"; }; + clock-measure@8758 { + compatible = "amlogic,meson-gx-clk-measure"; + reg = <0x0 0x8758 0x0 0x10>; + }; + i2c_B: i2c@87c0 { compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; reg = <0x0 0x087c0 0x0 0x20>; -- 2.19.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 3/3] ARM64: dts: meson-gx: Add Internal Clock Measurer node 2018-11-18 13:50 ` [PATCH v3 3/3] ARM64: dts: meson-gx: Add Internal Clock Measurer node Neil Armstrong @ 2018-11-18 14:00 ` Martin Blumenstingl 0 siblings, 0 replies; 9+ messages in thread From: Martin Blumenstingl @ 2018-11-18 14:00 UTC (permalink / raw) To: Neil Armstrong; +Cc: khilman, linux-amlogic, linux-kernel, linux-arm-kernel On Sun, Nov 18, 2018 at 2:51 PM Neil Armstrong <narmstrong@baylibre.com> wrote: > > The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal > clock paths frequencies. > This patch adds the node in the top-level meson-gx dtsi. > > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v3 1/3] dt-bindings: amlogic: Add Internal Clock Measurer bindings 2018-11-18 13:50 [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver Neil Armstrong 2018-11-18 13:50 ` [PATCH v3 2/3] soc: amlogic: Add Meson Clock Measure driver Neil Armstrong 2018-11-18 13:50 ` [PATCH v3 3/3] ARM64: dts: meson-gx: Add Internal Clock Measurer node Neil Armstrong @ 2018-11-18 13:53 ` Neil Armstrong 2018-11-26 16:05 ` Rob Herring 2018-11-18 14:05 ` [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver Martin Blumenstingl 2018-11-29 0:57 ` Kevin Hilman 4 siblings, 1 reply; 9+ messages in thread From: Neil Armstrong @ 2018-11-18 13:53 UTC (permalink / raw) To: devicetree; +Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel The Amlogic Meson SoCs embeds a clock measurer IP to measure the internal clock paths frequencies. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> --- Rob, I didn't take your v2 Reviewed-by since I changed the compatible list, tell me if i can still keep the tag. Thanks, Neil .../bindings/soc/amlogic/clk-measure.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt diff --git a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt new file mode 100644 index 000000000000..205a54bcd7c7 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt @@ -0,0 +1,18 @@ +Amlogic Internal Clock Measurer +=============================== + +The Amlogic SoCs contains an IP to measure the internal clocks. +The precision is multiple of MHz, useful to debug the clock states. + +Required properties: +- compatible: Shall contain one of the following : + "amlogic,meson-gx-clk-measure" for GX SoCs + "amlogic,meson8-clk-measure" for Meson8 SoCs + "amlogic,meson8b-clk-measure" for Meson8b SoCs +- reg: base address and size of the Clock Measurer register space. + +Example: + clock-measure@8758 { + compatible = "amlogic,meson-gx-clk-measure"; + reg = <0x0 0x8758 0x0 0x10>; + }; -- 2.19.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/3] dt-bindings: amlogic: Add Internal Clock Measurer bindings 2018-11-18 13:53 ` [PATCH v3 1/3] dt-bindings: amlogic: Add Internal Clock Measurer bindings Neil Armstrong @ 2018-11-26 16:05 ` Rob Herring 0 siblings, 0 replies; 9+ messages in thread From: Rob Herring @ 2018-11-26 16:05 UTC (permalink / raw) To: Neil Armstrong; +Cc: devicetree, linux-amlogic, linux-arm-kernel, linux-kernel On Sun, Nov 18, 2018 at 02:53:10PM +0100, Neil Armstrong wrote: > The Amlogic Meson SoCs embeds a clock measurer IP to measure the internal > clock paths frequencies. > > Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> > --- > Rob, > > I didn't take your v2 Reviewed-by since I changed the compatible list, > tell me if i can still keep the tag. Reviewed-by: Rob Herring <robh@kernel.org> > > Thanks, > Neil > > .../bindings/soc/amlogic/clk-measure.txt | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver 2018-11-18 13:50 [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver Neil Armstrong ` (2 preceding siblings ...) 2018-11-18 13:53 ` [PATCH v3 1/3] dt-bindings: amlogic: Add Internal Clock Measurer bindings Neil Armstrong @ 2018-11-18 14:05 ` Martin Blumenstingl 2018-11-29 0:57 ` Kevin Hilman 4 siblings, 0 replies; 9+ messages in thread From: Martin Blumenstingl @ 2018-11-18 14:05 UTC (permalink / raw) To: Neil Armstrong; +Cc: khilman, linux-amlogic, linux-kernel, linux-arm-kernel On Sun, Nov 18, 2018 at 2:51 PM Neil Armstrong <narmstrong@baylibre.com> wrote: > > The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal > clocks frequencies. > The precision is determined by stepping into the duration until the counter > overflows. > The debugfs shows a pretty summary and each clock can be measured > individually aswell. > > This patchset includes the dt-bindings, driver and the DT node added to the > meson-gx dtsi. > > Changes since v2 at [2]: > - Removed all reference to GX > - Added compatibles for meson8/meson8b > - Used Martin's suggestions on the divider naming > - Added Martin's meson8/meson8b clk id table > - Added Martin's fixes to support 32bit SoCs thank you for the updates Neil! here's the output from Odroid-C1: # cat /sys/kernel/debug/meson-clk-msr/measure_summary clock rate precision --------------------------------------------- ring_osc_out_ee0 0 +/-3125Hz ring_osc_out_ee1 0 +/-3125Hz ring_osc_out_ee2 0 +/-3125Hz a9_ring_osck 0 +/-3125Hz vid_pll 148497596 +/-4807Hz clk81 159372396 +/-5208Hz encp 148497596 +/-4807Hz encl 0 +/-3125Hz eth_rmii 125000000 +/-3906Hz amclk 0 +/-3125Hz fec_clk_0 0 +/-3125Hz fec_clk_1 0 +/-3125Hz fec_clk_2 0 +/-3125Hz a9_clk_div16 74998438 +/-3125Hz hdmi_sys 0 +/-3125Hz rtc_osc_clk_out 32813 +/-3125Hz i2s_clk_in_src0 0 +/-3125Hz clk_rmii_from_pad 0 +/-3125Hz hdmi_ch0_tmds 74248438 +/-3125Hz lvds_fifo 0 +/-3125Hz sc_clk_int 0 +/-3125Hz sar_adc 1140625 +/-3125Hz mpll_clk_test_out 0 +/-3125Hz audac_clkpi 0 +/-3125Hz vdac 0 +/-3125Hz sdhc_rx 0 +/-3125Hz sdhc_sd 0 +/-3125Hz mali 0 +/-3125Hz hdmi_tx_pixel 74250000 +/-3125Hz vdin_meas 0 +/-3125Hz pcm_sclk 0 +/-3125Hz pcm_mclk 0 +/-3125Hz eth_rx_tx 0 +/-3125Hz pwm_d 0 +/-3125Hz pwm_c 24000000 +/-3125Hz pwm_b 0 +/-3125Hz pwm_a 0 +/-3125Hz pcm2_sclk 0 +/-3125Hz ddr_dpll_pt 0 +/-3125Hz pwm_f 0 +/-3125Hz pwm_e 0 +/-3125Hz hcodec 0 +/-3125Hz usb_32k_alt 0 +/-3125Hz gpio 0 +/-3125Hz vid2_pll 0 +/-3125Hz mipi_csi_cfg 0 +/-3125Hz ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver 2018-11-18 13:50 [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver Neil Armstrong ` (3 preceding siblings ...) 2018-11-18 14:05 ` [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver Martin Blumenstingl @ 2018-11-29 0:57 ` Kevin Hilman 4 siblings, 0 replies; 9+ messages in thread From: Kevin Hilman @ 2018-11-29 0:57 UTC (permalink / raw) To: Neil Armstrong Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel Neil Armstrong <narmstrong@baylibre.com> writes: > The Amlogic Meson GX SoCs embeds a clock measurer IP to measure the internal > clocks frequencies. > The precision is determined by stepping into the duration until the counter > overflows. > The debugfs shows a pretty summary and each clock can be measured > individually aswell. > > This patchset includes the dt-bindings, driver and the DT node added to the > meson-gx dtsi. Queued for v4.21... [...] > Neil Armstrong (3): > dt-bindings: amlogic: Add Internal Clock Measurer bindings > soc: amlogic: Add Meson Clock Measure driver ...on branch v4.21/drivers and... > ARM64: dts: meson-gx: Add Internal Clock Measurer node ...on branch v4.21/dt64, Thanks, Kevin ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-11-29 0:57 UTC | newest] Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-11-18 13:50 [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver Neil Armstrong 2018-11-18 13:50 ` [PATCH v3 2/3] soc: amlogic: Add Meson Clock Measure driver Neil Armstrong 2018-11-18 14:04 ` Martin Blumenstingl 2018-11-18 13:50 ` [PATCH v3 3/3] ARM64: dts: meson-gx: Add Internal Clock Measurer node Neil Armstrong 2018-11-18 14:00 ` Martin Blumenstingl 2018-11-18 13:53 ` [PATCH v3 1/3] dt-bindings: amlogic: Add Internal Clock Measurer bindings Neil Armstrong 2018-11-26 16:05 ` Rob Herring 2018-11-18 14:05 ` [PATCH v3 0/3] Add Amlogic Meson GX SoC Clock Measure Driver Martin Blumenstingl 2018-11-29 0:57 ` Kevin Hilman
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