From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, bhupesh.linux@gmail.com,
agross@kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, maz@kernel.org,
quic_mkshah@quicinc.com, linux-gpio@vger.kernel.org,
linus.walleij@linaro.org, robh+dt@kernel.org,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh@kernel.org>
Subject: Re: [PATCH v2 3/4] arm64: dts: qcom: sm8150: Add pdc interrupt controller node
Date: Thu, 17 Mar 2022 11:21:46 +0530 [thread overview]
Message-ID: <CAH=2NtzHfqiFi8NKqQ=m24buzVsMT392ObOQ6ahT5BXB=fv6Hw@mail.gmail.com> (raw)
In-Reply-To: <YjC8bfY2U1WyV8FY@builder.lan>
Hi Bjorn,
Thanks for your review.
On Tue, 15 Mar 2022 at 21:48, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
>
> On Sat 26 Feb 12:40 CST 2022, Bhupesh Sharma wrote:
>
> > Add pdc interrupt controller for sm8150.
> >
> > Cc: Maulik Shah <quic_mkshah@quicinc.com>
> > Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Cc: Vinod Koul <vkoul@kernel.org>
> > Cc: Rob Herring <robh@kernel.org>
> > Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
> > ---
> > arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > index 6012322a5984..aaeacd379460 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > @@ -1626,6 +1626,16 @@ system-cache-controller@9200000 {
> > interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> > };
> >
> > + pdc: interrupt-controller@b220000 {
> > + compatible = "qcom,sm8150-pdc", "qcom,pdc";
> > + reg = <0 0x0b220000 0 0x400>;
> > + qcom,pdc-ranges = <0 480 94>, <94 609 31>,
> > + <125 63 1>;
>
> When I look at the platform documentation I get the impression that this
> should be: <0 480 94>, <94 609 32>;
>
> Can you confirm that the last signal is correctly described?
Yes, I confirmed by double checking the entries in downstream 'pdc-sm8150.c'.
The pdc pins in the 2nd range start from 94 and end at 124, so a total
of 31 entries, but both 94 and 124 pins included.
Or, am I missing something?
Thanks,
Bhupesh
> > + #interrupt-cells = <2>;
> > + interrupt-parent = <&intc>;
> > + interrupt-controller;
> > + };
> > +
> > ufs_mem_hc: ufshc@1d84000 {
> > compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
> > "jedec,ufs-2.0";
> > --
> > 2.35.1
> >
next prev parent reply other threads:[~2022-03-17 6:13 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-26 18:40 [PATCH v2 0/4] Add support for PDC interrupt controller for sm8150 Bhupesh Sharma
2022-02-26 18:40 ` [PATCH v2 1/4] dt-bindings: qcom,pdc: Add compatible for SM8150 Bhupesh Sharma
2022-03-15 16:09 ` Bjorn Andersson
2022-04-17 23:10 ` Linus Walleij
2022-02-26 18:40 ` [PATCH v2 2/4] pinctrl: qcom: sm8150: Specify PDC map Bhupesh Sharma
2022-03-15 16:10 ` Bjorn Andersson
2022-04-17 23:11 ` Linus Walleij
2022-02-26 18:40 ` [PATCH v2 3/4] arm64: dts: qcom: sm8150: Add pdc interrupt controller node Bhupesh Sharma
2022-03-15 16:18 ` Bjorn Andersson
2022-03-17 5:51 ` Bhupesh Sharma [this message]
2022-03-24 12:25 ` Bjorn Andersson
2022-02-26 18:40 ` [PATCH v2 4/4] arm64: dts: qcom: sm8150: Add PDC as the interrupt parent for tlmm Bhupesh Sharma
2022-03-15 16:19 ` Bjorn Andersson
2022-03-15 1:06 ` [PATCH v2 0/4] Add support for PDC interrupt controller for sm8150 Linus Walleij
2022-03-15 3:45 ` Vinod Koul
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