[PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

[PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

[Florian Eckert]

Changes v2:
- Update SPDX short identifier
- Remove gpio-keys-polled device moved to arch/x86/platform
- Fix styling
- Use spinnlock only there where it is useful
- Removed useless output on driver load
- Do bit manipulation later not on IO
- Add additional GPIOs handling mpci2_reset and mpcie3_reset.
- Add name to GPIOs exported via sysfs

Changes v3:
- Add a new platform device for the frontpanel push button.
- Get global variables from the heap
- Fix errors/warnings generated by ./scripts/checkpatch.pl

Changes v4:
gpio-apu.c
- Move bit shifting out of spinnlock
- Change declaration of int to unsigned int
- Remove redundant blank line
- Use dmi table callback
- Remove noise
pcengines-apu-platform.c
- Move platform device to drivers/platform/x86
- Remove needless include
- Add dmi information so that this device is only present on APU2
  APU3 boards from PC Engines

Changes v5:
gpio-apu.c
- Remove GPIO_GENERIC select from Kconfig
- Make gpio_chip real member of apu_gpio_pdata
- Use BIT macro for get_data and get_dir functions
- Pass platform data to devm_gpiochip_add_data to get data
  per-instance state container
- Remove DEVNAME define
- Remove platfrom_device member from apu_gpio_pdata this
- Clean up init function
- Remove MODULE_ALIAS

Until now it was not possible to get more information to detect the
MMIO_BASE address from the ACPI subsystem.

Florian Eckert (2):
  gpio: Add driver for PC Engines APU boards
  platform: Add reset button device for PC Engines APU boards

 drivers/gpio/Kconfig                          |   7 +
 drivers/gpio/Makefile                         |   1 +
 drivers/gpio/gpio-apu.c                       | 288 ++++++++++++++++++++++++++
 drivers/platform/x86/Kconfig                  |  11 +
 drivers/platform/x86/Makefile                 |   1 +
 drivers/platform/x86/pcengines-apu-platform.c | 114 ++++++++++
 6 files changed, 422 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c
 create mode 100644 drivers/platform/x86/pcengines-apu-platform.c

-- 
2.11.0

[PATCH v5 1/2] gpio: Add driver for PC Engines APU boards

[Florian Eckert]

Add a new device driver "gpio-apu" which will handle the GPIOs on APU2
and APU3 devices from PC Engines.

APU2 (https://pcengines.ch/schema/apu2c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line

APU3 (https://pcengines.ch/schema/apu3c.pdf page 7):
- G32 is "button_reset" connected to the smd-button on the frontpanel
- G50 is "mpcie2_reset" connected to mPCIe2 reset line
- G51 is "mpcie3_reset" connected to mPCIe3 reset line
- G33 is "simswap" connected to SIM switch IC to swap the SIM between
  mPCIe2 and mPCIe3 slot

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
 drivers/gpio/Kconfig    |   7 ++
 drivers/gpio/Makefile   |   1 +
 drivers/gpio/gpio-apu.c | 288 ++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 296 insertions(+)
 create mode 100644 drivers/gpio/gpio-apu.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 833a1b51c948..e89937f6051e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -117,6 +117,13 @@ config GPIO_AMDPT
 	  driver for GPIO functionality on Promontory IOHub
 	  Require ACPI ASL code to enumerate as a platform device.
 
+config GPIO_APU
+	tristate "PC Engines APU2/APU3 GPIO support"
+	depends on X86
+	help
+	  Say Y here to support GPIO functionality on APU2/APU3 boards
+	  from PC Engines.
+
 config GPIO_ASPEED
 	tristate "Aspeed GPIO support"
 	depends on (ARCH_ASPEED || COMPILE_TEST) && OF_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 671c4477c951..9c27523fb189 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_GPIO_ALTERA)  	+= gpio-altera.o
 obj-$(CONFIG_GPIO_ALTERA_A10SR)	+= gpio-altera-a10sr.o
 obj-$(CONFIG_GPIO_AMD8111)	+= gpio-amd8111.o
 obj-$(CONFIG_GPIO_AMDPT)	+= gpio-amdpt.o
+obj-$(CONFIG_GPIO_APU)		+= gpio-apu.o
 obj-$(CONFIG_GPIO_ARIZONA)	+= gpio-arizona.o
 obj-$(CONFIG_GPIO_ATH79)	+= gpio-ath79.o
 obj-$(CONFIG_GPIO_ASPEED)	+= gpio-aspeed.o
diff --git a/drivers/gpio/gpio-apu.c b/drivers/gpio/gpio-apu.c
new file mode 100644
index 000000000000..609972d11847
--- /dev/null
+++ b/drivers/gpio/gpio-apu.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0
+/* PC Engines APU2/APU3 GPIO device driver
+ *
+ * Copyright (C) 2018 Florian Eckert <fe@dev.tdt.de>
+ */
+
+#include <linux/bits.h>
+#include <linux/dmi.h>
+#include <linux/err.h>
+#include <linux/gpio/driver.h>
+#include <linux/input.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#define APU_FCH_ACPI_MMIO_BASE 0xFED80000
+#define APU_FCH_GPIO_BASE      (APU_FCH_ACPI_MMIO_BASE + 0x1500)
+#define APU_GPIO_BIT_RD        16
+#define APU_GPIO_BIT_WR        22
+#define APU_GPIO_BIT_DIR       23
+
+struct apu_gpio_pdata {
+	struct gpio_chip chip;
+	unsigned long *offset;		/* base register offset */
+	void __iomem **addr;		/* remapped iomem addresses */
+	spinlock_t lock;		/* lock register access */
+};
+
+static struct platform_device *apu_gpio_pdev;
+
+/* APU2 */
+static unsigned long apu2_gpio_offset[] = {
+	APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+	APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+	APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+};
+static const char * const apu2_gpio_names[] = {
+	"button_reset",
+	"mpcie2_reset",
+	"mpcie3_reset",
+};
+
+/* APU3 */
+static unsigned long apu3_gpio_offset[] = {
+	APU_FCH_GPIO_BASE + 89 * sizeof(u32),
+	APU_FCH_GPIO_BASE + 67 * sizeof(u32),
+	APU_FCH_GPIO_BASE + 66 * sizeof(u32),
+	APU_FCH_GPIO_BASE + 90 * sizeof(u32),
+};
+static const char * const apu3_gpio_names[] = {
+	"button_reset",
+	"mpcie2_reset",
+	"mpcie3_reset",
+	"simswap",
+};
+
+static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int offset)
+{
+	u32 val;
+	struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+	spin_lock(&apu_gpio->lock);
+
+	val = ~ioread32(apu_gpio->addr[offset]);
+
+	spin_unlock(&apu_gpio->lock);
+
+	return !!(val & BIT(APU_GPIO_BIT_DIR));
+}
+
+static int gpio_apu_dir_in(struct gpio_chip *chip, unsigned int offset)
+{
+	u32 val;
+	struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+	spin_lock(&apu_gpio->lock);
+
+	val = ioread32(apu_gpio->addr[offset]);
+	val &= ~BIT(APU_GPIO_BIT_DIR);
+	iowrite32(val, apu_gpio->addr[offset]);
+
+	spin_unlock(&apu_gpio->lock);
+
+	return 0;
+}
+
+static int gpio_apu_dir_out(struct gpio_chip *chip, unsigned int offset,
+		int value)
+{
+	u32 val;
+	struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+	spin_lock(&apu_gpio->lock);
+
+	val = ioread32(apu_gpio->addr[offset]);
+	val |= BIT(APU_GPIO_BIT_DIR);
+	iowrite32(val, apu_gpio->addr[offset]);
+
+	spin_unlock(&apu_gpio->lock);
+
+	return 0;
+}
+
+static int gpio_apu_get_data(struct gpio_chip *chip, unsigned int offset)
+{
+	u32 val;
+	struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+	spin_lock(&apu_gpio->lock);
+
+	val = ioread32(apu_gpio->addr[offset]);
+
+	spin_unlock(&apu_gpio->lock);
+
+	return !!(val & BIT(APU_GPIO_BIT_RD));
+}
+
+static void gpio_apu_set_data(struct gpio_chip *chip, unsigned int offset,
+		int value)
+{
+	u32 val;
+	struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
+
+	spin_lock(&apu_gpio->lock);
+
+	val = ioread32(apu_gpio->addr[offset]);
+	if (value)
+		val |= BIT(APU_GPIO_BIT_WR);
+	else
+		val &= ~BIT(APU_GPIO_BIT_WR);
+	iowrite32(val, apu_gpio->addr[offset]);
+
+	spin_unlock(&apu_gpio->lock);
+}
+
+static const struct dmi_system_id apu2_gpio_dmi_table[] __initconst = {
+	/* PC Engines APU2 with "Legacy" bios < 4.0.8 */
+	{
+		.ident = "apu2",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "APU2")
+		}
+	},
+	/* PC Engines APU2 with "Legacy" bios >= 4.0.8 */
+	{
+		.ident = "apu2",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "apu2")
+		}
+	},
+	/* PC Engines APU2 with "Mainline" bios */
+	{
+		.ident = "apu2",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
+		}
+	},
+	{}
+}
+MODULE_DEVICE_TABLE(dmi, apu2_gpio_dmi_table);
+
+static const struct dmi_system_id apu3_gpio_dmi_table[] __initconst = {
+	/* PC Engines APU3 with "Legacy" bios < 4.0.8 */
+	{
+		.ident = "apu3",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "APU3")
+		}
+	},
+	/* PC Engines APU3 with "Legacy" bios >= 4.0.8 */
+	{
+		.ident = "apu3",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "apu3")
+		}
+	},
+	/* PC Engines APU3 with "Mainline" bios */
+	{
+		.ident = "apu3",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu3")
+		}
+	},
+	{}
+};
+MODULE_DEVICE_TABLE(dmi, apu3_gpio_dmi_table);
+
+static int __init apu_gpio_probe(struct platform_device *pdev)
+{
+	unsigned int i;
+	struct apu_gpio_pdata *apu_gpio;
+
+	apu_gpio = devm_kzalloc(&pdev->dev, sizeof(*apu_gpio), GFP_KERNEL);
+	if (!apu_gpio)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, apu_gpio);
+	spin_lock_init(&apu_gpio->lock);
+
+	apu_gpio->chip.label = KBUILD_MODNAME;
+	apu_gpio->chip.base = 20;
+	apu_gpio->chip.get_direction = gpio_apu_get_dir;
+	apu_gpio->chip.direction_input = gpio_apu_dir_in;
+	apu_gpio->chip.direction_output = gpio_apu_dir_out;
+	apu_gpio->chip.get = gpio_apu_get_data;
+	apu_gpio->chip.set = gpio_apu_set_data;
+
+	if (dmi_check_system(apu3_gpio_dmi_table)) {
+		apu_gpio->addr = devm_kzalloc(&pdev->dev,
+				sizeof(apu3_gpio_offset),
+				GFP_KERNEL);
+
+		if (!apu_gpio->addr)
+			return -ENOMEM;
+
+		apu_gpio->offset = apu3_gpio_offset;
+		apu_gpio->chip.names = apu3_gpio_names;
+		apu_gpio->chip.ngpio = ARRAY_SIZE(apu3_gpio_offset);
+		for (i = 0; i < ARRAY_SIZE(apu3_gpio_offset); i++) {
+			apu_gpio->addr[i] = devm_ioremap(&pdev->dev,
+					apu_gpio->offset[i], sizeof(u32));
+			if (!apu_gpio->addr[i])
+				return -ENOMEM;
+		}
+	} else if (dmi_check_system(apu2_gpio_dmi_table)) {
+		apu_gpio->addr = devm_kzalloc(&pdev->dev,
+				sizeof(apu2_gpio_offset),
+				GFP_KERNEL);
+
+		if (!apu_gpio->addr)
+			return -ENOMEM;
+
+		apu_gpio->offset = apu2_gpio_offset;
+		apu_gpio->chip.names = apu2_gpio_names;
+		apu_gpio->chip.ngpio = ARRAY_SIZE(apu2_gpio_offset);
+		for (i = 0; i < ARRAY_SIZE(apu2_gpio_offset); i++) {
+			apu_gpio->addr[i] = devm_ioremap(&pdev->dev,
+					apu_gpio->offset[i], sizeof(u32));
+			if (!apu_gpio->addr[i])
+				return -ENOMEM;
+		}
+	}
+
+	return devm_gpiochip_add_data(&pdev->dev, &apu_gpio->chip, apu_gpio);
+}
+
+static struct platform_driver apu_gpio_driver = {
+	.driver = {
+		.name = KBUILD_MODNAME,
+	},
+	.probe = apu_gpio_probe,
+};
+
+static int __init apu_gpio_init(void)
+{
+	if (!(dmi_check_system(apu2_gpio_dmi_table)) &&
+		!(dmi_check_system(apu3_gpio_dmi_table))) {
+		pr_err("No PC Engines board detected\n");
+		return -ENODEV;
+	}
+
+	apu_gpio_pdev = platform_device_register_simple(KBUILD_MODNAME,
+			-1, NULL, 0);
+	if (IS_ERR(apu_gpio_pdev))
+		return PTR_ERR(apu_gpio_pdev);
+
+
+	return platform_driver_register(&apu_gpio_driver);
+}
+
+static void __exit apu_gpio_exit(void)
+{
+	platform_device_unregister(apu_gpio_pdev);
+	platform_driver_unregister(&apu_gpio_driver);
+}
+
+module_init(apu_gpio_init);
+module_exit(apu_gpio_exit);
+
+MODULE_AUTHOR("Florian Eckert");
+MODULE_DESCRIPTION("PC Engines APU2/APU3 family GPIO driver");
+MODULE_LICENSE("GPL v2");
-- 
2.11.0

Re: [PATCH v5 1/2] gpio: Add driver for PC Engines APU boards

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 2253 bytes --]

Hi Florian,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on gpio/for-next]
[also build test ERROR on v4.20-rc4 next-20181127]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Florian-Eckert/Add-device-driver-for-APU2-APU3-GPIOs/20181128-045043
base:   https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git for-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

All error/warnings (new ones prefixed by >>):

   In file included from drivers/gpio/gpio-apu.c:13:0:
>> include/linux/module.h:213:1: error: expected ',' or ';' before 'extern'
    extern typeof(name) __mod_##type##__##name##_device_table  \
    ^
>> drivers/gpio/gpio-apu.c:163:1: note: in expansion of macro 'MODULE_DEVICE_TABLE'
    MODULE_DEVICE_TABLE(dmi, apu2_gpio_dmi_table);
    ^~~~~~~~~~~~~~~~~~~

vim +213 include/linux/module.h

^1da177e Linus Torvalds    2005-04-16  209  
cff26a51 Rusty Russell     2014-02-03  210  #ifdef MODULE
cff26a51 Rusty Russell     2014-02-03  211  /* Creates an alias so file2alias.c can find device table. */
^1da177e Linus Torvalds    2005-04-16  212  #define MODULE_DEVICE_TABLE(type, name)					\
0bf8bf50 Matthias Kaehlcke 2017-07-24 @213  extern typeof(name) __mod_##type##__##name##_device_table		\
cff26a51 Rusty Russell     2014-02-03  214    __attribute__ ((unused, alias(__stringify(name))))
cff26a51 Rusty Russell     2014-02-03  215  #else  /* !MODULE */
cff26a51 Rusty Russell     2014-02-03  216  #define MODULE_DEVICE_TABLE(type, name)
cff26a51 Rusty Russell     2014-02-03  217  #endif
^1da177e Linus Torvalds    2005-04-16  218  

:::::: The code at line 213 was first introduced by commit
:::::: 0bf8bf50eddc7511b52461bae798cbfaa0157a34 module: Remove const attribute from alias for MODULE_DEVICE_TABLE

:::::: TO: Matthias Kaehlcke <mka@chromium.org>
:::::: CC: Jessica Yu <jeyu@kernel.org>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 66034 bytes --]

Re: [PATCH v5 1/2] gpio: Add driver for PC Engines APU boards

[Andy Shevchenko]

On Tue, Nov 27, 2018 at 3:25 PM Florian Eckert <fe@dev.tdt.de> wrote:
>
> Add a new device driver "gpio-apu" which will handle the GPIOs on APU2
> and APU3 devices from PC Engines.
>
> APU2 (https://pcengines.ch/schema/apu2c.pdf page 7):
> - G32 is "button_reset" connected to the smd-button on the frontpanel
> - G50 is "mpcie2_reset" connected to mPCIe2 reset line
> - G51 is "mpcie3_reset" connected to mPCIe3 reset line
>
> APU3 (https://pcengines.ch/schema/apu3c.pdf page 7):
> - G32 is "button_reset" connected to the smd-button on the frontpanel
> - G50 is "mpcie2_reset" connected to mPCIe2 reset line
> - G51 is "mpcie3_reset" connected to mPCIe3 reset line
> - G33 is "simswap" connected to SIM switch IC to swap the SIM between
>   mPCIe2 and mPCIe3 slot

> +/* PC Engines APU2/APU3 GPIO device driver
> + *
> + * Copyright (C) 2018 Florian Eckert <fe@dev.tdt.de>
> + */

/*
 * Multi-line comments
 * have this style
 */

> +#include <linux/bits.h>
> +#include <linux/dmi.h>
> +#include <linux/err.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/input.h>
> +#include <linux/kernel.h>

kbuild bot complains for absence of

#include <linux/mod_devicetable.h>

here.

> +#include <linux/module.h>
> +#include <linux/platform_device.h>

> +static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int offset)
> +{
> +       u32 val;
> +       struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
> +
> +       spin_lock(&apu_gpio->lock);
> +

> +       val = ~ioread32(apu_gpio->addr[offset]);

There is no need to do ~ under spin lock.

> +
> +       spin_unlock(&apu_gpio->lock);
> +
> +       return !!(val & BIT(APU_GPIO_BIT_DIR));
> +}

> +       if (dmi_check_system(apu3_gpio_dmi_table)) {

(1)

> +               apu_gpio->addr = devm_kzalloc(&pdev->dev,
> +                               sizeof(apu3_gpio_offset),
> +                               GFP_KERNEL);

> +

No need to have this blank line. Same for the other cases.

> +               if (!apu_gpio->addr)
> +                       return -ENOMEM;

> +       } else if (dmi_check_system(apu2_gpio_dmi_table)) {

(2)

I think I have already told about (1) and (2). You may create two
callbacks and utilize .callback member in DMI table.

> +       }

> +static int __init apu_gpio_init(void)
> +{

> +       if (!(dmi_check_system(apu2_gpio_dmi_table)) &&
> +               !(dmi_check_system(apu3_gpio_dmi_table))) {
> +               pr_err("No PC Engines board detected\n");
> +               return -ENODEV;
> +       }

I don't think we need this.

> +       apu_gpio_pdev = platform_device_register_simple(KBUILD_MODNAME,
> +                       -1, NULL, 0);
> +       if (IS_ERR(apu_gpio_pdev))
> +               return PTR_ERR(apu_gpio_pdev);
> +
> +
> +       return platform_driver_register(&apu_gpio_driver);
> +}
> +
> +static void __exit apu_gpio_exit(void)
> +{
> +       platform_device_unregister(apu_gpio_pdev);
> +       platform_driver_unregister(&apu_gpio_driver);
> +}
> +
> +module_init(apu_gpio_init);
> +module_exit(apu_gpio_exit);

After removing unneeded checks why not to simple use
module_platform_driver()
?

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v5 1/2] gpio: Add driver for PC Engines APU boards

[Florian Eckert]

> /*
>  * Multi-line comments
>  * have this style
>  */

fixed


>> +#include <linux/kernel.h>
> 
> kbuild bot complains for absence of
> 
> #include <linux/mod_devicetable.h>
> 
> here.
> 

fixed

>> +static int gpio_apu_get_dir(struct gpio_chip *chip, unsigned int 
>> offset)
>> +{
>> +       u32 val;
>> +       struct apu_gpio_pdata *apu_gpio = gpiochip_get_data(chip);
>> +
>> +       spin_lock(&apu_gpio->lock);
>> +
> 
>> +       val = ~ioread32(apu_gpio->addr[offset]);
> 
> There is no need to do ~ under spin lock.
> 

fixed

>> +
>> +       spin_unlock(&apu_gpio->lock);
>> +
>> +       return !!(val & BIT(APU_GPIO_BIT_DIR));
>> +}
> 
>> +       if (dmi_check_system(apu3_gpio_dmi_table)) {
> 
> (1)
> 
>> +               apu_gpio->addr = devm_kzalloc(&pdev->dev,
>> +                               sizeof(apu3_gpio_offset),
>> +                               GFP_KERNEL);
> 
>> +
> 
> No need to have this blank line. Same for the other cases.
> 

fixed

>> +               if (!apu_gpio->addr)
>> +                       return -ENOMEM;
> 
>> +       } else if (dmi_check_system(apu2_gpio_dmi_table)) {
> 
> (2)
> 
> I think I have already told about (1) and (2). You may create two
> callbacks and utilize .callback member in DMI table.
> 

Done but I do not seen any advantage. I used the following driver as 
basis.
https://github.com/torvalds/linux/blob/master/drivers/leds/leds-clevo-mail.c

>> +       }
> 
>> +static int __init apu_gpio_init(void)
>> +{
> 
>> +       if (!(dmi_check_system(apu2_gpio_dmi_table)) &&
>> +               !(dmi_check_system(apu3_gpio_dmi_table))) {
>> +               pr_err("No PC Engines board detected\n");
>> +               return -ENODEV;
>> +       }
> 
> I don't think we need this.
> 

see below


>> +}
>> +
>> +module_init(apu_gpio_init);
>> +module_exit(apu_gpio_exit);

> 
> After removing unneeded checks why not to simple use
> module_platform_driver()
> ?

I have fixed all the above hints from you now but using 
"module_platform_driver" is no option.
I played around with them but the driver does not find any device. So I 
need the init function
to add a platform device. Only if I do this way driver and device will 
find and match. And I
see the gpios under /sys/class/gpio. So I think I need this?
I have not find any driver who has the same problems
I used the following drivers as my basis:
https://github.com/torvalds/linux/blob/master/drivers/leds/leds-apu.c
https://github.com/torvalds/linux/blob/master/drivers/leds/leds-clevo-mail.c
They all use dmi and need init/exit for platform device register and 
unregister

[PATCH v5 2/2] platform: Add reset button device for PC Engines APU boards

[Florian Eckert]

Add a platform/x86 device "gpio-keys-polled" for the frontpanel reset button.
This device uses the gpio-apu driver for APU borads from PC Engines.

Signed-off-by: Florian Eckert <fe@dev.tdt.de>
---
 drivers/platform/x86/Kconfig                  |  11 +++
 drivers/platform/x86/Makefile                 |   1 +
 drivers/platform/x86/pcengines-apu-platform.c | 114 ++++++++++++++++++++++++++
 3 files changed, 126 insertions(+)
 create mode 100644 drivers/platform/x86/pcengines-apu-platform.c

diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 54f6a40c75c6..5cd27c2174cb 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1288,6 +1288,17 @@ config INTEL_ATOMISP2_PM
 	  To compile this driver as a module, choose M here: the module
 	  will be called intel_atomisp2_pm.
 
+config PCENGINES_APU_PLATFORM
+	bool "PCEngines APU System Support"
+	depends on X86_64 && DMI && GPIOLIB
+	help
+	  This option enables system support for the PCEngines APU platform.
+	  At present this just adds the GPIO reset button platform device on
+	  APU2/APU3 boards.
+
+	  Note: You must still enable the drivers for GPIO and LED support
+	  (GPIO_APU & LEDS_APU) to actually use the LEDs and the GPIOs.
+
 endif # X86_PLATFORM_DEVICES
 
 config PMC_ATOM
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 39ae94135406..f899cc4c6b48 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -96,3 +96,4 @@ obj-$(CONFIG_INTEL_TURBO_MAX_3) += intel_turbo_max_3.o
 obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN)	+= intel_chtdc_ti_pwrbtn.o
 obj-$(CONFIG_I2C_MULTI_INSTANTIATE)	+= i2c-multi-instantiate.o
 obj-$(CONFIG_INTEL_ATOMISP2_PM)	+= intel_atomisp2_pm.o
+obj-$(CONFIG_PCENGINES_APU_PLATFORM)	+= pcengines-apu-platform.o
diff --git a/drivers/platform/x86/pcengines-apu-platform.c b/drivers/platform/x86/pcengines-apu-platform.c
new file mode 100644
index 000000000000..3bfbaa93cb11
--- /dev/null
+++ b/drivers/platform/x86/pcengines-apu-platform.c
@@ -0,0 +1,114 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * System Specific setup for PC-Engines APU2/APU3 devices
+ *
+ * Copyright (C) 2018 Florian Eckert <fe@dev.tdt.de>
+ */
+
+#include <linux/dmi.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+static const struct dmi_system_id apu2_gpio_dmi_table[] __initconst = {
+	/* PC Engines APU2 with "Legacy" bios < 4.0.8 */
+	{
+		.ident = "apu2",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "APU2")
+		}
+	},
+	/* PC Engines APU2 with "Legacy" bios >= 4.0.8 */
+	{
+		.ident = "apu2",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "apu2")
+		}
+	},
+	/* PC Engines APU2 with "Mainline" bios */
+	{
+		.ident = "apu2",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
+		}
+	},
+	{}
+};
+MODULE_DEVICE_TABLE(dmi, apu2_gpio_dmi_table);
+
+static const struct dmi_system_id apu3_gpio_dmi_table[] __initconst = {
+	/* PC Engines APU3 with "Legacy" bios < 4.0.8 */
+	{
+		.ident = "apu3",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "APU3")
+		}
+	},
+	/* PC Engines APU3 with "Legacy" bios >= 4.0.8 */
+	{
+		.ident = "apu3",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "apu3")
+		}
+	},
+	/* PC Engines APU3 with "Mainline" bios */
+	{
+		.ident = "apu3",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
+			DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu3")
+		}
+	},
+	{}
+};
+MODULE_DEVICE_TABLE(dmi, apu3_gpio_dmi_table);
+
+
+static struct gpio_keys_button apu_gpio_buttons[] = {
+	{
+		.code			= KEY_RESTART,
+		.gpio			= 20,
+		.active_low		= 1,
+		.desc			= "Reset button",
+		.type			= EV_KEY,
+		.debounce_interval	= 60,
+	}
+};
+
+static struct gpio_keys_platform_data apu_buttons_data = {
+	.buttons		= apu_gpio_buttons,
+	.nbuttons		= ARRAY_SIZE(apu_gpio_buttons),
+	.poll_interval		= 20,
+};
+
+static struct platform_device apu_button_dev = {
+	.name			= "gpio-keys-polled",
+	.id			= 1,
+	.dev = {
+		.platform_data		= &apu_buttons_data,
+	}
+};
+
+static int __init apu_init(void)
+{
+	if (!(dmi_check_system(apu2_gpio_dmi_table)) &&
+		!(dmi_check_system(apu3_gpio_dmi_table))) {
+		return -ENODEV;
+	}
+
+	return platform_device_register(&apu_button_dev);
+}
+
+static void __exit apu_exit(void)
+{
+	platform_device_unregister(&apu_button_dev);
+}
+
+module_init(apu_init);
+module_exit(apu_exit);
-- 
2.11.0

Re: [PATCH v5 2/2] platform: Add reset button device for PC Engines APU boards

[Andy Shevchenko]

On Tue, Nov 27, 2018 at 3:25 PM Florian Eckert <fe@dev.tdt.de> wrote:
>
> Add a platform/x86 device "gpio-keys-polled" for the frontpanel reset button.
> This device uses the gpio-apu driver for APU borads from PC Engines.

Yep, and actually this one has to instantiate a GPIO.

>
> Signed-off-by: Florian Eckert <fe@dev.tdt.de>
> ---
>  drivers/platform/x86/Kconfig                  |  11 +++
>  drivers/platform/x86/Makefile                 |   1 +
>  drivers/platform/x86/pcengines-apu-platform.c | 114 ++++++++++++++++++++++++++
>  3 files changed, 126 insertions(+)
>  create mode 100644 drivers/platform/x86/pcengines-apu-platform.c
>
> diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
> index 54f6a40c75c6..5cd27c2174cb 100644
> --- a/drivers/platform/x86/Kconfig
> +++ b/drivers/platform/x86/Kconfig
> @@ -1288,6 +1288,17 @@ config INTEL_ATOMISP2_PM
>           To compile this driver as a module, choose M here: the module
>           will be called intel_atomisp2_pm.
>
> +config PCENGINES_APU_PLATFORM
> +       bool "PCEngines APU System Support"
> +       depends on X86_64 && DMI && GPIOLIB
> +       help
> +         This option enables system support for the PCEngines APU platform.
> +         At present this just adds the GPIO reset button platform device on
> +         APU2/APU3 boards.
> +
> +         Note: You must still enable the drivers for GPIO and LED support
> +         (GPIO_APU & LEDS_APU) to actually use the LEDs and the GPIOs.
> +
>  endif # X86_PLATFORM_DEVICES
>
>  config PMC_ATOM
> diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
> index 39ae94135406..f899cc4c6b48 100644
> --- a/drivers/platform/x86/Makefile
> +++ b/drivers/platform/x86/Makefile
> @@ -96,3 +96,4 @@ obj-$(CONFIG_INTEL_TURBO_MAX_3) += intel_turbo_max_3.o
>  obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN)    += intel_chtdc_ti_pwrbtn.o
>  obj-$(CONFIG_I2C_MULTI_INSTANTIATE)    += i2c-multi-instantiate.o
>  obj-$(CONFIG_INTEL_ATOMISP2_PM)        += intel_atomisp2_pm.o
> +obj-$(CONFIG_PCENGINES_APU_PLATFORM)   += pcengines-apu-platform.o
> diff --git a/drivers/platform/x86/pcengines-apu-platform.c b/drivers/platform/x86/pcengines-apu-platform.c
> new file mode 100644
> index 000000000000..3bfbaa93cb11
> --- /dev/null
> +++ b/drivers/platform/x86/pcengines-apu-platform.c
> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * System Specific setup for PC-Engines APU2/APU3 devices
> + *
> + * Copyright (C) 2018 Florian Eckert <fe@dev.tdt.de>
> + */
> +
> +#include <linux/dmi.h>
> +#include <linux/gpio_keys.h>
> +#include <linux/input.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +static const struct dmi_system_id apu2_gpio_dmi_table[] __initconst = {
> +       /* PC Engines APU2 with "Legacy" bios < 4.0.8 */
> +       {
> +               .ident = "apu2",
> +               .matches = {
> +                       DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
> +                       DMI_MATCH(DMI_BOARD_NAME, "APU2")
> +               }
> +       },
> +       /* PC Engines APU2 with "Legacy" bios >= 4.0.8 */
> +       {
> +               .ident = "apu2",
> +               .matches = {
> +                       DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
> +                       DMI_MATCH(DMI_BOARD_NAME, "apu2")
> +               }
> +       },
> +       /* PC Engines APU2 with "Mainline" bios */
> +       {
> +               .ident = "apu2",
> +               .matches = {
> +                       DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
> +                       DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
> +               }
> +       },
> +       {}
> +};
> +MODULE_DEVICE_TABLE(dmi, apu2_gpio_dmi_table);
> +
> +static const struct dmi_system_id apu3_gpio_dmi_table[] __initconst = {
> +       /* PC Engines APU3 with "Legacy" bios < 4.0.8 */
> +       {
> +               .ident = "apu3",
> +               .matches = {
> +                       DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
> +                       DMI_MATCH(DMI_BOARD_NAME, "APU3")
> +               }
> +       },
> +       /* PC Engines APU3 with "Legacy" bios >= 4.0.8 */
> +       {
> +               .ident = "apu3",
> +               .matches = {
> +                       DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
> +                       DMI_MATCH(DMI_BOARD_NAME, "apu3")
> +               }
> +       },
> +       /* PC Engines APU3 with "Mainline" bios */
> +       {
> +               .ident = "apu3",
> +               .matches = {
> +                       DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
> +                       DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu3")
> +               }
> +       },
> +       {}
> +};
> +MODULE_DEVICE_TABLE(dmi, apu3_gpio_dmi_table);
> +
> +
> +static struct gpio_keys_button apu_gpio_buttons[] = {
> +       {
> +               .code                   = KEY_RESTART,
> +               .gpio                   = 20,
> +               .active_low             = 1,
> +               .desc                   = "Reset button",
> +               .type                   = EV_KEY,
> +               .debounce_interval      = 60,
> +       }
> +};
> +
> +static struct gpio_keys_platform_data apu_buttons_data = {
> +       .buttons                = apu_gpio_buttons,
> +       .nbuttons               = ARRAY_SIZE(apu_gpio_buttons),
> +       .poll_interval          = 20,
> +};
> +
> +static struct platform_device apu_button_dev = {
> +       .name                   = "gpio-keys-polled",
> +       .id                     = 1,
> +       .dev = {
> +               .platform_data          = &apu_buttons_data,
> +       }
> +};
> +
> +static int __init apu_init(void)
> +{
> +       if (!(dmi_check_system(apu2_gpio_dmi_table)) &&
> +               !(dmi_check_system(apu3_gpio_dmi_table))) {
> +               return -ENODEV;
> +       }
> +
> +       return platform_device_register(&apu_button_dev);
> +}
> +
> +static void __exit apu_exit(void)
> +{
> +       platform_device_unregister(&apu_button_dev);
> +}
> +
> +module_init(apu_init);
> +module_exit(apu_exit);
> --
> 2.11.0
>


-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v5 2/2] platform: Add reset button device for PC Engines APU boards

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 3490 bytes --]

Hi Florian,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on gpio/for-next]
[also build test ERROR on v4.20-rc4 next-20181128]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Florian-Eckert/Add-device-driver-for-APU2-APU3-GPIOs/20181128-045043
base:   https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git for-next
config: x86_64-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

>> drivers/gpio/gpio-apu.c:163:1: error: Expected ; at end of declaration
>> drivers/gpio/gpio-apu.c:163:1: error: got extern
   In file included from drivers/gpio/gpio-apu.c:13:0:
   include/linux/module.h:213:1: error: expected ',' or ';' before 'extern'
    extern typeof(name) __mod_##type##__##name##_device_table  \
    ^
   drivers/gpio/gpio-apu.c:163:1: note: in expansion of macro 'MODULE_DEVICE_TABLE'
    MODULE_DEVICE_TABLE(dmi, apu2_gpio_dmi_table);
    ^~~~~~~~~~~~~~~~~~~

vim +163 drivers/gpio/gpio-apu.c

4c30b3d4 Florian Eckert 2018-11-27  135  
4c30b3d4 Florian Eckert 2018-11-27  136  static const struct dmi_system_id apu2_gpio_dmi_table[] __initconst = {
4c30b3d4 Florian Eckert 2018-11-27  137  	/* PC Engines APU2 with "Legacy" bios < 4.0.8 */
4c30b3d4 Florian Eckert 2018-11-27  138  	{
4c30b3d4 Florian Eckert 2018-11-27  139  		.ident = "apu2",
4c30b3d4 Florian Eckert 2018-11-27  140  		.matches = {
4c30b3d4 Florian Eckert 2018-11-27  141  			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
4c30b3d4 Florian Eckert 2018-11-27  142  			DMI_MATCH(DMI_BOARD_NAME, "APU2")
4c30b3d4 Florian Eckert 2018-11-27  143  		}
4c30b3d4 Florian Eckert 2018-11-27  144  	},
4c30b3d4 Florian Eckert 2018-11-27  145  	/* PC Engines APU2 with "Legacy" bios >= 4.0.8 */
4c30b3d4 Florian Eckert 2018-11-27  146  	{
4c30b3d4 Florian Eckert 2018-11-27  147  		.ident = "apu2",
4c30b3d4 Florian Eckert 2018-11-27  148  		.matches = {
4c30b3d4 Florian Eckert 2018-11-27  149  			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
4c30b3d4 Florian Eckert 2018-11-27  150  			DMI_MATCH(DMI_BOARD_NAME, "apu2")
4c30b3d4 Florian Eckert 2018-11-27  151  		}
4c30b3d4 Florian Eckert 2018-11-27  152  	},
4c30b3d4 Florian Eckert 2018-11-27  153  	/* PC Engines APU2 with "Mainline" bios */
4c30b3d4 Florian Eckert 2018-11-27  154  	{
4c30b3d4 Florian Eckert 2018-11-27  155  		.ident = "apu2",
4c30b3d4 Florian Eckert 2018-11-27  156  		.matches = {
4c30b3d4 Florian Eckert 2018-11-27  157  			DMI_MATCH(DMI_SYS_VENDOR, "PC Engines"),
4c30b3d4 Florian Eckert 2018-11-27  158  			DMI_MATCH(DMI_BOARD_NAME, "PC Engines apu2")
4c30b3d4 Florian Eckert 2018-11-27  159  		}
4c30b3d4 Florian Eckert 2018-11-27  160  	},
4c30b3d4 Florian Eckert 2018-11-27  161  	{}
4c30b3d4 Florian Eckert 2018-11-27  162  }
4c30b3d4 Florian Eckert 2018-11-27 @163  MODULE_DEVICE_TABLE(dmi, apu2_gpio_dmi_table);
4c30b3d4 Florian Eckert 2018-11-27  164  

:::::: The code at line 163 was first introduced by commit
:::::: 4c30b3d47204299cdb436562e2099c4a72427db7 gpio: Add driver for PC Engines APU boards

:::::: TO: Florian Eckert <fe@dev.tdt.de>
:::::: CC: 0day robot <lkp@intel.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 66638 bytes --]

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

[Andy Shevchenko]

On Tue, Nov 27, 2018 at 3:25 PM Florian Eckert <fe@dev.tdt.de> wrote:

> Changes v5:
> gpio-apu.c
> - Remove GPIO_GENERIC select from Kconfig
> - Make gpio_chip real member of apu_gpio_pdata
> - Use BIT macro for get_data and get_dir functions
> - Pass platform data to devm_gpiochip_add_data to get data
>   per-instance state container
> - Remove DEVNAME define
> - Remove platfrom_device member from apu_gpio_pdata this
> - Clean up init function
> - Remove MODULE_ALIAS
>
> Until now it was not possible to get more information to detect the
> MMIO_BASE address from the ACPI subsystem.

I'm sorry if I already asked, please, remind me where dump of ACPI
tables can be found?
Also would be nice to have the output of `lspci -nk -vv -xxx` on such platform.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

[Florian Eckert]

Hello Andy,

Thank you very very much for your code review "again" I will update my 
patch set with your hints.
Should I send v6 or should i wait till I get feedback from you about 
ACPI?

>> 
>> Until now it was not possible to get more information to detect the
>> MMIO_BASE address from the ACPI subsystem.
> 
> I'm sorry if I already asked, please, remind me where dump of ACPI
> tables can be found?

https://www.spinics.net/lists/kernel/msg2887290.html

> Also would be nice to have the output of `lspci -nk -vv -xxx` on such 
> platform.

00:00.0 0600: 1022:1566
	Subsystem: 1022:1566
	Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0
lspci: Unable to load libkmod resources: error -12
00: 22 10 66 15 04 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 66 15
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00
50: 22 10 66 15 00 00 00 00 00 00 00 00 00 00 00 00
60: 46 00 00 00 63 10 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00
80: 00 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 7f 2c 00 00 00 02 02 19 00 00 00 00 00
a0: 01 80 30 01 ef be ad de 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 04 00 10 c2 03 00 00 00
c0: 00 00 00 00 00 00 00 00 01 00 12 00 00 00 14 00
d0: b6 14 30 01 00 00 00 00 00 00 00 00 00 00 00 00
e0: 10 00 40 01 01 11 e3 80 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 80 80 00 00 00 00 00 05 00 00 00

00:02.0 0600: 1022:156b
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
00: 22 10 6b 15 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.2 0604: 1022:1439 (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin B routed to IRQ 24
	Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
	I/O behind bridge: 00001000-00001fff [size=4K]
	Memory behind bridge: fe500000-fe5fffff [size=1M]
	Prefetchable memory behind bridge: None
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- <SERR- <PERR-
	BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA 
PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 512 bytes, PhantFunc 0
			ExtTag+ RBE+
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 256 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #1, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s 
<512ns, L1 <64us
			ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ 
BWMgmt+ ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
			Slot #0, PowerLimit 0.000W; Interlock- NoCompl+
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- 
LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet+ LinkState+
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- 
CRSVisible+
		RootCap: CRSVisible+
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
		DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not 
Supported ARIFwd-
			 AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
		DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis-, LTR-, OBFF 
Disabled ARIFwd-
			 AtomicOpsCtl: ReqEn- EgressBlck-
		LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- 
ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, 
EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
		Address: 0000000000000000  Data: 0000
	Capabilities: [b0] Subsystem: 1022:1234
	Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+
	Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 
Len=010 <?>
	Kernel driver in use: pcieport
00: 22 10 39 14 07 00 10 00 00 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 11 11 00 00
20: 50 fe 50 fe f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 02 03 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 58 03 c8 00 00 00 00 10 a0 42 01 22 80 00 00
60: 30 29 00 00 12 3c 73 01 40 00 11 70 00 00 04 00
70: 00 00 48 01 10 00 01 00 00 00 00 00 1f 00 00 00
80: 06 00 00 00 06 00 00 00 02 00 01 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 05 b0 80 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 6a 00 00 00 01 05 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.3 0604: 1022:1439 (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin C routed to IRQ 25
	Bus: primary=00, secondary=02, subordinate=02, sec-latency=0
	I/O behind bridge: 00002000-00002fff [size=4K]
	Memory behind bridge: fe600000-fe6fffff [size=1M]
	Prefetchable memory behind bridge: None
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- <SERR- <PERR-
	BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA 
PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 512 bytes, PhantFunc 0
			ExtTag+ RBE+
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 256 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #2, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s 
<512ns, L1 <64us
			ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ 
BWMgmt+ ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
			Slot #0, PowerLimit 0.000W; Interlock- NoCompl+
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- 
LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet+ LinkState+
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- 
CRSVisible+
		RootCap: CRSVisible+
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
		DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not 
Supported ARIFwd-
			 AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
		DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis-, LTR-, OBFF 
Disabled ARIFwd-
			 AtomicOpsCtl: ReqEn- EgressBlck-
		LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- 
ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, 
EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
		Address: 0000000000000000  Data: 0000
	Capabilities: [b0] Subsystem: 1022:1234
	Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+
	Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 
Len=010 <?>
	Kernel driver in use: pcieport
00: 22 10 39 14 07 00 10 00 00 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 02 02 00 21 21 00 00
20: 60 fe 60 fe f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 03 03 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 58 03 c8 00 00 00 00 10 a0 42 01 22 80 00 00
60: 30 29 00 00 12 3c 73 02 40 00 11 70 00 00 04 00
70: 00 00 48 01 10 00 01 00 00 00 00 00 1f 00 00 00
80: 06 00 00 00 06 00 00 00 02 00 01 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 05 b0 80 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 6a 00 00 00 01 05 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.4 0604: 1022:1439 (prog-if 00 [Normal decode])
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin D routed to IRQ 26
	Bus: primary=00, secondary=03, subordinate=03, sec-latency=0
	I/O behind bridge: 00003000-00003fff [size=4K]
	Memory behind bridge: fe700000-fe7fffff [size=1M]
	Prefetchable memory behind bridge: None
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- <SERR- <PERR-
	BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA 
PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 512 bytes, PhantFunc 0
			ExtTag+ RBE+
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 256 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #3, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s 
<512ns, L1 <64us
			ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ 
BWMgmt+ ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
			Slot #0, PowerLimit 0.000W; Interlock- NoCompl+
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- 
LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet+ LinkState+
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- 
CRSVisible+
		RootCap: CRSVisible+
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
		DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not 
Supported ARIFwd-
			 AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
		DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis-, LTR-, OBFF 
Disabled ARIFwd-
			 AtomicOpsCtl: ReqEn- EgressBlck-
		LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- 
ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, 
EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
		Address: 0000000000000000  Data: 0000
	Capabilities: [b0] Subsystem: 1022:1234
	Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+
	Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 
Len=010 <?>
	Kernel driver in use: pcieport
00: 22 10 39 14 07 00 10 00 00 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 03 03 00 31 31 00 00
20: 70 fe 70 fe f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 04 03 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 58 03 c8 00 00 00 00 10 a0 42 01 22 80 00 00
60: 30 29 00 00 12 3c 73 03 40 00 11 70 00 00 04 00
70: 00 00 48 01 10 00 01 00 00 00 00 00 1f 00 00 00
80: 06 00 00 00 06 00 00 00 02 00 01 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 05 b0 80 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 6a 00 00 00 01 05 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:02.5 0604: 1022:1439 (prog-if 00 [Normal decode])
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 27
	Bus: primary=00, secondary=04, subordinate=04, sec-latency=0
	I/O behind bridge: None
	Memory behind bridge: fe200000-fe4fffff [size=3M]
	Prefetchable memory behind bridge: None
	Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- <SERR- <PERR-
	BridgeCtl: Parity+ SERR+ NoISA- VGA- MAbort- >Reset- FastB2B-
		PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA 
PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [58] Express (v2) Root Port (Slot+), MSI 00
		DevCap:	MaxPayload 512 bytes, PhantFunc 0
			ExtTag+ RBE+
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 256 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #4, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s 
<512ns, L1 <64us
			ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ 
BWMgmt+ ABWMgmt-
		SltCap:	AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
			Slot #0, PowerLimit 0.000W; Interlock- NoCompl+
		SltCtl:	Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- 
LinkChg-
			Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
		SltSta:	Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
			Changed: MRL- PresDet+ LinkState+
		RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- 
CRSVisible+
		RootCap: CRSVisible+
		RootSta: PME ReqID 0000, PMEStatus- PMEPending-
		DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not 
Supported ARIFwd-
			 AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
		DevCtl2: Completion Timeout: 65ms to 210ms, TimeoutDis-, LTR-, OBFF 
Disabled ARIFwd-
			 AtomicOpsCtl: ReqEn- EgressBlck-
		LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- 
ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, 
EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit+
		Address: 0000000000000000  Data: 0000
	Capabilities: [b0] Subsystem: 1022:1234
	Capabilities: [b8] HyperTransport: MSI Mapping Enable+ Fixed+
	Capabilities: [100 v1] Vendor Specific Information: ID=0001 Rev=1 
Len=010 <?>
	Kernel driver in use: pcieport
00: 22 10 39 14 06 00 10 00 00 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 04 04 00 f1 01 00 00
20: 20 fe 40 fe f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 03 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 01 58 03 c8 00 00 00 00 10 a0 42 01 22 80 00 00
60: 30 29 00 00 12 3c 73 04 40 00 11 70 00 00 04 00
70: 00 00 48 01 10 00 01 00 00 00 00 00 1f 00 00 00
80: 06 00 00 00 06 00 00 00 02 00 01 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 05 b0 80 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 0d b8 00 00 22 10 34 12 08 00 03 a8 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 6a 00 00 00 01 05 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:08.0 1080: 1022:1537
	Subsystem: 1022:1537
	Control: I/O- Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Region 0: Memory at fea00000 (64-bit, prefetchable) [size=128K]
	Region 2: Memory at fe800000 (32-bit, non-prefetchable) [size=1M]
	Region 3: Memory at fea24000 (32-bit, non-prefetchable) [size=4K]
	Region 4: Memory at fe900000 (32-bit, non-prefetchable) [size=1M]
	Region 5: Memory at fea20000 (32-bit, non-prefetchable) [size=8K]
	Capabilities: [50] MSI-X: Enable- Count=2 Masked-
		Vector table: BAR=5 offset=00000000
		PBA: BAR=5 offset=00001000
	Capabilities: [5c] HyperTransport: MSI Mapping Enable+ Fixed+
	Capabilities: [60] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA 
PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
00: 22 10 37 15 02 00 10 00 00 00 80 10 00 00 00 00
10: 0c 00 a0 fe 00 00 00 00 00 00 80 fe 00 40 a2 fe
20: 00 00 90 fe 00 00 a2 fe 00 00 00 00 22 10 37 15
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 80 10 00 00 37 15 00 00 00 00 22 10 37 15
50: 11 5c 01 00 05 00 00 00 05 10 00 00 08 60 03 a8
60: 01 00 03 00 08 00 00 00 10 00 92 00 e0 8f 00 00
70: 10 09 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 13 00 06 01 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 4c 00 00 00 00 00 00 00
f0: 49 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00

00:10.0 0c03: 1022:7814 (rev 11) (prog-if 30 [XHCI])
	Subsystem: 1022:1410
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 18
	Region 0: Memory at fea22000 (64-bit, non-prefetchable) [size=8K]
	Capabilities: [50] Power Management version 3
		Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA 
PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [70] MSI: Enable- Count=1/8 Maskable- 64bit+
		Address: 0000000000000000  Data: 0000
	Capabilities: [90] MSI-X: Enable+ Count=8 Masked-
		Vector table: BAR=0 offset=00001000
		PBA: BAR=0 offset=00001080
	Capabilities: [a0] Express (v2) Root Complex Integrated Endpoint, MSI 
00
		DevCap:	MaxPayload 128 bytes, PhantFunc 0
			ExtTag- RBE+
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop+
			MaxPayload 128 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR+, OBFF 
Not Supported
			 AtomicOpsCap: 32bit- 64bit- 128bitCAS-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF 
Disabled
			 AtomicOpsCtl: ReqEn-
	Capabilities: [100 v1] Latency Tolerance Reporting
		Max snoop latency: 0ns
		Max no snoop latency: 0ns
	Kernel driver in use: xhci_hcd
00: 22 10 14 78 06 04 10 00 11 30 03 0c 10 00 00 00
10: 04 20 a2 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 10 14
30: 00 00 00 00 50 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 20 00 00 01 04 00 00 00 11 00 ff 0f
50: 01 70 03 c8 08 00 00 00 00 00 00 00 00 00 00 00
60: 30 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 05 90 86 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 11 a0 07 80 00 10 00 00 80 10 00 00 00 00 00 00
a0: 10 00 92 00 c0 8f 00 00 00 28 10 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 10 08 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: fc 1f 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 08 17 80 00 00 00 00 00 00 00 00 00 00 00 00 00

00:11.0 0106: 1022:7800 (rev 40) (prog-if 01 [AHCI 1.0])
	Subsystem: 1022:7800
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 64, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 19
	Region 0: I/O ports at 4010 [size=8]
	Region 1: I/O ports at 4020 [size=4]
	Region 2: I/O ports at 4018 [size=8]
	Region 3: I/O ports at 4024 [size=4]
	Region 4: I/O ports at 4000 [size=16]
	Region 5: Memory at fea25000 (32-bit, non-prefetchable) [size=1K]
	Capabilities: [60] Power Management version 3
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA 
PME(D0-,D1-,D2-,D3hot+,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [70] SATA HBA v1.0 InCfgSpace
	Kernel driver in use: ahci
00: 22 10 00 78 07 00 30 02 40 01 06 01 10 40 00 00
10: 11 40 00 00 21 40 00 00 19 40 00 00 25 40 00 00
20: 01 40 00 00 00 50 a2 fe 00 00 00 00 22 10 00 78
30: 00 00 00 00 60 00 00 00 00 00 00 00 00 01 00 00
40: 04 20 00 00 01 00 20 00 ea 10 00 80 01 03 03 fa
50: 05 d0 80 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 01 70 23 40 00 00 00 00 00 00 00 00 00 00 00 00
70: 12 00 10 00 0f 00 00 00 00 00 00 00 00 00 00 00
80: 10 00 00 00 06 00 14 04 ab 01 00 20 7d 00 70 60
90: 45 70 00 00 0c 00 10 00 03 31 40 00 86 0a 8f 0f
a0: 01 c8 00 00 81 10 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 20 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 10 00 00 ff 00 00 00 00
d0: 13 00 06 03 00 00 64 00 00 00 08 00 00 00 00 00
e0: 80 00 00 00 00 00 00 00 27 60 74 c7 ff 00 ff 01
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:12.0 0c03: 1022:7808 (rev 39) (prog-if 20 [EHCI])
	Subsystem: 1022:7808
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 64, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 18
	Region 0: Memory at fea25400 (32-bit, non-prefetchable) [size=256]
	Capabilities: [c0] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA 
PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
		Bridge: PM- B3+
	Capabilities: [e4] Debug port: BAR=1 offset=00e0
	Kernel driver in use: ehci-pci
00: 22 10 08 78 16 00 b0 02 39 20 03 0c 10 40 00 00
10: 00 54 a2 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 08 78
30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 41 11 2a a4 7b da 7f fb 00 00 00 00 00 00 00 00
60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: ff ff 0f 00 2c 00 00 c0 ff 00 00 80 00 00 00 00
80: 38 04 00 79 18 00 fe fc 81 00 20 00 c7 7e 32 64
90: 4c 1d 01 10 00 00 00 00 00 00 00 00 00 0f 0f 03
a0: 01 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 e4 02 fe 00 00 40 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 20 00 00 01
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:13.0 0c03: 1022:7808 (rev 39) (prog-if 20 [EHCI])
	Subsystem: 1022:7808
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 64, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 18
	Region 0: Memory at fea25500 (32-bit, non-prefetchable) [size=256]
	Capabilities: [c0] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA 
PME(D0+,D1+,D2+,D3hot+,D3cold+)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
		Bridge: PM- B3+
	Capabilities: [e4] Debug port: BAR=1 offset=00e0
	Kernel driver in use: ehci-pci
00: 22 10 08 78 16 00 b0 02 39 20 03 0c 10 40 00 00
10: 00 55 a2 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 08 78
30: 00 00 00 00 c0 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 41 11 2a a4 7b da 7f fb 00 00 00 00 00 00 00 00
60: 20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: ff ff 0f 00 2c 00 00 c0 ff 00 00 80 00 00 00 00
80: 38 04 00 79 18 00 fe fc 81 00 20 00 c7 7e 32 64
90: 4c 1d 01 10 00 00 00 00 00 00 00 00 00 0f 0b 00
a0: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 01 e4 02 fe 00 00 40 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 0a 00 e0 20 00 00 00 00 20 00 00 01
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:14.0 0c05: 1022:780b (rev 42)
	Subsystem: 1022:780b
	Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx+
	Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR- INTx-
	Kernel driver in use: piix4_smbus
00: 22 10 0b 78 03 04 20 02 42 00 05 0c 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 0b 78
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:14.3 0601: 1022:780e (rev 11)
	Subsystem: 1022:780e
	Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 0
00: 22 10 0e 78 0f 00 20 02 11 00 01 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 0e 78
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 04 00 00 00 d5 ff 03 ff 07 ff 20 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 0e 10 00 0e 00 0f 00 00 ff ff ff
70: 67 45 23 00 00 00 00 00 90 00 00 00 05 0a 00 00
80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 c1 fe 2f 01 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 04 00 e9 3d 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 80 47 10 82 ff
d0: 86 ff ff 08 42 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:14.7 0805: 1022:7813 (rev 01) (prog-if 01)
	Subsystem: 1022:7806
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- 
<TAbort- <MAbort- >SERR- <PERR- INTx-
	Latency: 71, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 16
	Region 0: Memory at fea25600 (32-bit, non-prefetchable) [size=256]
	Kernel driver in use: sdhci-pci
00: 22 10 13 78 06 00 20 02 01 01 05 08 10 47 80 00
10: 00 56 a2 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 06 78
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 01 00 03 80 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 00 00 b2 32 fe 21 70 00 00 00 64 00 c8 00
b0: 01 0c 18 01 01 00 00 80 00 04 02 88 98 cc 44 00
c0: 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 8b 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: fa 00 04 00 02 00 04 00 02 00 01 00 00 40 01 00

00:18.0 0600: 1022:1580
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
00: 22 10 80 15 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 02 04 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 03 00 e0 c8 00 00 1f 88 4e 00 00 fe 0f 58
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 20 10 11 00 00 00 00 00 13 00 00 00
90: a5 01 05 80 00 00 01 02 27 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.1 0600: 1022:1581
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
00: 22 10 81 15 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 03 00 00 00 00 00 7e 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 03 d0 fe 00 80 df fe 00 03 00 7f 00 00 cf fe 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 03 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.2 0600: 1022:1582
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
00: 22 10 82 15 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: e0 ff 78 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 02 00 90 00 08 18
80: 07 00 00 00 05 00 80 00 00 00 00 3c 00 00 02 00
90: 00 00 01 83 8e 88 49 9f 1f 00 0f 8d 06 60 00 00
a0: a0 03 1f 00 00 00 00 00 00 00 32 80 00 00 00 00
b0: d1 fe c5 c8 59 00 00 00 31 b7 9b a3 d2 09 54 3d
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: f6 7e be 29 f3 66 c6 da 2e ea e7 9c 76 76 d7 b9
e0: b7 69 17 dd ea 6c 9f db f5 6f 2b fb bd 36 d4 7e
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.3 0600: 1022:1583
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Capabilities: [f0] Secure device <?>
	Kernel driver in use: k10temp
00: 22 10 83 15 00 00 10 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 f0 00 00 00 00 00 00 00 00 00 00 00
40: ff ff ff ff 44 00 b0 48 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 25 00 6a 42 00 00 00 40 52 00 01 10
70: 53 11 13 10 01 01 1c 01 10 08 18 00 1b 06 05 00
80: 00 00 00 00 02 00 00 00 00 00 85 00 00 40 c8 40
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 48 8c a0 ef 0f a0 33 00 00 00 90 00 00 00 00
b0: 00 00 00 00 00 00 00 00 89 03 00 b0 00 80 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 0a 0f 80 98 40 00 00 00 00 64 78 68
e0: 00 00 00 00 20 00 00 00 18 4f f7 01 00 00 00 00
f0: 0f 00 10 00 00 00 00 00 00 00 00 00 01 0f 73 00

00:18.4 0600: 1022:1584
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Kernel driver in use: fam15h_power
00: 22 10 84 15 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 ff ff 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

00:18.5 0600: 1022:1585
	Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx-
	Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
00: 22 10 85 15 00 00 00 00 00 00 00 06 00 00 80 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 01 00 00 01 03 f0 0e 0e 01 10 0e 01 02 80 00 84
90: 4f 1d 12 60 31 00 00 00 00 00 00 01 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 a0 03 00 05 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 71 0d 00 00 00 00 00 00 28 ac 7b 00 00 00 00 00
f0: 11 00 00 00 02 00 00 40 00 00 00 00 00 00 00 00

01:00.0 0200: 8086:1539 (rev 03)
	Subsystem: 8086:0000
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 33
	Region 0: Memory at fe500000 (32-bit, non-prefetchable) [size=128K]
	Region 2: I/O ports at 1000 [size=32]
	Region 3: Memory at fe520000 (32-bit, non-prefetchable) [size=16K]
	Capabilities: [40] Power Management version 3
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA 
PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME-
	Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
		Address: 0000000000000000  Data: 0000
		Masking: 00000000  Pending: 00000000
	Capabilities: [70] MSI-X: Enable+ Count=5 Masked-
		Vector table: BAR=3 offset=00000000
		PBA: BAR=3 offset=00002000
	Capabilities: [a0] Express (v2) Endpoint, MSI 00
		DevCap:	MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 
<64us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W
		DevCtl:	Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
			MaxPayload 256 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency 
L0s <2us, L1 <16us
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- 
BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not 
Supported
			 AtomicOpsCap: 32bit- 64bit- 128bitCAS-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF 
Disabled
			 AtomicOpsCtl: ReqEn-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- 
ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, 
EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [100 v2] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- 
MalfTLP- ECRC- UnsupReq- ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- 
MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ 
MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		AERCap:	First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ 
ECRCChkEn-
			MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
		HeaderLog: 00000000 00000000 00000000 00000000
	Capabilities: [140 v1] Device Serial Number 00-0d-b9-ff-ff-4b-48-a4
	Capabilities: [1a0 v1] Transaction Processing Hints
		Device specific mode supported
		Steering table in TPH capability structure
	Kernel driver in use: igb
00: 86 80 39 15 07 04 10 00 03 00 00 02 10 00 00 00
10: 00 00 50 fe 00 00 00 00 01 10 00 00 00 00 52 fe
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00
40: 01 50 23 c8 08 20 00 00 00 00 00 00 00 00 00 00
50: 05 70 80 01 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 11 a0 04 80 03 00 00 00 03 20 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff ff
a0: 10 00 02 00 c2 8c 00 10 3f 28 10 00 11 5c 42 01
b0: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 1f 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

02:00.0 0200: 8086:1539 (rev 03)
	Subsystem: 8086:0000
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 39
	Region 0: Memory at fe600000 (32-bit, non-prefetchable) [size=128K]
	Region 2: I/O ports at 2000 [size=32]
	Region 3: Memory at fe620000 (32-bit, non-prefetchable) [size=16K]
	Capabilities: [40] Power Management version 3
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA 
PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME-
	Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
		Address: 0000000000000000  Data: 0000
		Masking: 00000000  Pending: 00000000
	Capabilities: [70] MSI-X: Enable+ Count=5 Masked-
		Vector table: BAR=3 offset=00000000
		PBA: BAR=3 offset=00002000
	Capabilities: [a0] Express (v2) Endpoint, MSI 00
		DevCap:	MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 
<64us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W
		DevCtl:	Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
			MaxPayload 256 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency 
L0s <2us, L1 <16us
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- 
BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not 
Supported
			 AtomicOpsCap: 32bit- 64bit- 128bitCAS-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF 
Disabled
			 AtomicOpsCtl: ReqEn-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- 
ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, 
EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [100 v2] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- 
MalfTLP- ECRC- UnsupReq- ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- 
MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ 
MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		AERCap:	First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ 
ECRCChkEn-
			MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
		HeaderLog: 00000000 00000000 00000000 00000000
	Capabilities: [140 v1] Device Serial Number 00-0d-b9-ff-ff-4b-48-a5
	Capabilities: [1a0 v1] Transaction Processing Hints
		Device specific mode supported
		Steering table in TPH capability structure
	Kernel driver in use: igb
00: 86 80 39 15 07 04 10 00 03 00 00 02 10 00 00 00
10: 00 00 60 fe 00 00 00 00 01 20 00 00 00 00 62 fe
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00
40: 01 50 23 c8 08 20 00 00 00 00 00 00 00 00 00 00
50: 05 70 80 01 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 11 a0 04 80 03 00 00 00 03 20 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff ff
a0: 10 00 02 00 c2 8c 00 10 3f 28 10 00 11 5c 42 02
b0: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 1f 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

03:00.0 0200: 8086:1539 (rev 03)
	Subsystem: 8086:0000
	Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 45
	Region 0: Memory at fe700000 (32-bit, non-prefetchable) [size=128K]
	Region 2: I/O ports at 3000 [size=32]
	Region 3: Memory at fe720000 (32-bit, non-prefetchable) [size=16K]
	Capabilities: [40] Power Management version 3
		Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA 
PME(D0+,D1-,D2-,D3hot+,D3cold+)
		Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=1 PME-
	Capabilities: [50] MSI: Enable- Count=1/1 Maskable+ 64bit+
		Address: 0000000000000000  Data: 0000
		Masking: 00000000  Pending: 00000000
	Capabilities: [70] MSI-X: Enable+ Count=5 Masked-
		Vector table: BAR=3 offset=00000000
		PBA: BAR=3 offset=00002000
	Capabilities: [a0] Express (v2) Endpoint, MSI 00
		DevCap:	MaxPayload 512 bytes, PhantFunc 0, Latency L0s <512ns, L1 
<64us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset+ SlotPowerLimit 0.000W
		DevCtl:	Report errors: Correctable+ Non-Fatal+ Fatal+ Unsupported+
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ FLReset-
			MaxPayload 256 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
		LnkCap:	Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency 
L0s <2us, L1 <16us
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp+
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- 
BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Range ABCD, TimeoutDis+, LTR-, OBFF Not 
Supported
			 AtomicOpsCap: 32bit- 64bit- 128bitCAS-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF 
Disabled
			 AtomicOpsCtl: ReqEn-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- 
ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, 
EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [100 v2] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- 
MalfTLP- ECRC- UnsupReq- ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- 
MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ 
MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		AERCap:	First Error Pointer: 00, ECRCGenCap+ ECRCGenEn- ECRCChkCap+ 
ECRCChkEn-
			MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
		HeaderLog: 00000000 00000000 00000000 00000000
	Capabilities: [140 v1] Device Serial Number 00-0d-b9-ff-ff-4b-48-a6
	Capabilities: [1a0 v1] Transaction Processing Hints
		Device specific mode supported
		Steering table in TPH capability structure
	Kernel driver in use: igb
00: 86 80 39 15 07 04 10 00 03 00 00 02 10 00 00 00
10: 00 00 70 fe 00 00 00 00 01 30 00 00 00 00 72 fe
20: 00 00 00 00 00 00 00 00 00 00 00 00 86 80 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 01 00 00
40: 01 50 23 c8 08 20 00 00 00 00 00 00 00 00 00 00
50: 05 70 80 01 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 11 a0 04 80 03 00 00 00 03 20 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 ff ff ff ff
a0: 10 00 02 00 c2 8c 00 10 3f 28 10 00 11 5c 42 03
b0: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 1f 00 00 00 00 00 00 00 00 00 00 00
d0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

04:00.0 0280: 168c:003c
	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- 
Stepping- SERR- FastB2B- DisINTx+
	Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- 
<MAbort- >SERR- <PERR- INTx-
	Latency: 0, Cache Line Size: 64 bytes
	Interrupt: pin A routed to IRQ 52
	Region 0: Memory at fe200000 (64-bit, non-prefetchable) [size=2M]
	Expansion ROM at fe400000 [disabled] [size=64K]
	Capabilities: [40] Power Management version 2
		Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=375mA 
PME(D0-,D1-,D2-,D3hot-,D3cold-)
		Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
	Capabilities: [50] MSI: Enable+ Count=1/8 Maskable+ 64bit-
		Address: fee0f00c  Data: 41e3
		Masking: 00fe00fe  Pending: 00000000
	Capabilities: [70] Express (v2) Endpoint, MSI 00
		DevCap:	MaxPayload 256 bytes, PhantFunc 0, Latency L0s unlimited, L1 
<64us
			ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset- SlotPowerLimit 0.000W
		DevCtl:	Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
			RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop-
			MaxPayload 256 bytes, MaxReadReq 512 bytes
		DevSta:	CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
		LnkCap:	Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency 
L0s <4us, L1 <64us
			ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
		LnkCtl:	ASPM Disabled; RCB 64 bytes Disabled- CommClk+
			ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
		LnkSta:	Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- 
BWMgmt- ABWMgmt-
		DevCap2: Completion Timeout: Not Supported, TimeoutDis+, LTR-, OBFF 
Not Supported
			 AtomicOpsCap: 32bit- 64bit- 128bitCAS-
		DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF 
Disabled
			 AtomicOpsCtl: ReqEn-
		LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
			 Transmit Margin: Normal Operating Range, EnterModifiedCompliance- 
ComplianceSOS-
			 Compliance De-emphasis: -6dB
		LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, 
EqualizationPhase1-
			 EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
	Capabilities: [100 v1] Advanced Error Reporting
		UESta:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- 
MalfTLP- ECRC- UnsupReq- ACSViol-
		UEMsk:	DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- 
MalfTLP- ECRC- UnsupReq- ACSViol-
		UESvrt:	DLP+ SDES+ TLP- FCP+ CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ 
MalfTLP+ ECRC- UnsupReq- ACSViol-
		CESta:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
		CEMsk:	RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
		AERCap:	First Error Pointer: 00, ECRCGenCap- ECRCGenEn- ECRCChkCap- 
ECRCChkEn-
			MultHdrRecCap- MultHdrRecEn- TLPPfxPres- HdrLogCap-
		HeaderLog: 00000000 00000000 00000000 00000000
	Capabilities: [140 v1] Virtual Channel
		Caps:	LPEVC=0 RefClk=100ns PATEntryBits=1
		Arb:	Fixed- WRR32- WRR64- WRR128-
		Ctrl:	ArbSelect=Fixed
		Status:	InProgress-
		VC0:	Caps:	PATOffset=00 MaxTimeSlots=1 RejSnoopTrans-
			Arb:	Fixed- WRR32- WRR64- WRR128- TWRR128- WRR256-
			Ctrl:	Enable+ ID=0 ArbSelect=Fixed TC/VC=ff
			Status:	NegoPending- InProgress-
	Capabilities: [160 v1] Device Serial Number 00-00-00-00-00-00-00-00
	Kernel driver in use: ath10k_pci
00: 8c 16 3c 00 06 04 10 00 00 00 80 02 10 00 00 00
10: 04 00 20 fe 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 40 fe 40 00 00 00 00 00 00 00 00 01 00 00
40: 01 50 c2 07 00 00 00 00 00 00 00 00 00 00 00 00
50: 05 70 07 01 0c f0 e0 fe e3 41 00 00 fe 00 fe 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 10 00 02 00 c1 8d 00 00 30 20 00 00 11 6c 03 00
80: 40 00 11 10 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 10 00 00 00 00 00 00 00 02 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

[Andy Shevchenko]

On Thu, Nov 29, 2018 at 12:15 PM Florian Eckert <fe@dev.tdt.de> wrote:
>
> Hello Andy,
>
> Thank you very very much for your code review "again" I will update my
> patch set with your hints.
> Should I send v6 or should i wait till I get feedback from you about
> ACPI?
>
> >>
> >> Until now it was not possible to get more information to detect the
> >> MMIO_BASE address from the ACPI subsystem.
> >
> > I'm sorry if I already asked, please, remind me where dump of ACPI
> > tables can be found?
>
> https://www.spinics.net/lists/kernel/msg2887290.html

Unfortunately the file had been removed.

Btw, is the statement in above email still actual? "...I can fix
required things."

> > Also would be nice to have the output of `lspci -nk -vv -xxx` on such
> > platform.

> 00:14.3 0601: 1022:780e (rev 11)
>         Subsystem: 1022:780e
>         Control: I/O+ Mem+ BusMaster+ SpecCycle+ MemWINV- VGASnoop- ParErr-
> Stepping- SERR- FastB2B- DisINTx-
>         Status: Cap- 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort-
> <TAbort- <MAbort- >SERR- <PERR- INTx-
>         Latency: 0
> 00: 22 10 0e 78 0f 00 20 02 11 00 01 06 00 00 80 00
> 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 0e 78
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 40: 04 00 00 00 d5 ff 03 ff 07 ff 20 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 0e 10 00 0e 00 0f 00 00 ff ff ff
> 70: 67 45 23 00 00 00 00 00 90 00 00 00 05 0a 00 00
> 80: 08 00 03 a8 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 02 00 c1 fe 2f 01 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 04 00 e9 3d 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 80 47 10 82 ff
> d0: 86 ff ff 08 42 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Thanks.

--
With Best Regards,
Andy Shevchenko

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

[Florian Eckert]

>> Thank you very very much for your code review "again" I will update my
>> patch set with your hints.
>> Should I send v6 or should i wait till I get feedback from you about
>> ACPI?
>> 
>> >>
>> >> Until now it was not possible to get more information to detect the
>> >> MMIO_BASE address from the ACPI subsystem.
>> >
>> > I'm sorry if I already asked, please, remind me where dump of ACPI
>> > tables can be found?
>> 
>> https://www.spinics.net/lists/kernel/msg2887290.html
> 
> Unfortunately the file had been removed.
> 
> Btw, is the statement in above email still actual? "...I can fix
> required things."
> 

Yes i will fix your hints tomorrow and send a v6 of my patchset.
Thank you for your hints and time
It would be nice if you could fix ACPI problemmatik.

Best regards
Florian Eckert

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

[Andy Shevchenko]

On Thu, Nov 29, 2018 at 4:02 PM Florian Eckert <fe@dev.tdt.de> wrote:
>
> >> Thank you very very much for your code review "again" I will update my
> >> patch set with your hints.
> >> Should I send v6 or should i wait till I get feedback from you about
> >> ACPI?
> >>
> >> >>
> >> >> Until now it was not possible to get more information to detect the
> >> >> MMIO_BASE address from the ACPI subsystem.
> >> >
> >> > I'm sorry if I already asked, please, remind me where dump of ACPI
> >> > tables can be found?
> >>
> >> https://www.spinics.net/lists/kernel/msg2887290.html
> >
> > Unfortunately the file had been removed.
> >
> > Btw, is the statement in above email still actual? "...I can fix
> > required things."

> Yes i will fix your hints tomorrow and send a v6 of my patchset.
> Thank you for your hints and time
> It would be nice if you could fix ACPI problemmatik.

I would like to see the ACPI dump for that...

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

[Florian Eckert]

Hello Andy

>> > Btw, is the statement in above email still actual? "...I can fix
>> > required things."
> 
>> Yes i will fix your hints tomorrow and send a v6 of my patchset.
>> Thank you for your hints and time
>> It would be nice if you could fix ACPI problemmatik.
> 
> I would like to see the ACPI dump for that...

See https://github.com/openwrt/openwrt/pull/1232#issuecomment-443224576
In this comment Michał Żygowski appended to this thread the missing
files you want to have.

Regards
Flo

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

[Andy Shevchenko]

On Mon, Dec 3, 2018 at 9:58 AM Florian Eckert <fe@dev.tdt.de> wrote:

> >> > Btw, is the statement in above email still actual? "...I can fix
> >> > required things."
> >
> >> Yes i will fix your hints tomorrow and send a v6 of my patchset.
> >> Thank you for your hints and time
> >> It would be nice if you could fix ACPI problemmatik.
> >
> > I would like to see the ACPI dump for that...
>
> See https://github.com/openwrt/openwrt/pull/1232#issuecomment-443224576
> In this comment Michał Żygowski appended to this thread the missing
> files you want to have.

Thanks!

So, let me clarify what we have:
 - some platforms are in the wild with old BIOS with broken ACPI tables
 - you still may fix the things for new BIOS version for all affected platforms
 - you need to support both

Is this all correct?

For broken firmware you need to do the following:
 - create an MFD driver, which would instantiate GPIO and GPIO keys
support (at least)
 - create one of each above drivers w/o any DMI crap (should be done
as a part of MFD driver)

For fixed BIOS you need to add the following (example, not a fully
correct solution) at the level behind SB:

Scope (SB)
{
  Device(GPIO)
  {
           Name (_ADR, Zero)  // _ADR: Address
           Name (_HID, "AMDxxxx") // One ID per platform, so, APU2 :
1, APU 3: 1 => 2 unique IDs, in this case no need to add neither _HRV
nor _UID
           Name (_HRV, 2)          // Other approach is to have one ID
but different _HRV: e.g. 2 for APU2, 3 for APU3
           Name (_UID, Zero)        // Another approach is to have one
device per community of pins and several _UID:s
           Name (_DDN, "AMD APU General Purpose Input/Output (GPIO) controller")
           Method (_CRS, 0, NotSerialized)
           {
               Name (RBUF, ResourceTemplate ()
               {
                   Memory32Fixed (ReadWrite,
                       0xFED80000 // + offset + community0 offset
                       0x0000xxxx, // + size of the community0
                       )
...
                  Memory32Fixed (ReadWrite,
                       0xFED80000 // + offset + communityN offset
                       0x0000xxxx, // + size of the communityN
                       )
                   /* IRQ resource if needed and present on real HW */
                   Interrupt (ResourceConsumer, Level, ActiveLow, Shared, ,, )
                   {
                       0x000000xx,
                   }
               })
               Return (RBUF) /* \_SB_.GPIO._CRS.RBUF */
           }

           Method (_STA, 0, NotSerialized)
           {
               Return (0x0F)
           }
  }

  Device (BTNS)
  {
           Name (_HID, "PRP0001")
           Name (_DDN, "GPIO buttons device")
           Name (_CRS, ResourceTemplate () {
               GpioIo (
                   Exclusive,                  // Not shared
                   PullUp,                     // Pull up the line
                   0,                          // Debounce timeout
                   0,                          // Drive strength
                   IoRestrictionInputOnly,     // Only used as input
                   "\\_SB.GPIO",           // GPIO controller
                   0)                          // Must be 0
               {
                   x0,                         // GPIO pin offset in
corresponding controller for Button 0
                   x1,                         // for Button 1, and so on
...
               }
           })

           Name (_DSD, Package () {
               ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
               Package () {
                   Package () {"compatible", "gpio-keys-polled"},
                   Package () {"poll-interval", 100},
                   Package () {"autorepeat", 1}
               },
               ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),
               Package () {
                   Package () {"button-0", "BTN0"},
                   Package () {"button-1", "BTN1"},
...
               }
           })

           // For more information about these bindings see:
           // Documentation/devicetree/bindings/input/gpio-keys-polled.txt
           // and Documentation/acpi/gpio-properties.txt.

           Name (BTN0, Package () {
               ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
               Package () {
                   Package () {"linux,code", 105},
                   Package () {"linux,input-type", 1},
                   Package () {"gpios", Package () {^BTNS, 0, 0, 1}}
               }
           })

  }
}

After updating firmware you would need just an ACPI ID table to be
added to the GPIO driver. MFD driver should not be enumerated at all.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v5 0/2] Add device driver for APU2/APU3 GPIOs

[Florian Eckert]

>> >> Yes i will fix your hints tomorrow and send a v6 of my patchset.
>> >> Thank you for your hints and time
>> >> It would be nice if you could fix ACPI problemmatik.
>> >
>> > I would like to see the ACPI dump for that...
>> 
>> See 
>> https://github.com/openwrt/openwrt/pull/1232#issuecomment-443224576
>> In this comment Michał Żygowski appended to this thread the missing
>> files you want to have.

> So, let me clarify what we have:
>  - some platforms are in the wild with old BIOS with broken ACPI tables

correct

>  - you still may fix the things for new BIOS version for all affected 
> platforms

I have seen that this is a lot of work and I didn't think it was so 
complicated!
To get the GPIO support for APU2/APU3 merged into the gpio subsystem.
I am little confused what i should do now. By the way I only have one 
board (APU3).

>  - you need to support both

That is not necessary from my point of view. I am fine if the driver 
supports at least
the current BIOS version. And if the coreboot maintainer fixes the ACPI 
problem
then we could extend the driver and add the ACPI stuff.
But this not in my hand, right?

> For broken firmware you need to do the following:
>  - create an MFD driver, which would instantiate GPIO and GPIO keys
> support (at least)
>  - create one of each above drivers w/o any DMI crap (should be done
> as a part of MFD driver)

I will have a look how to achieve this.
If we want to support all BIOS version.
And is a must have to get the driver into mainline.

> For fixed BIOS you need to add the following (example, not a fully
> correct solution) at the level behind SB:

I do not understand how I could fix this. I have no idea from ACPI.
I have not found any driver where I can inspire myself.

> 
> Scope (SB)
> {
>   Device(GPIO)
>   {

> After updating firmware you would need just an ACPI ID table to be
> added to the GPIO driver. MFD driver should not be enumerated at all.

That's maybe coming next when the coreboot maintainers have their bios 
fixed, right?