[PATCH 1/2] mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT

[PATCH 1/2] mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT

[Hans de Goede]

Both Bay and Cherry Trail devices may be used together with a Crystal Cove
PMIC. Each platform has its own variant of the PMIC, which both use the
same ACPI HID, but they are not 100% compatible.

Looking at the android x86 kernel sources where most of the Crystal Cove
code comes from, it talks about "Valley View", "Bay Trail" and / or BYT
without ever mentioning Cherry Trail, with the exception of the regulator
driver. The Asus Zenfone-2 kernel code has 2 regulator drivers, one
for Crystal Cove and one for what it calls Crystal Cove Plus. The
Crystal Cove Plus regulator driver is the only one to mention Cherry
Trail and that driver uses different register addresses then the
normal (Bay Trail) Crystal Cove regulator driver, showing that at
least the regulator register addresses are different.

The GPIO code should work on both, and the PWM code is known to work on
both and is necessary for backlight control on some Cherry Trail devices.

Testing has shown that the ACPI OpRegion code otoh is causing problems
on Cherry Trail devices, which is not surprising as it deals with the
regulators and those have different register addresses on CHT.

Specifically the ACPI OpRegion code causes the external microsd slot on
a Dell Venue 8 5855 (Cherry Trail version) to not work and the eMMC to
become unreliable and throw lots of errors.

This commit replaces the single mfd_cell array currently used for Crystal
Cove with 2 separate arrays, one for the Bay Trail variant and one for
the Cherry Trail variant, note that the Cherry Trail version of the array
only contains gpio and pwm cells. The PMIC OpRegion cell is deliberately
not included and drivers for the other cells in the Bay Trail cell array
were never upstreamed.

Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/mfd/intel_soc_pmic_core.c |  2 +-
 drivers/mfd/intel_soc_pmic_core.h |  3 ++-
 drivers/mfd/intel_soc_pmic_crc.c  | 27 +++++++++++++++++++++++----
 3 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c
index 13737be6df35..2234a847370a 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -157,7 +157,7 @@ MODULE_DEVICE_TABLE(i2c, intel_soc_pmic_i2c_id);
 
 #if defined(CONFIG_ACPI)
 static const struct acpi_device_id intel_soc_pmic_acpi_match[] = {
-	{"INT33FD", (kernel_ulong_t)&intel_soc_pmic_config_crc},
+	{"INT33FD", (kernel_ulong_t)&intel_soc_pmic_config_byt_crc},
 	{ },
 };
 MODULE_DEVICE_TABLE(acpi, intel_soc_pmic_acpi_match);
diff --git a/drivers/mfd/intel_soc_pmic_core.h b/drivers/mfd/intel_soc_pmic_core.h
index ff2464bc172f..90a1416d4dac 100644
--- a/drivers/mfd/intel_soc_pmic_core.h
+++ b/drivers/mfd/intel_soc_pmic_core.h
@@ -27,6 +27,7 @@ struct intel_soc_pmic_config {
 	const struct regmap_irq_chip *irq_chip;
 };
 
-extern struct intel_soc_pmic_config intel_soc_pmic_config_crc;
+extern struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc;
+extern struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc;
 
 #endif	/* __INTEL_SOC_PMIC_CORE_H__ */
diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
index 4a7494872da2..6d19a6d0fb97 100644
--- a/drivers/mfd/intel_soc_pmic_crc.c
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -80,7 +80,7 @@ static struct resource bcu_resources[] = {
 	},
 };
 
-static struct mfd_cell crystal_cove_dev[] = {
+static struct mfd_cell crystal_cove_byt_dev[] = {
 	{
 		.name = "crystal_cove_pwrsrc",
 		.num_resources = ARRAY_SIZE(pwrsrc_resources),
@@ -114,6 +114,17 @@ static struct mfd_cell crystal_cove_dev[] = {
 	},
 };
 
+static struct mfd_cell crystal_cove_cht_dev[] = {
+	{
+		.name = "crystal_cove_gpio",
+		.num_resources = ARRAY_SIZE(gpio_resources),
+		.resources = gpio_resources,
+	},
+	{
+		.name = "crystal_cove_pwm",
+	},
+};
+
 static const struct regmap_config crystal_cove_regmap_config = {
 	.reg_bits = 8,
 	.val_bits = 8,
@@ -155,10 +166,18 @@ static const struct regmap_irq_chip crystal_cove_irq_chip = {
 	.mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
 };
 
-struct intel_soc_pmic_config intel_soc_pmic_config_crc = {
+struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = {
+	.irq_flags = IRQF_TRIGGER_RISING,
+	.cell_dev = crystal_cove_byt_dev,
+	.n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
+	.regmap_config = &crystal_cove_regmap_config,
+	.irq_chip = &crystal_cove_irq_chip,
+};
+
+struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = {
 	.irq_flags = IRQF_TRIGGER_RISING,
-	.cell_dev = crystal_cove_dev,
-	.n_cell_devs = ARRAY_SIZE(crystal_cove_dev),
+	.cell_dev = crystal_cove_cht_dev,
+	.n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
 	.regmap_config = &crystal_cove_regmap_config,
 	.irq_chip = &crystal_cove_irq_chip,
 };
-- 
2.13.0

[PATCH 2/2] mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants

[Hans de Goede]

Both Bay and Cherry Trail devices may be used together with a Crystal Cove
PMIC. Each platform has its own variant of the PMIC, which both use the
same ACPI HID, but they are not 100% compatible.

This commits makes the intel_soc_pmic_core code check the _HRV of the
ACPI-firmware-node and selects intel_soc_pmic_config_byt_crc resp.
intel_soc_pmic_config_cht_crc based on this.

This fixes the Bay Trail specific ACPI OpRegion code causing problems
on Cherry Trail devices. Specifically this was causing the external
microsd slot on a Dell Venue 8 5855 (Cherry Trail version) to not work
and the eMMC to become unreliable and throw lots of errors.

Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/mfd/Kconfig               |  4 ++--
 drivers/mfd/intel_soc_pmic_core.c | 34 ++++++++++++++++++++++++++++------
 2 files changed, 30 insertions(+), 8 deletions(-)

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 44e7164b5063..8533cb46a875 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -448,12 +448,12 @@ config LPC_SCH
 
 config INTEL_SOC_PMIC
 	bool "Support for Crystal Cove PMIC"
-	depends on HAS_IOMEM && I2C=y && GPIOLIB && COMMON_CLK
+	depends on ACPI && HAS_IOMEM && I2C=y && GPIOLIB && COMMON_CLK
 	depends on X86 || COMPILE_TEST
 	select MFD_CORE
 	select REGMAP_I2C
 	select REGMAP_IRQ
-	select I2C_DESIGNWARE_PLATFORM if ACPI
+	select I2C_DESIGNWARE_PLATFORM
 	help
 	  Select this option to enable support for Crystal Cove PMIC
 	  on some Intel SoC systems. The PMIC provides ADC, GPIO,
diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c
index 2234a847370a..36adf9e8153e 100644
--- a/drivers/mfd/intel_soc_pmic_core.c
+++ b/drivers/mfd/intel_soc_pmic_core.c
@@ -16,6 +16,7 @@
  * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
  */
 
+#include <linux/acpi.h>
 #include <linux/module.h>
 #include <linux/mfd/core.h>
 #include <linux/i2c.h>
@@ -28,6 +29,10 @@
 #include <linux/pwm.h>
 #include "intel_soc_pmic_core.h"
 
+/* Crystal Cove PMIC shares same ACPI ID between different platforms */
+#define BYT_CRC_HRV		2
+#define CHT_CRC_HRV		3
+
 /* Lookup table for the Panel Enable/Disable line as GPIO signals */
 static struct gpiod_lookup_table panel_gpio_table = {
 	/* Intel GFX is consumer */
@@ -48,16 +53,33 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
 				    const struct i2c_device_id *i2c_id)
 {
 	struct device *dev = &i2c->dev;
-	const struct acpi_device_id *id;
 	struct intel_soc_pmic_config *config;
 	struct intel_soc_pmic *pmic;
+	unsigned long long hrv;
+	acpi_status status;
 	int ret;
 
-	id = acpi_match_device(dev->driver->acpi_match_table, dev);
-	if (!id || !id->driver_data)
+	/*
+	 * There are 2 different Crystal Cove PMICs a Bay Trail and Cherry
+	 * Trail version, use _HRV to differentiate between the 2.
+	 */
+	status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
+	if (ACPI_FAILURE(status)) {
+		dev_err(dev, "Failed to get PMIC hardware revision\n");
 		return -ENODEV;
-
-	config = (struct intel_soc_pmic_config *)id->driver_data;
+	}
+
+	switch (hrv) {
+	case BYT_CRC_HRV:
+		config = &intel_soc_pmic_config_byt_crc;
+		break;
+	case CHT_CRC_HRV:
+		config = &intel_soc_pmic_config_cht_crc;
+		break;
+	default:
+		dev_warn(dev, "Unknown hardware rev %llu, assuming BYT\n", hrv);
+		config = &intel_soc_pmic_config_byt_crc;
+	}
 
 	pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
 	if (!pmic)
@@ -157,7 +179,7 @@ MODULE_DEVICE_TABLE(i2c, intel_soc_pmic_i2c_id);
 
 #if defined(CONFIG_ACPI)
 static const struct acpi_device_id intel_soc_pmic_acpi_match[] = {
-	{"INT33FD", (kernel_ulong_t)&intel_soc_pmic_config_byt_crc},
+	{ "INT33FD" },
 	{ },
 };
 MODULE_DEVICE_TABLE(acpi, intel_soc_pmic_acpi_match);
-- 
2.13.0

Re: [PATCH 1/2] mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT

[Andy Shevchenko]

On Sat, Jul 1, 2017 at 1:13 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Both Bay and Cherry Trail devices may be used together with a Crystal Cove
> PMIC. Each platform has its own variant of the PMIC, which both use the
> same ACPI HID, but they are not 100% compatible.
>
> Looking at the android x86 kernel sources where most of the Crystal Cove
> code comes from, it talks about "Valley View", "Bay Trail" and / or BYT
> without ever mentioning Cherry Trail, with the exception of the regulator
> driver. The Asus Zenfone-2 kernel code has 2 regulator drivers, one
> for Crystal Cove and one for what it calls Crystal Cove Plus. The
> Crystal Cove Plus regulator driver is the only one to mention Cherry
> Trail and that driver uses different register addresses then the
> normal (Bay Trail) Crystal Cove regulator driver, showing that at
> least the regulator register addresses are different.
>
> The GPIO code should work on both, and the PWM code is known to work on
> both and is necessary for backlight control on some Cherry Trail devices.
>
> Testing has shown that the ACPI OpRegion code otoh is causing problems
> on Cherry Trail devices, which is not surprising as it deals with the
> regulators and those have different register addresses on CHT.
>
> Specifically the ACPI OpRegion code causes the external microsd slot on
> a Dell Venue 8 5855 (Cherry Trail version) to not work and the eMMC to
> become unreliable and throw lots of errors.
>
> This commit replaces the single mfd_cell array currently used for Crystal
> Cove with 2 separate arrays, one for the Bay Trail variant and one for
> the Cherry Trail variant, note that the Cherry Trail version of the array
> only contains gpio and pwm cells. The PMIC OpRegion cell is deliberately
> not included and drivers for the other cells in the Bay Trail cell array
> were never upstreamed.
>

Looks good to me.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>

> Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  drivers/mfd/intel_soc_pmic_core.c |  2 +-
>  drivers/mfd/intel_soc_pmic_core.h |  3 ++-
>  drivers/mfd/intel_soc_pmic_crc.c  | 27 +++++++++++++++++++++++----
>  3 files changed, 26 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c
> index 13737be6df35..2234a847370a 100644
> --- a/drivers/mfd/intel_soc_pmic_core.c
> +++ b/drivers/mfd/intel_soc_pmic_core.c
> @@ -157,7 +157,7 @@ MODULE_DEVICE_TABLE(i2c, intel_soc_pmic_i2c_id);
>
>  #if defined(CONFIG_ACPI)
>  static const struct acpi_device_id intel_soc_pmic_acpi_match[] = {
> -       {"INT33FD", (kernel_ulong_t)&intel_soc_pmic_config_crc},
> +       {"INT33FD", (kernel_ulong_t)&intel_soc_pmic_config_byt_crc},
>         { },
>  };
>  MODULE_DEVICE_TABLE(acpi, intel_soc_pmic_acpi_match);
> diff --git a/drivers/mfd/intel_soc_pmic_core.h b/drivers/mfd/intel_soc_pmic_core.h
> index ff2464bc172f..90a1416d4dac 100644
> --- a/drivers/mfd/intel_soc_pmic_core.h
> +++ b/drivers/mfd/intel_soc_pmic_core.h
> @@ -27,6 +27,7 @@ struct intel_soc_pmic_config {
>         const struct regmap_irq_chip *irq_chip;
>  };
>
> -extern struct intel_soc_pmic_config intel_soc_pmic_config_crc;
> +extern struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc;
> +extern struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc;
>
>  #endif /* __INTEL_SOC_PMIC_CORE_H__ */
> diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
> index 4a7494872da2..6d19a6d0fb97 100644
> --- a/drivers/mfd/intel_soc_pmic_crc.c
> +++ b/drivers/mfd/intel_soc_pmic_crc.c
> @@ -80,7 +80,7 @@ static struct resource bcu_resources[] = {
>         },
>  };
>
> -static struct mfd_cell crystal_cove_dev[] = {
> +static struct mfd_cell crystal_cove_byt_dev[] = {
>         {
>                 .name = "crystal_cove_pwrsrc",
>                 .num_resources = ARRAY_SIZE(pwrsrc_resources),
> @@ -114,6 +114,17 @@ static struct mfd_cell crystal_cove_dev[] = {
>         },
>  };
>
> +static struct mfd_cell crystal_cove_cht_dev[] = {
> +       {
> +               .name = "crystal_cove_gpio",
> +               .num_resources = ARRAY_SIZE(gpio_resources),
> +               .resources = gpio_resources,
> +       },
> +       {
> +               .name = "crystal_cove_pwm",
> +       },
> +};
> +
>  static const struct regmap_config crystal_cove_regmap_config = {
>         .reg_bits = 8,
>         .val_bits = 8,
> @@ -155,10 +166,18 @@ static const struct regmap_irq_chip crystal_cove_irq_chip = {
>         .mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
>  };
>
> -struct intel_soc_pmic_config intel_soc_pmic_config_crc = {
> +struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = {
> +       .irq_flags = IRQF_TRIGGER_RISING,
> +       .cell_dev = crystal_cove_byt_dev,
> +       .n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
> +       .regmap_config = &crystal_cove_regmap_config,
> +       .irq_chip = &crystal_cove_irq_chip,
> +};
> +
> +struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = {
>         .irq_flags = IRQF_TRIGGER_RISING,
> -       .cell_dev = crystal_cove_dev,
> -       .n_cell_devs = ARRAY_SIZE(crystal_cove_dev),
> +       .cell_dev = crystal_cove_cht_dev,
> +       .n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
>         .regmap_config = &crystal_cove_regmap_config,
>         .irq_chip = &crystal_cove_irq_chip,
>  };
> --
> 2.13.0
>



-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 2/2] mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants

[Andy Shevchenko]

On Sat, Jul 1, 2017 at 1:13 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Both Bay and Cherry Trail devices may be used together with a Crystal Cove
> PMIC. Each platform has its own variant of the PMIC, which both use the
> same ACPI HID, but they are not 100% compatible.
>
> This commits makes the intel_soc_pmic_core code check the _HRV of the
> ACPI-firmware-node and selects intel_soc_pmic_config_byt_crc resp.
> intel_soc_pmic_config_cht_crc based on this.
>
> This fixes the Bay Trail specific ACPI OpRegion code causing problems
> on Cherry Trail devices. Specifically this was causing the external
> microsd slot on a Dell Venue 8 5855 (Cherry Trail version) to not work
> and the eMMC to become unreliable and throw lots of errors.
>

Fine to me
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>

> Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  drivers/mfd/Kconfig               |  4 ++--
>  drivers/mfd/intel_soc_pmic_core.c | 34 ++++++++++++++++++++++++++++------
>  2 files changed, 30 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 44e7164b5063..8533cb46a875 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -448,12 +448,12 @@ config LPC_SCH
>
>  config INTEL_SOC_PMIC
>         bool "Support for Crystal Cove PMIC"
> -       depends on HAS_IOMEM && I2C=y && GPIOLIB && COMMON_CLK
> +       depends on ACPI && HAS_IOMEM && I2C=y && GPIOLIB && COMMON_CLK
>         depends on X86 || COMPILE_TEST
>         select MFD_CORE
>         select REGMAP_I2C
>         select REGMAP_IRQ
> -       select I2C_DESIGNWARE_PLATFORM if ACPI
> +       select I2C_DESIGNWARE_PLATFORM
>         help
>           Select this option to enable support for Crystal Cove PMIC
>           on some Intel SoC systems. The PMIC provides ADC, GPIO,
> diff --git a/drivers/mfd/intel_soc_pmic_core.c b/drivers/mfd/intel_soc_pmic_core.c
> index 2234a847370a..36adf9e8153e 100644
> --- a/drivers/mfd/intel_soc_pmic_core.c
> +++ b/drivers/mfd/intel_soc_pmic_core.c
> @@ -16,6 +16,7 @@
>   * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
>   */
>
> +#include <linux/acpi.h>
>  #include <linux/module.h>
>  #include <linux/mfd/core.h>
>  #include <linux/i2c.h>
> @@ -28,6 +29,10 @@
>  #include <linux/pwm.h>
>  #include "intel_soc_pmic_core.h"
>
> +/* Crystal Cove PMIC shares same ACPI ID between different platforms */
> +#define BYT_CRC_HRV            2
> +#define CHT_CRC_HRV            3
> +
>  /* Lookup table for the Panel Enable/Disable line as GPIO signals */
>  static struct gpiod_lookup_table panel_gpio_table = {
>         /* Intel GFX is consumer */
> @@ -48,16 +53,33 @@ static int intel_soc_pmic_i2c_probe(struct i2c_client *i2c,
>                                     const struct i2c_device_id *i2c_id)
>  {
>         struct device *dev = &i2c->dev;
> -       const struct acpi_device_id *id;
>         struct intel_soc_pmic_config *config;
>         struct intel_soc_pmic *pmic;
> +       unsigned long long hrv;
> +       acpi_status status;
>         int ret;
>
> -       id = acpi_match_device(dev->driver->acpi_match_table, dev);
> -       if (!id || !id->driver_data)
> +       /*
> +        * There are 2 different Crystal Cove PMICs a Bay Trail and Cherry
> +        * Trail version, use _HRV to differentiate between the 2.
> +        */
> +       status = acpi_evaluate_integer(ACPI_HANDLE(dev), "_HRV", NULL, &hrv);
> +       if (ACPI_FAILURE(status)) {
> +               dev_err(dev, "Failed to get PMIC hardware revision\n");
>                 return -ENODEV;
> -
> -       config = (struct intel_soc_pmic_config *)id->driver_data;
> +       }
> +
> +       switch (hrv) {
> +       case BYT_CRC_HRV:
> +               config = &intel_soc_pmic_config_byt_crc;
> +               break;
> +       case CHT_CRC_HRV:
> +               config = &intel_soc_pmic_config_cht_crc;
> +               break;
> +       default:
> +               dev_warn(dev, "Unknown hardware rev %llu, assuming BYT\n", hrv);
> +               config = &intel_soc_pmic_config_byt_crc;
> +       }
>
>         pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
>         if (!pmic)
> @@ -157,7 +179,7 @@ MODULE_DEVICE_TABLE(i2c, intel_soc_pmic_i2c_id);
>
>  #if defined(CONFIG_ACPI)
>  static const struct acpi_device_id intel_soc_pmic_acpi_match[] = {
> -       {"INT33FD", (kernel_ulong_t)&intel_soc_pmic_config_byt_crc},
> +       { "INT33FD" },
>         { },
>  };
>  MODULE_DEVICE_TABLE(acpi, intel_soc_pmic_acpi_match);
> --
> 2.13.0
>



-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH 2/2] mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants

[Lee Jones]

On Sat, 01 Jul 2017, Hans de Goede wrote:

> Both Bay and Cherry Trail devices may be used together with a Crystal Cove
> PMIC. Each platform has its own variant of the PMIC, which both use the
> same ACPI HID, but they are not 100% compatible.
> 
> This commits makes the intel_soc_pmic_core code check the _HRV of the
> ACPI-firmware-node and selects intel_soc_pmic_config_byt_crc resp.
> intel_soc_pmic_config_cht_crc based on this.
> 
> This fixes the Bay Trail specific ACPI OpRegion code causing problems
> on Cherry Trail devices. Specifically this was causing the external
> microsd slot on a Dell Venue 8 5855 (Cherry Trail version) to not work
> and the eMMC to become unreliable and throw lots of errors.
> 
> Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru>

Real names only please.

What is the name of this reporter/tester?

> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  drivers/mfd/Kconfig               |  4 ++--
>  drivers/mfd/intel_soc_pmic_core.c | 34 ++++++++++++++++++++++++++++------
>  2 files changed, 30 insertions(+), 8 deletions(-)

Code looks okay though:

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
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Re: [PATCH 1/2] mfd: intel_soc_pmic: Export separate mfd-cell configs for BYT and CHT

[Lee Jones]

On Sat, 01 Jul 2017, Hans de Goede wrote:

> Both Bay and Cherry Trail devices may be used together with a Crystal Cove
> PMIC. Each platform has its own variant of the PMIC, which both use the
> same ACPI HID, but they are not 100% compatible.
> 
> Looking at the android x86 kernel sources where most of the Crystal Cove
> code comes from, it talks about "Valley View", "Bay Trail" and / or BYT
> without ever mentioning Cherry Trail, with the exception of the regulator
> driver. The Asus Zenfone-2 kernel code has 2 regulator drivers, one
> for Crystal Cove and one for what it calls Crystal Cove Plus. The
> Crystal Cove Plus regulator driver is the only one to mention Cherry
> Trail and that driver uses different register addresses then the
> normal (Bay Trail) Crystal Cove regulator driver, showing that at
> least the regulator register addresses are different.
> 
> The GPIO code should work on both, and the PWM code is known to work on
> both and is necessary for backlight control on some Cherry Trail devices.
> 
> Testing has shown that the ACPI OpRegion code otoh is causing problems
> on Cherry Trail devices, which is not surprising as it deals with the
> regulators and those have different register addresses on CHT.
> 
> Specifically the ACPI OpRegion code causes the external microsd slot on
> a Dell Venue 8 5855 (Cherry Trail version) to not work and the eMMC to
> become unreliable and throw lots of errors.
> 
> This commit replaces the single mfd_cell array currently used for Crystal
> Cove with 2 separate arrays, one for the Bay Trail variant and one for
> the Cherry Trail variant, note that the Cherry Trail version of the array
> only contains gpio and pwm cells. The PMIC OpRegion cell is deliberately
> not included and drivers for the other cells in the Bay Trail cell array
> were never upstreamed.
> 
> Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  drivers/mfd/intel_soc_pmic_core.c |  2 +-
>  drivers/mfd/intel_soc_pmic_core.h |  3 ++-
>  drivers/mfd/intel_soc_pmic_crc.c  | 27 +++++++++++++++++++++++----
>  3 files changed, 26 insertions(+), 6 deletions(-)

For my own reference:
  Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
  
-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH 2/2] mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants

[Andy Shevchenko]

On Mon, 2017-07-17 at 11:59 +0100, Lee Jones wrote:
> On Sat, 01 Jul 2017, Hans de Goede wrote:
> 
> > Both Bay and Cherry Trail devices may be used together with a
> > Crystal Cove
> > PMIC. Each platform has its own variant of the PMIC, which both use
> > the
> > same ACPI HID, but they are not 100% compatible.
> > 
> > This commits makes the intel_soc_pmic_core code check the _HRV of
> > the
> > ACPI-firmware-node and selects intel_soc_pmic_config_byt_crc resp.
> > intel_soc_pmic_config_cht_crc based on this.
> > 
> > This fixes the Bay Trail specific ACPI OpRegion code causing
> > problems
> > on Cherry Trail devices. Specifically this was causing the external
> > microsd slot on a Dell Venue 8 5855 (Cherry Trail version) to not
> > work
> > and the eMMC to become unreliable and throw lots of errors.
> > 
> > Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru
> > >
> 
> Real names only please.
> 
> What is the name of this reporter/tester?

No one knows, I think.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

Re: [PATCH 2/2] mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants

[Lee Jones]

On Mon, 17 Jul 2017, Andy Shevchenko wrote:

> On Mon, 2017-07-17 at 11:59 +0100, Lee Jones wrote:
> > On Sat, 01 Jul 2017, Hans de Goede wrote:
> > 
> > > Both Bay and Cherry Trail devices may be used together with a
> > > Crystal Cove
> > > PMIC. Each platform has its own variant of the PMIC, which both use
> > > the
> > > same ACPI HID, but they are not 100% compatible.
> > > 
> > > This commits makes the intel_soc_pmic_core code check the _HRV of
> > > the
> > > ACPI-firmware-node and selects intel_soc_pmic_config_byt_crc resp.
> > > intel_soc_pmic_config_cht_crc based on this.
> > > 
> > > This fixes the Bay Trail specific ACPI OpRegion code causing
> > > problems
> > > on Cherry Trail devices. Specifically this was causing the external
> > > microsd slot on a Dell Venue 8 5855 (Cherry Trail version) to not
> > > work
> > > and the eMMC to become unreliable and throw lots of errors.
> > > 
> > > Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru
> > > >
> > 
> > Real names only please.
> > 
> > What is the name of this reporter/tester?
> 
> No one knows, I think.

Then I don't think we can credit him/her for their efforts.
SubmittingPatches clearly states "no pseudonyms or anonymous
contributions".  Either write to them and ask for their real name so
that they can be credited, or remove the line.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH 2/2] mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants

[Hans de Goede]

Hi,

On 18-07-17 09:17, Lee Jones wrote:
> On Mon, 17 Jul 2017, Andy Shevchenko wrote:
> 
>> On Mon, 2017-07-17 at 11:59 +0100, Lee Jones wrote:
>>> On Sat, 01 Jul 2017, Hans de Goede wrote:
>>>
>>>> Both Bay and Cherry Trail devices may be used together with a
>>>> Crystal Cove
>>>> PMIC. Each platform has its own variant of the PMIC, which both use
>>>> the
>>>> same ACPI HID, but they are not 100% compatible.
>>>>
>>>> This commits makes the intel_soc_pmic_core code check the _HRV of
>>>> the
>>>> ACPI-firmware-node and selects intel_soc_pmic_config_byt_crc resp.
>>>> intel_soc_pmic_config_cht_crc based on this.
>>>>
>>>> This fixes the Bay Trail specific ACPI OpRegion code causing
>>>> problems
>>>> on Cherry Trail devices. Specifically this was causing the external
>>>> microsd slot on a Dell Venue 8 5855 (Cherry Trail version) to not
>>>> work
>>>> and the eMMC to become unreliable and throw lots of errors.
>>>>
>>>> Reported-and-tested-by: russianneuromancer <russianneuromancer@ya.ru
>>>>>
>>>
>>> Real names only please.
>>>
>>> What is the name of this reporter/tester?
>>
>> No one knows, I think.
> 
> Then I don't think we can credit him/her for their efforts.
> SubmittingPatches clearly states "no pseudonyms or anonymous
> contributions".  Either write to them and ask for their real name so
> that they can be credited, or remove the line.

russianneuromancer has been a great help with reporting and testing
many Bay Trail / Cherry Trail issues. He does not want to use his
real name.

AFAIK the Real Name rule only applies tot he Signed-off-by tag, no
other subsys-maintainers have had problems with listing him as
reporter / tester using his alias.

The Real Name only rule is part of "11) Sign your work — the
Developer’s Certificate of Origin" of :

https://www.kernel.org/doc/html/latest/process/submitting-patches.html#sign-your-work-the-developer-s-certificate-of-origin

Which is all about the S-o-b tag. If you despite this still want
a new version with russianneuromancer's Reported-and-tested-by
dropped let me know and I will send a new version.

Regards,

Hans

Re: [PATCH 2/2] mfd: intel_soc_pmic: Differentiate between Bay and Cherry Trail CRC variants

[Andy Shevchenko]

On Fri, 2017-07-21 at 20:41 +0200, Hans de Goede wrote:
> On 18-07-17 09:17, Lee Jones wrote:
> > On Mon, 17 Jul 2017, Andy Shevchenko wrote:
> > 
> > > On Mon, 2017-07-17 at 11:59 +0100, Lee Jones wrote:
> > > > On Sat, 01 Jul 2017, Hans de Goede wrote:
> > > > 

> > > > > Reported-and-tested-by: russianneuromancer
> > > > > <russianneuromancer@ya.ru
> > > > > > 
> > > > 
> > > > Real names only please.
> > > > 
> > > > What is the name of this reporter/tester?
> > > 
> > > No one knows, I think.
> > 
> > Then I don't think we can credit him/her for their efforts.
> > SubmittingPatches clearly states "no pseudonyms or anonymous
> > contributions".  Either write to them and ask for their real name so
> > that they can be credited, or remove the line.
> 
> russianneuromancer has been a great help with reporting and testing
> many Bay Trail / Cherry Trail issues. He does not want to use his
> real name.
> 
> AFAIK the Real Name rule only applies tot he Signed-off-by tag, no
> other subsys-maintainers have had problems with listing him as
> reporter / tester using his alias.
> 
> The Real Name only rule is part of "11) Sign your work — the
> Developer’s Certificate of Origin" of :
> 
> https://www.kernel.org/doc/html/latest/process/submitting-patches.html
> #sign-your-work-the-developer-s-certificate-of-origin
> 
> Which is all about the S-o-b tag. If you despite this still want
> a new version with russianneuromancer's Reported-and-tested-by
> dropped let me know and I will send a new version.

I saw some patches applied just with email in tags like Reported-by.

So, I think everyone will be okay if you remove nick and leave email
only.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy