[PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

[PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

[Gayatri Kammela]

Hi,

Patch 1: Cleans up termination lines
Patch 2: Refactor driver for ease of adding new SoCs
Patch 3: Refactor debugfs entry for PCH IPs power gating status
Patch 4: Add Tiger Lake legacy support to pmc_core
Patch 5: Add Elkhart Lake legacy support to pmc_core

All the information regarding the PCH IPs and names of IPs will be available
in *future* Intel's Platform Controller Hub (PCH) External Design Specification
(EDS) document.

Gayatri Kammela (5):
  x86/intel_pmc_core: Clean up: Remove comma after the termination line
  x86/intel_pmc_core: Create platform dependent pmc bitmap structs
  x86/intel_pmc_core: Make debugfs entry for pch_ip_power_gating_status
    conditional
  platform/x86: Add Tiger Lake(TGL) platform support to intel_pmc_core
    driver
  platform/x86: Add Atom based Elkhart Lake(EHL) platform support to
    intel_pmc_core driver

 drivers/platform/x86/intel_pmc_core.c | 108 +++++++++++++++++++++-----
 drivers/platform/x86/intel_pmc_core.h |   2 +-
 2 files changed, 88 insertions(+), 22 deletions(-)

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: David E. Box <david.e.box@intel.com>
Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
-- 
2.17.1

[PATCH v1 1/5] x86/intel_pmc_core: Clean up: Remove comma after the termination line

[Gayatri Kammela]

It is common practice to place a comma after the last entry in an
initialized array to avoid the need to add one in future patches that
extend the array. But when the last element is a termination marker, the
comma could be harmful. Any new entries must be added before the
terminator (and the comma would prevent the compiler from issuing a
warning about an entry after the terminator).

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: David E. Box <david.e.box@intel.com>
Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 94a008efb09b..6ad829915689 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -49,7 +49,7 @@ static const struct pmc_bit_map spt_pll_map[] = {
 	{"GEN2 USB2PCIE2 PLL",		SPT_PMC_BIT_MPHY_CMN_LANE1},
 	{"DMIPCIE3 PLL",		SPT_PMC_BIT_MPHY_CMN_LANE2},
 	{"SATA PLL",			SPT_PMC_BIT_MPHY_CMN_LANE3},
-	{},
+	{}
 };
 
 static const struct pmc_bit_map spt_mphy_map[] = {
@@ -69,7 +69,7 @@ static const struct pmc_bit_map spt_mphy_map[] = {
 	{"MPHY CORE LANE 13",          SPT_PMC_BIT_MPHY_LANE13},
 	{"MPHY CORE LANE 14",          SPT_PMC_BIT_MPHY_LANE14},
 	{"MPHY CORE LANE 15",          SPT_PMC_BIT_MPHY_LANE15},
-	{},
+	{}
 };
 
 static const struct pmc_bit_map spt_pfear_map[] = {
@@ -113,7 +113,7 @@ static const struct pmc_bit_map spt_pfear_map[] = {
 	{"CSME_SMS1",			SPT_PMC_BIT_CSME_SMS1},
 	{"CSME_RTC",			SPT_PMC_BIT_CSME_RTC},
 	{"CSME_PSF",			SPT_PMC_BIT_CSME_PSF},
-	{},
+	{}
 };
 
 static const struct pmc_bit_map spt_ltr_show_map[] = {
@@ -299,7 +299,7 @@ static const struct pmc_bit_map *cnp_slps0_dbg_maps[] = {
 	cnp_slps0_dbg0_map,
 	cnp_slps0_dbg1_map,
 	cnp_slps0_dbg2_map,
-	NULL,
+	NULL
 };
 
 static const struct pmc_bit_map cnp_ltr_show_map[] = {
@@ -820,7 +820,7 @@ MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
 
 static const struct pci_device_id pmc_pci_ids[] = {
 	{ PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), 0},
-	{ 0, },
+	{ 0, }
 };
 
 /*
-- 
2.17.1

[PATCH v1 2/5] x86/intel_pmc_core: Create platform dependent pmc bitmap structs

[Gayatri Kammela]

The current implementation of pmc_core driver allows to reuse, but does
not reflect the exact number and names of IPs for a newer platform which
does not necessarily support all the IPs in the entries. The names and
number of these IPs might differ from its previous platforms. The number
of PCH IPs per platform is calculated based on PPFEAR_NUM_ENTRIES
defined, where each entry represents a bucket (8 bits). The platform can
support 'n' entries, but not necessarily all 'n*8' IPs.

Create platform dependent bitmap structures to specify the exact number,
names of IPs while reusing the existing IPs.

The changes in this patch are preparatory to accommodate future SoCs
that might reuse the CNL/ICL PCH IPs, and to reflect the exact number of
IPs with its names.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: David E. Box <david.e.box@intel.com>
Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 46 ++++++++++++++++++++-------
 drivers/platform/x86/intel_pmc_core.h |  2 +-
 2 files changed, 35 insertions(+), 13 deletions(-)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index 6ad829915689..c6a0c29d3476 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -116,6 +116,11 @@ static const struct pmc_bit_map spt_pfear_map[] = {
 	{}
 };
 
+static const struct pmc_bit_map *ext_spt_pfear_map[] = {
+	spt_pfear_map,
+	NULL
+};
+
 static const struct pmc_bit_map spt_ltr_show_map[] = {
 	{"SOUTHPORT_A",		SPT_PMC_LTR_SPA},
 	{"SOUTHPORT_B",		SPT_PMC_LTR_SPB},
@@ -142,7 +147,7 @@ static const struct pmc_bit_map spt_ltr_show_map[] = {
 };
 
 static const struct pmc_reg_map spt_reg_map = {
-	.pfear_sts = spt_pfear_map,
+	.pfear_sts = ext_spt_pfear_map,
 	.mphy_sts = spt_mphy_map,
 	.pll_sts = spt_pll_map,
 	.ltr_show_sts = spt_ltr_show_map,
@@ -233,7 +238,15 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
 	{"PSF6",		BIT(5)},
 	{"PSF7",		BIT(6)},
 	{"PSF8",		BIT(7)},
+	{}
+};
+
+static const struct pmc_bit_map *ext_cnp_pfear_map[] = {
+	cnp_pfear_map,
+	NULL
+};
 
+static const struct pmc_bit_map icl_pfear_map[] = {
 	/* Icelake generation onwards only */
 	{"RES_65",		BIT(0)},
 	{"RES_66",		BIT(1)},
@@ -246,6 +259,12 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
 	{}
 };
 
+static const struct pmc_bit_map *ext_icl_pfear_map[] = {
+	cnp_pfear_map,
+	icl_pfear_map,
+	NULL
+};
+
 static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
 	{"AUDIO_D3",		BIT(0)},
 	{"OTG_D3",		BIT(1)},
@@ -333,7 +352,7 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = {
 };
 
 static const struct pmc_reg_map cnp_reg_map = {
-	.pfear_sts = cnp_pfear_map,
+	.pfear_sts = ext_cnp_pfear_map,
 	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 	.slps0_dbg_maps = cnp_slps0_dbg_maps,
 	.ltr_show_sts = cnp_ltr_show_map,
@@ -349,7 +368,7 @@ static const struct pmc_reg_map cnp_reg_map = {
 };
 
 static const struct pmc_reg_map icl_reg_map = {
-	.pfear_sts = cnp_pfear_map,
+	.pfear_sts = ext_icl_pfear_map,
 	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
 	.slps0_dbg_maps = cnp_slps0_dbg_maps,
 	.ltr_show_sts = cnp_ltr_show_map,
@@ -411,20 +430,20 @@ static int pmc_core_check_read_lock_bit(void)
 #if IS_ENABLED(CONFIG_DEBUG_FS)
 static bool slps0_dbg_latch;
 
-static void pmc_core_display_map(struct seq_file *s, int index,
-				 u8 pf_reg, const struct pmc_bit_map *pf_map)
+static void pmc_core_display_map(struct seq_file *s, int index, int idx, int ip,
+				 u8 pf_reg, const struct pmc_bit_map **pf_map)
 {
 	seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
-		   index, pf_map[index].name,
-		   pf_map[index].bit_mask & pf_reg ? "Off" : "On");
+		   ip, pf_map[idx][index].name,
+		   pf_map[idx][index].bit_mask & pf_reg ? "Off" : "On");
 }
 
 static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
 {
 	struct pmc_dev *pmcdev = s->private;
-	const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
+	const struct pmc_bit_map **maps = pmcdev->map->pfear_sts;
 	u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
-	int index, iter;
+	int index, iter, idx, ip = 0;
 
 	iter = pmcdev->map->ppfear0_offset;
 
@@ -432,9 +451,12 @@ static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
 	     index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
 		pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
 
-	for (index = 0; map[index].name &&
-	     index < pmcdev->map->ppfear_buckets * 8; index++)
-		pmc_core_display_map(s, index, pf_regs[index / 8], map);
+	for (idx = 0; maps[idx]; idx++) {
+		for (index = 0; maps[idx][index].name &&
+		     index < pmcdev->map->ppfear_buckets * 8; ip++, index++)
+			pmc_core_display_map(s, index, idx, ip,
+					     pf_regs[index / 8], maps);
+	}
 
 	return 0;
 }
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel_pmc_core.h
index fdee5772e532..4b9f9ad6b692 100644
--- a/drivers/platform/x86/intel_pmc_core.h
+++ b/drivers/platform/x86/intel_pmc_core.h
@@ -213,7 +213,7 @@ struct pmc_bit_map {
  * captures them to have a common implementation.
  */
 struct pmc_reg_map {
-	const struct pmc_bit_map *pfear_sts;
+	const struct pmc_bit_map **pfear_sts;
 	const struct pmc_bit_map *mphy_sts;
 	const struct pmc_bit_map *pll_sts;
 	const struct pmc_bit_map **slps0_dbg_maps;
-- 
2.17.1

[PATCH v1 3/5] x86/intel_pmc_core: Make debugfs entry for pch_ip_power_gating_status conditional

[Gayatri Kammela]

Check if the platform supports and only then add a debugfs entry for PCH
IP power gating status.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: David E. Box <david.e.box@intel.com>
Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index c6a0c29d3476..ea43a5989c96 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -788,8 +788,9 @@ static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 	debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
 			    &pmc_core_dev_state);
 
-	debugfs_create_file("pch_ip_power_gating_status", 0444, dir, pmcdev,
-			    &pmc_core_ppfear_fops);
+	if (pmcdev->map->pfear_sts)
+		debugfs_create_file("pch_ip_power_gating_status", 0444, dir,
+				    pmcdev, &pmc_core_ppfear_fops);
 
 	debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
 			    &pmc_core_ltr_ignore_ops);
-- 
2.17.1

[PATCH v1 4/5] platform/x86: Add Tiger Lake(TGL) platform support to intel_pmc_core driver

[Gayatri Kammela]

Add Tiger Lake to the list of the platforms that intel_pmc_core driver
supports for the pmc_core device.

Just like ICL, TGL can also reuse all the CNL PCH IPs. Since TGL has
almost the same number of PCH IPs as ICL, reuse ICL's PPFEAR_NUM_ENTRIES
instead of defining a new macro.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: David E. Box <david.e.box@intel.com>
Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 40 +++++++++++++++++++++++++--
 1 file changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index ea43a5989c96..aef8f6d8bddb 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -190,7 +190,7 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
 	{"SDX",                 BIT(4)},
 	{"SPE",                 BIT(5)},
 	{"Fuse",                BIT(6)},
-	/* Reserved for Cannonlake but valid for Icelake */
+	/* Reserved for Cannonlake but valid for Icelake and Tigerlake */
 	{"SBR8",		BIT(7)},
 
 	{"CSME_FSC",            BIT(0)},
@@ -234,7 +234,7 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
 	{"HDA_PGD4",            BIT(2)},
 	{"HDA_PGD5",            BIT(3)},
 	{"HDA_PGD6",            BIT(4)},
-	/* Reserved for Cannonlake but valid for Icelake */
+	/* Reserved for Cannonlake but valid for Icelake and Tigerlake */
 	{"PSF6",		BIT(5)},
 	{"PSF7",		BIT(6)},
 	{"PSF8",		BIT(7)},
@@ -265,6 +265,24 @@ static const struct pmc_bit_map *ext_icl_pfear_map[] = {
 	NULL
 };
 
+static const struct pmc_bit_map tgl_pfear_map[] = {
+	/* Tigerlake generation onwards only */
+	{"PSF9",		BIT(0)},
+	{"RES_66",		BIT(1)},
+	{"RES_67",		BIT(2)},
+	{"RES_68",		BIT(3)},
+	{"RES_69",		BIT(4)},
+	{"RES_70",		BIT(5)},
+	{"TBTLSX",		BIT(6)},
+	{}
+};
+
+static const struct pmc_bit_map *ext_tgl_pfear_map[] = {
+	cnp_pfear_map,
+	tgl_pfear_map,
+	NULL
+};
+
 static const struct pmc_bit_map cnp_slps0_dbg0_map[] = {
 	{"AUDIO_D3",		BIT(0)},
 	{"OTG_D3",		BIT(1)},
@@ -383,6 +401,22 @@ static const struct pmc_reg_map icl_reg_map = {
 	.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
 };
 
+static const struct pmc_reg_map tgl_reg_map = {
+	.pfear_sts = ext_tgl_pfear_map,
+	.slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
+	.slps0_dbg_maps = cnp_slps0_dbg_maps,
+	.ltr_show_sts = cnp_ltr_show_map,
+	.msr_sts = msr_map,
+	.slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
+	.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
+	.regmap_length = CNP_PMC_MMIO_REG_LEN,
+	.ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
+	.ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
+	.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
+	.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+	.ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
+};
+
 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
 {
 	return readb(pmcdev->regbase + offset);
@@ -836,6 +870,8 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
 	INTEL_CPU_FAM6(CANNONLAKE_L, cnp_reg_map),
 	INTEL_CPU_FAM6(ICELAKE_L, icl_reg_map),
 	INTEL_CPU_FAM6(ICELAKE_NNPI, icl_reg_map),
+	INTEL_CPU_FAM6(TIGERLAKE_L, tgl_reg_map),
+	INTEL_CPU_FAM6(TIGERLAKE, tgl_reg_map),
 	{}
 };
 
-- 
2.17.1

[PATCH v1 5/5] platform/x86: Add Atom based Elkhart Lake(EHL) platform support to intel_pmc_core driver

[Gayatri Kammela]

Add Elkhart Lake to the list of the platforms that intel_pmc_core
driver supports for pmc_core device.

Just like ICL and TGL, EHL can also reuse all the CNL PCH IPs. Also, it
uses the same PCH IPs of TGL, no additional effort is needed to enable
but to simply reuse them.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: David E. Box <david.e.box@intel.com>
Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
 drivers/platform/x86/intel_pmc_core.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
index aef8f6d8bddb..2047b54fad54 100644
--- a/drivers/platform/x86/intel_pmc_core.c
+++ b/drivers/platform/x86/intel_pmc_core.c
@@ -190,7 +190,10 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
 	{"SDX",                 BIT(4)},
 	{"SPE",                 BIT(5)},
 	{"Fuse",                BIT(6)},
-	/* Reserved for Cannonlake but valid for Icelake and Tigerlake */
+	/*
+	 * Reserved for Cannonlake but valid for Icelake,
+	 * Tigerlake and Elkhart lake.
+	 */
 	{"SBR8",		BIT(7)},
 
 	{"CSME_FSC",            BIT(0)},
@@ -234,7 +237,10 @@ static const struct pmc_bit_map cnp_pfear_map[] = {
 	{"HDA_PGD4",            BIT(2)},
 	{"HDA_PGD5",            BIT(3)},
 	{"HDA_PGD6",            BIT(4)},
-	/* Reserved for Cannonlake but valid for Icelake and Tigerlake */
+	/*
+	 * Reserved for Cannonlake but valid for Icelake,
+	 * Tigerlake and Elkhart lake.
+	 */
 	{"PSF6",		BIT(5)},
 	{"PSF7",		BIT(6)},
 	{"PSF8",		BIT(7)},
@@ -266,7 +272,7 @@ static const struct pmc_bit_map *ext_icl_pfear_map[] = {
 };
 
 static const struct pmc_bit_map tgl_pfear_map[] = {
-	/* Tigerlake generation onwards only */
+	/* Tigerlake and Elkhart lake generation onwards only */
 	{"PSF9",		BIT(0)},
 	{"RES_66",		BIT(1)},
 	{"RES_67",		BIT(2)},
@@ -872,6 +878,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
 	INTEL_CPU_FAM6(ICELAKE_NNPI, icl_reg_map),
 	INTEL_CPU_FAM6(TIGERLAKE_L, tgl_reg_map),
 	INTEL_CPU_FAM6(TIGERLAKE, tgl_reg_map),
+	INTEL_CPU_FAM6(ATOM_TREMONT, tgl_reg_map),
 	{}
 };
 
-- 
2.17.1

Re: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

[Andy Shevchenko]

On Thu, Sep 26, 2019 at 9:43 PM Gayatri Kammela
<gayatri.kammela@intel.com> wrote:

Thank you for the series, I'll comment them later.

For now, check how to properly setup prefix for all patches. The Title
all broken.

> Patch 1: Cleans up termination lines
> Patch 2: Refactor driver for ease of adding new SoCs
> Patch 3: Refactor debugfs entry for PCH IPs power gating status
> Patch 4: Add Tiger Lake legacy support to pmc_core
> Patch 5: Add Elkhart Lake legacy support to pmc_core
>
> All the information regarding the PCH IPs and names of IPs will be available
> in *future* Intel's Platform Controller Hub (PCH) External Design Specification
> (EDS) document.

When?

> Gayatri Kammela (5):
>   x86/intel_pmc_core: Clean up: Remove comma after the termination line
>   x86/intel_pmc_core: Create platform dependent pmc bitmap structs
>   x86/intel_pmc_core: Make debugfs entry for pch_ip_power_gating_status
>     conditional
>   platform/x86: Add Tiger Lake(TGL) platform support to intel_pmc_core
>     driver
>   platform/x86: Add Atom based Elkhart Lake(EHL) platform support to
>     intel_pmc_core driver
>
>  drivers/platform/x86/intel_pmc_core.c | 108 +++++++++++++++++++++-----
>  drivers/platform/x86/intel_pmc_core.h |   2 +-
>  2 files changed, 88 insertions(+), 22 deletions(-)
>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Kan Liang <kan.liang@intel.com>
> Cc: David E. Box <david.e.box@intel.com>
> Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
> Cc: Tony Luck <tony.luck@intel.com>
> Reviewed-by: Tony Luck <tony.luck@intel.com>
> --
> 2.17.1
>


-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

[Andy Shevchenko]

On Fri, Sep 27, 2019 at 9:01 AM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
> On Thu, Sep 26, 2019 at 9:43 PM Gayatri Kammela
> <gayatri.kammela@intel.com> wrote:
>
> Thank you for the series, I'll comment them later.
>
> For now, check how to properly setup prefix for all patches. The Title
> all broken.
>

On top of that the fully inconsistent SoC naming through the existing
code / new additions.

I'm pretty sure you need to spell platforms as Tiger Lake, Elkhart
Lake and so on everywhere.

Fix this, but do not send new version till I look at the code here.

> > Patch 1: Cleans up termination lines
> > Patch 2: Refactor driver for ease of adding new SoCs
> > Patch 3: Refactor debugfs entry for PCH IPs power gating status
> > Patch 4: Add Tiger Lake legacy support to pmc_core
> > Patch 5: Add Elkhart Lake legacy support to pmc_core
> >
> > All the information regarding the PCH IPs and names of IPs will be available
> > in *future* Intel's Platform Controller Hub (PCH) External Design Specification
> > (EDS) document.
>
> When?

-- 
With Best Regards,
Andy Shevchenko

RE: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

[Kammela, Gayatri]

> On Thu, Sep 26, 2019 at 9:43 PM Gayatri Kammela
> <gayatri.kammela@intel.com> wrote:
> 
> Thank you for the series, I'll comment them later.
Thank you Andy!
> 
> For now, check how to properly setup prefix for all patches. The Title all
> broken.
I'm sorry about that. I will fix it in v2
> 
> > Patch 1: Cleans up termination lines
> > Patch 2: Refactor driver for ease of adding new SoCs Patch 3: Refactor
> > debugfs entry for PCH IPs power gating status Patch 4: Add Tiger Lake
> > legacy support to pmc_core Patch 5: Add Elkhart Lake legacy support to
> > pmc_core
> >
> > All the information regarding the PCH IPs and names of IPs will be
> > available in *future* Intel's Platform Controller Hub (PCH) External
> > Design Specification
> > (EDS) document.
> 
> When?
I was told it will be available in the upcoming release of EDS document. I am not aware of the timeline. I will update the timeline in v2.

RE: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

[Kammela, Gayatri]

> On top of that the fully inconsistent SoC naming through the existing code /
> new additions.
I will fix it in the existing code/new additions in v2.
> 
> I'm pretty sure you need to spell platforms as Tiger Lake, Elkhart Lake and so
> on everywhere.
Sorry, I was careful about naming convention in the commit message but not in the comments ☹. I will fix it in v2.
> 
> Fix this, but do not send new version till I look at the code here.
Sure Andy! I will wait. Thanks!
> 

RE: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

[Kammela, Gayatri]

> -----Original Message-----
> From: Kammela, Gayatri
> Sent: Monday, September 30, 2019 11:24 AM
> To: Andy Shevchenko <andy.shevchenko@gmail.com>
> Cc: Platform Driver <platform-driver-x86@vger.kernel.org>; Somayaji,
> Vishwanath <vishwanath.somayaji@intel.com>; Darren Hart
> <dvhart@infradead.org>; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>; Prestopine, Charles D
> <charles.d.prestopine@intel.com>; Peter Zijlstra <peterz@infradead.org>;
> Pandruvada, Srinivas <srinivas.pandruvada@intel.com>; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; Liang, Kan <kan.liang@intel.com>;
> Box, David E <david.e.box@intel.com>; Bhardwaj, Rajneesh
> <rajneesh.bhardwaj@intel.com>; Luck, Tony <tony.luck@intel.com>
> Subject: RE: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core
> driver
> 
> > On Thu, Sep 26, 2019 at 9:43 PM Gayatri Kammela
> > <gayatri.kammela@intel.com> wrote:
> >
> > Thank you for the series, I'll comment them later.
> Thank you Andy!
> >

Hi Andy! I'm wondering if you have any comments for this patch series. Thanks!

Re: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

[Andy Shevchenko]

On Mon, Oct 28, 2019 at 6:41 PM Kammela, Gayatri
<gayatri.kammela@intel.com> wrote:
>
> > -----Original Message-----
> > From: Kammela, Gayatri
> > Sent: Monday, September 30, 2019 11:24 AM
> > To: Andy Shevchenko <andy.shevchenko@gmail.com>
> > Cc: Platform Driver <platform-driver-x86@vger.kernel.org>; Somayaji,
> > Vishwanath <vishwanath.somayaji@intel.com>; Darren Hart
> > <dvhart@infradead.org>; Linux Kernel Mailing List <linux-
> > kernel@vger.kernel.org>; Prestopine, Charles D
> > <charles.d.prestopine@intel.com>; Peter Zijlstra <peterz@infradead.org>;
> > Pandruvada, Srinivas <srinivas.pandruvada@intel.com>; Andy Shevchenko
> > <andriy.shevchenko@linux.intel.com>; Liang, Kan <kan.liang@intel.com>;
> > Box, David E <david.e.box@intel.com>; Bhardwaj, Rajneesh
> > <rajneesh.bhardwaj@intel.com>; Luck, Tony <tony.luck@intel.com>
> > Subject: RE: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core
> > driver
> >
> > > On Thu, Sep 26, 2019 at 9:43 PM Gayatri Kammela
> > > <gayatri.kammela@intel.com> wrote:
> > >
> > > Thank you for the series, I'll comment them later.
> > Thank you Andy!
> > >
>
> Hi Andy! I'm wondering if you have any comments for this patch series. Thanks!

Please, address above mentioned comments and send a v2. I'll push it
to review branch.

-- 
With Best Regards,
Andy Shevchenko

RE: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to pmc_core driver

[Kammela, Gayatri]

> > > Subject: RE: [PATCH v1 0/5] Add Tiger Lake/Elkhart Lake support to
> > > pmc_core driver
> > >
> > > > On Thu, Sep 26, 2019 at 9:43 PM Gayatri Kammela
> > > > <gayatri.kammela@intel.com> wrote:
> > > >
> > > > Thank you for the series, I'll comment them later.
> > > Thank you Andy!
> > > >
> >
> > Hi Andy! I'm wondering if you have any comments for this patch series.
> Thanks!
> 
> Please, address above mentioned comments and send a v2. I'll push it to
> review branch.

Thank you Andy! Sorry for the delay. I sent v2 of the series. Thanks!