* [PATCH V4] perf vendor events riscv: add T-HEAD C9xx JSON file
@ 2023-08-26 8:44 Inochi Amaoto
2023-08-27 11:01 ` Guo Ren
0 siblings, 1 reply; 2+ messages in thread
From: Inochi Amaoto @ 2023-08-26 8:44 UTC (permalink / raw)
To: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Ian Rogers, Adrian Hunter, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Nikita Shubin, Wei Fu, Guo Ren, Inochi Amaoto
Cc: linux-kernel, linux-perf-users, linux-riscv
Add json file of T-HEAD C9xx series events.
The event idx (raw value) is summary as following:
event id range | support cpu
0x01 - 0x2a | c906,c910,c920
The event ids are based on the public document of T-HEAD and cover
the c900 series.
These events are the max that c900 series support.
Since T-HEAD let manufacturers decide whether events are usable,
the final support of the perf events is determined by the pmu node
of the soc dtb.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
---
Change from V3:
1. fix some typo in json file
2. correct the event id range in commit
3. rename directory to c900-legacy to identify the old T-HEAD cpus
This patch need the following patches for opensbi to function normaly:
https://lists.infradead.org/pipermail/opensbi/2023-August/005500.html
The dtb patch:
https://lists.infradead.org/pipermail/linux-riscv/2023-August/039040.html
A test result on D1 board with mainline opensbi and mainline kernel:
[root@test perf]# ./perf stat -a \
> -e l1_icache_access \
> -e l1_icache_miss \
> -e itlb_miss \
> -e dtlb_miss \
> -e jtlb_miss \
> -e inst_branch_mispredict \
> -e inst_branch \
> -e inst_store \
> -e l1_dcache_read_access \
> -e l1_dcache_read_miss \
> -e l1_dcache_write_access \
> -e l1_dcache_write_miss \
> -- openssl speed rsa2048
Doing 2048 bits private rsa's for 10s: 100 2048 bits private RSA's in 10.06s
Doing 2048 bits public rsa's for 10s: 4051 2048 bits public RSA's in 10.00s
version: 3.1.2
built on: Sat Aug 5 14:56:47 2023 UTC
options: bn(64,64)
CPUINFO: N/A
sign verify sign/s verify/s
rsa 2048 bits 0.100600s 0.002469s 9.9 405.1
Performance counter stats for 'system wide':
7,120,831,110 l1_icache_access
2,145,279 l1_icache_miss
1,307,935 itlb_miss
2,477,482 dtlb_miss
402,760 jtlb_miss
8,043,723 inst_branch_mispredict
153,469,454 inst_branch
537,300,381 inst_store
947,508,099 l1_dcache_read_access
770,550 l1_dcache_read_miss
537,262,702 l1_dcache_write_access
171,436 l1_dcache_write_miss
20.315046885 seconds time elapsed
---
tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
.../arch/riscv/thead/c900-legacy/cache.json | 67 ++++++++++++++++
.../riscv/thead/c900-legacy/firmware.json | 68 ++++++++++++++++
.../riscv/thead/c900-legacy/instruction.json | 72 +++++++++++++++++
.../riscv/thead/c900-legacy/microarch.json | 80 +++++++++++++++++++
5 files changed, 288 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json
create mode 100644 tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json
create mode 100644 tools/perf/pmu-events/arch/riscv/thead/c900-legacy/instruction.json
create mode 100644 tools/perf/pmu-events/arch/riscv/thead/c900-legacy/microarch.json
diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index c61b3d6ef616..b42b65d09c36 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -15,3 +15,4 @@
#
#MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
+0x5b7-0x0-0x0,v1,thead/c900-legacy,core
diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json
new file mode 100644
index 000000000000..2b142348d635
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json
@@ -0,0 +1,67 @@
+[
+ {
+ "EventName": "L1_ICACHE_ACCESS",
+ "EventCode": "0x00000001",
+ "BriefDescription": "L1 instruction cache access"
+ },
+ {
+ "EventName": "L1_ICACHE_MISS",
+ "EventCode": "0x00000002",
+ "BriefDescription": "L1 instruction cache miss"
+ },
+ {
+ "EventName": "ITLB_MISS",
+ "EventCode": "0x00000003",
+ "BriefDescription": "I-UTLB miss"
+ },
+ {
+ "EventName": "DTLB_MISS",
+ "EventCode": "0x00000004",
+ "BriefDescription": "D-UTLB miss"
+ },
+ {
+ "EventName": "JTLB_MISS",
+ "EventCode": "0x00000005",
+ "BriefDescription": "JTLB miss"
+ },
+ {
+ "EventName": "L1_DCACHE_READ_ACCESS",
+ "EventCode": "0x0000000c",
+ "BriefDescription": "L1 data cache read access"
+ },
+ {
+ "EventName": "L1_DCACHE_READ_MISS",
+ "EventCode": "0x0000000d",
+ "BriefDescription": "L1 data cache read miss"
+ },
+ {
+ "EventName": "L1_DCACHE_WRITE_ACCESS",
+ "EventCode": "0x0000000e",
+ "BriefDescription": "L1 data cache write access"
+ },
+ {
+ "EventName": "L1_DCACHE_WRITE_MISS",
+ "EventCode": "0x0000000f",
+ "BriefDescription": "L1 data cache write miss"
+ },
+ {
+ "EventName": "LL_CACHE_READ_ACCESS",
+ "EventCode": "0x00000010",
+ "BriefDescription": "LL Cache read access"
+ },
+ {
+ "EventName": "LL_CACHE_READ_MISS",
+ "EventCode": "0x00000011",
+ "BriefDescription": "LL Cache read miss"
+ },
+ {
+ "EventName": "LL_CACHE_WRITE_ACCESS",
+ "EventCode": "0x00000012",
+ "BriefDescription": "LL Cache write access"
+ },
+ {
+ "EventName": "LL_CACHE_WRITE_MISS",
+ "EventCode": "0x00000013",
+ "BriefDescription": "LL Cache write miss"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json
new file mode 100644
index 000000000000..9b4a032186a7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json
@@ -0,0 +1,68 @@
+[
+ {
+ "ArchStdEvent": "FW_MISALIGNED_LOAD"
+ },
+ {
+ "ArchStdEvent": "FW_MISALIGNED_STORE"
+ },
+ {
+ "ArchStdEvent": "FW_ACCESS_LOAD"
+ },
+ {
+ "ArchStdEvent": "FW_ACCESS_STORE"
+ },
+ {
+ "ArchStdEvent": "FW_ILLEGAL_INSN"
+ },
+ {
+ "ArchStdEvent": "FW_SET_TIMER"
+ },
+ {
+ "ArchStdEvent": "FW_IPI_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_IPI_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_FENCE_I_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_FENCE_I_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
+ },
+ {
+ "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/instruction.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/instruction.json
new file mode 100644
index 000000000000..c822b5373333
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/instruction.json
@@ -0,0 +1,72 @@
+[
+ {
+ "EventName": "INST_BRANCH_MISPREDICT",
+ "EventCode": "0x00000006",
+ "BriefDescription": "Mispredicted branch instructions"
+ },
+ {
+ "EventName": "INST_BRANCH",
+ "EventCode": "0x00000007",
+ "BriefDescription": "Retired branch instructions"
+ },
+ {
+ "EventName": "INST_JMP_MISPREDICT",
+ "EventCode": "0x00000008",
+ "BriefDescription": "Indirect branch mispredict"
+ },
+ {
+ "EventName": "INST_JMP",
+ "EventCode": "0x00000009",
+ "BriefDescription": "Retired jmp instructions"
+ },
+ {
+ "EventName": "INST_STORE",
+ "EventCode": "0x0000000b",
+ "BriefDescription": "Retired store instructions"
+ },
+ {
+ "EventName": "INST_ALU",
+ "EventCode": "0x0000001d",
+ "BriefDescription": "Retired ALU instructions"
+ },
+ {
+ "EventName": "INST_LDST",
+ "EventCode": "0x0000001e",
+ "BriefDescription": "Retired Load/Store instructions"
+ },
+ {
+ "EventName": "INST_VECTOR",
+ "EventCode": "0x0000001f",
+ "BriefDescription": "Retired Vector instructions"
+ },
+ {
+ "EventName": "INST_CSR",
+ "EventCode": "0x00000020",
+ "BriefDescription": "Retired CSR instructions"
+ },
+ {
+ "EventName": "INST_SYNC",
+ "EventCode": "0x00000021",
+ "BriefDescription": "Retired sync instructions (AMO/LR/SC instructions)"
+ },
+ {
+ "EventName": "INST_UNALIGNED_ACCESS",
+ "EventCode": "0x00000022",
+ "BriefDescription": "Retired Store/Load instructions with unaligned memory access"
+ },
+ {
+ "EventName": "INST_ECALL",
+ "EventCode": "0x00000025",
+ "BriefDescription": "Retired ecall instructions"
+ },
+ {
+ "EventName": "INST_LONG_JP",
+ "EventCode": "0x00000026",
+ "BriefDescription": "Retired long jump instructions"
+ },
+ {
+ "EventName": "INST_FP",
+ "EventCode": "0x0000002a",
+ "BriefDescription": "Retired FPU instructions"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/microarch.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/microarch.json
new file mode 100644
index 000000000000..0ab6f288af91
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/microarch.json
@@ -0,0 +1,80 @@
+[
+ {
+ "EventName": "LSU_SPEC_FAIL",
+ "EventCode": "0x0000000a",
+ "BriefDescription": "LSU speculation fail"
+ },
+ {
+ "EventName": "IDU_RF_PIPE_FAIL",
+ "EventCode": "0x00000014",
+ "BriefDescription": "Instruction decode unit launch pipeline failed in RF state"
+ },
+ {
+ "EventName": "IDU_RF_REG_FAIL",
+ "EventCode": "0x00000015",
+ "BriefDescription": "Instruction decode unit launch register file fail in RF state"
+ },
+ {
+ "EventName": "IDU_RF_INSTRUCTION",
+ "EventCode": "0x00000016",
+ "BriefDescription": "retired instruction count of Instruction decode unit in RF (Register File) stage"
+ },
+ {
+ "EventName": "LSU_4K_STALL",
+ "EventCode": "0x00000017",
+ "BriefDescription": "LSU stall times for long distance data access (Over 4K)",
+ "PublicDescription": "This stall occurs when translate virtual address with page offset over 4k"
+ },
+ {
+ "EventName": "LSU_OTHER_STALL",
+ "EventCode": "0x00000018",
+ "BriefDescription": "LSU stall times for other reasons (except the 4k stall)"
+ },
+ {
+ "EventName": "LSU_SQ_OTHER_DIS",
+ "EventCode": "0x00000019",
+ "BriefDescription": "LSU store queue discard others"
+ },
+ {
+ "EventName": "LSU_SQ_DATA_DISCARD",
+ "EventCode": "0x0000001a",
+ "BriefDescription": "LSU store queue discard data (uops)"
+ },
+ {
+ "EventName": "BRANCH_DIRECTION_MISPREDICTION",
+ "EventCode": "0x0000001b",
+ "BriefDescription": "Branch misprediction in BTB"
+ },
+ {
+ "EventName": "BRANCH_DIRECTION_PREDICTION",
+ "EventCode": "0x0000001c",
+ "BriefDescription": "All branch prediction in BTB",
+ "PublicDescription": "This event including both successful prediction and failed prediction in BTB"
+ },
+ {
+ "EventName": "INTERRUPT_ACK_COUNT",
+ "EventCode": "0x00000023",
+ "BriefDescription": "acknowledged interrupt count"
+ },
+ {
+ "EventName": "INTERRUPT_OFF_CYCLE",
+ "EventCode": "0x00000024",
+ "BriefDescription": "PLIC arbitration time when the interrupt is not responded",
+ "PublicDescription": "The arbitration time is recorded while meeting any of the following:\n- CPU is M-mode and MIE == 0\n- CPU is S-mode and delegation and SIE == 0\n"
+ },
+ {
+ "EventName": "IFU_STALLED_CYCLE",
+ "EventCode": "0x00000027",
+ "BriefDescription": "Number of stall cycles of the instruction fetch unit (IFU)."
+ },
+ {
+ "EventName": "IDU_STALLED_CYCLE",
+ "EventCode": "0x00000028",
+ "BriefDescription": "hpcp_backend_stall Number of stall cycles of the instruction decoding unit (IDU) and next-level pipeline unit."
+ },
+ {
+ "EventName": "SYNC_STALL",
+ "EventCode": "0x00000029",
+ "BriefDescription": "Sync instruction stall cycle fence/fence.i/sync/sfence"
+ }
+]
--
2.41.0
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH V4] perf vendor events riscv: add T-HEAD C9xx JSON file
2023-08-26 8:44 [PATCH V4] perf vendor events riscv: add T-HEAD C9xx JSON file Inochi Amaoto
@ 2023-08-27 11:01 ` Guo Ren
0 siblings, 0 replies; 2+ messages in thread
From: Guo Ren @ 2023-08-27 11:01 UTC (permalink / raw)
To: Inochi Amaoto
Cc: Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo,
Mark Rutland, Alexander Shishkin, Jiri Olsa, Namhyung Kim,
Ian Rogers, Adrian Hunter, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Nikita Shubin, Wei Fu, linux-kernel, linux-perf-users,
linux-riscv
Thx for the patch.
Tested-by: Guo Ren <guoren@kernel.org>
On Sat, Aug 26, 2023 at 4:44 AM Inochi Amaoto <inochiama@outlook.com> wrote:
>
> Add json file of T-HEAD C9xx series events.
>
> The event idx (raw value) is summary as following:
>
> event id range | support cpu
> 0x01 - 0x2a | c906,c910,c920
>
> The event ids are based on the public document of T-HEAD and cover
> the c900 series.
>
> These events are the max that c900 series support.
> Since T-HEAD let manufacturers decide whether events are usable,
> the final support of the perf events is determined by the pmu node
> of the soc dtb.
>
> Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
> ---
> Change from V3:
> 1. fix some typo in json file
> 2. correct the event id range in commit
> 3. rename directory to c900-legacy to identify the old T-HEAD cpus
>
> This patch need the following patches for opensbi to function normaly:
> https://lists.infradead.org/pipermail/opensbi/2023-August/005500.html
>
> The dtb patch:
> https://lists.infradead.org/pipermail/linux-riscv/2023-August/039040.html
>
> A test result on D1 board with mainline opensbi and mainline kernel:
> [root@test perf]# ./perf stat -a \
> > -e l1_icache_access \
> > -e l1_icache_miss \
> > -e itlb_miss \
> > -e dtlb_miss \
> > -e jtlb_miss \
> > -e inst_branch_mispredict \
> > -e inst_branch \
> > -e inst_store \
> > -e l1_dcache_read_access \
> > -e l1_dcache_read_miss \
> > -e l1_dcache_write_access \
> > -e l1_dcache_write_miss \
> > -- openssl speed rsa2048
> Doing 2048 bits private rsa's for 10s: 100 2048 bits private RSA's in 10.06s
> Doing 2048 bits public rsa's for 10s: 4051 2048 bits public RSA's in 10.00s
> version: 3.1.2
> built on: Sat Aug 5 14:56:47 2023 UTC
> options: bn(64,64)
> CPUINFO: N/A
> sign verify sign/s verify/s
> rsa 2048 bits 0.100600s 0.002469s 9.9 405.1
>
> Performance counter stats for 'system wide':
>
> 7,120,831,110 l1_icache_access
> 2,145,279 l1_icache_miss
> 1,307,935 itlb_miss
> 2,477,482 dtlb_miss
> 402,760 jtlb_miss
> 8,043,723 inst_branch_mispredict
> 153,469,454 inst_branch
> 537,300,381 inst_store
> 947,508,099 l1_dcache_read_access
> 770,550 l1_dcache_read_miss
> 537,262,702 l1_dcache_write_access
> 171,436 l1_dcache_write_miss
>
> 20.315046885 seconds time elapsed
>
> ---
> tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 +
> .../arch/riscv/thead/c900-legacy/cache.json | 67 ++++++++++++++++
> .../riscv/thead/c900-legacy/firmware.json | 68 ++++++++++++++++
> .../riscv/thead/c900-legacy/instruction.json | 72 +++++++++++++++++
> .../riscv/thead/c900-legacy/microarch.json | 80 +++++++++++++++++++
> 5 files changed, 288 insertions(+)
> create mode 100644 tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/thead/c900-legacy/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/thead/c900-legacy/microarch.json
>
> diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> index c61b3d6ef616..b42b65d09c36 100644
> --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> @@ -15,3 +15,4 @@
> #
> #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType
> 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/u74,core
> +0x5b7-0x0-0x0,v1,thead/c900-legacy,core
> diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json
> new file mode 100644
> index 000000000000..2b142348d635
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/cache.json
> @@ -0,0 +1,67 @@
> +[
> + {
> + "EventName": "L1_ICACHE_ACCESS",
> + "EventCode": "0x00000001",
> + "BriefDescription": "L1 instruction cache access"
> + },
> + {
> + "EventName": "L1_ICACHE_MISS",
> + "EventCode": "0x00000002",
> + "BriefDescription": "L1 instruction cache miss"
> + },
> + {
> + "EventName": "ITLB_MISS",
> + "EventCode": "0x00000003",
> + "BriefDescription": "I-UTLB miss"
> + },
> + {
> + "EventName": "DTLB_MISS",
> + "EventCode": "0x00000004",
> + "BriefDescription": "D-UTLB miss"
> + },
> + {
> + "EventName": "JTLB_MISS",
> + "EventCode": "0x00000005",
> + "BriefDescription": "JTLB miss"
> + },
> + {
> + "EventName": "L1_DCACHE_READ_ACCESS",
> + "EventCode": "0x0000000c",
> + "BriefDescription": "L1 data cache read access"
> + },
> + {
> + "EventName": "L1_DCACHE_READ_MISS",
> + "EventCode": "0x0000000d",
> + "BriefDescription": "L1 data cache read miss"
> + },
> + {
> + "EventName": "L1_DCACHE_WRITE_ACCESS",
> + "EventCode": "0x0000000e",
> + "BriefDescription": "L1 data cache write access"
> + },
> + {
> + "EventName": "L1_DCACHE_WRITE_MISS",
> + "EventCode": "0x0000000f",
> + "BriefDescription": "L1 data cache write miss"
> + },
> + {
> + "EventName": "LL_CACHE_READ_ACCESS",
> + "EventCode": "0x00000010",
> + "BriefDescription": "LL Cache read access"
> + },
> + {
> + "EventName": "LL_CACHE_READ_MISS",
> + "EventCode": "0x00000011",
> + "BriefDescription": "LL Cache read miss"
> + },
> + {
> + "EventName": "LL_CACHE_WRITE_ACCESS",
> + "EventCode": "0x00000012",
> + "BriefDescription": "LL Cache write access"
> + },
> + {
> + "EventName": "LL_CACHE_WRITE_MISS",
> + "EventCode": "0x00000013",
> + "BriefDescription": "LL Cache write miss"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json
> new file mode 100644
> index 000000000000..9b4a032186a7
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/firmware.json
> @@ -0,0 +1,68 @@
> +[
> + {
> + "ArchStdEvent": "FW_MISALIGNED_LOAD"
> + },
> + {
> + "ArchStdEvent": "FW_MISALIGNED_STORE"
> + },
> + {
> + "ArchStdEvent": "FW_ACCESS_LOAD"
> + },
> + {
> + "ArchStdEvent": "FW_ACCESS_STORE"
> + },
> + {
> + "ArchStdEvent": "FW_ILLEGAL_INSN"
> + },
> + {
> + "ArchStdEvent": "FW_SET_TIMER"
> + },
> + {
> + "ArchStdEvent": "FW_IPI_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_IPI_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_FENCE_I_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_FENCE_I_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_SFENCE_VMA_ASID_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_GVMA_VMID_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_RECEIVED"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_SENT"
> + },
> + {
> + "ArchStdEvent": "FW_HFENCE_VVMA_ASID_RECEIVED"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/instruction.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/instruction.json
> new file mode 100644
> index 000000000000..c822b5373333
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/instruction.json
> @@ -0,0 +1,72 @@
> +[
> + {
> + "EventName": "INST_BRANCH_MISPREDICT",
> + "EventCode": "0x00000006",
> + "BriefDescription": "Mispredicted branch instructions"
> + },
> + {
> + "EventName": "INST_BRANCH",
> + "EventCode": "0x00000007",
> + "BriefDescription": "Retired branch instructions"
> + },
> + {
> + "EventName": "INST_JMP_MISPREDICT",
> + "EventCode": "0x00000008",
> + "BriefDescription": "Indirect branch mispredict"
> + },
> + {
> + "EventName": "INST_JMP",
> + "EventCode": "0x00000009",
> + "BriefDescription": "Retired jmp instructions"
> + },
> + {
> + "EventName": "INST_STORE",
> + "EventCode": "0x0000000b",
> + "BriefDescription": "Retired store instructions"
> + },
> + {
> + "EventName": "INST_ALU",
> + "EventCode": "0x0000001d",
> + "BriefDescription": "Retired ALU instructions"
> + },
> + {
> + "EventName": "INST_LDST",
> + "EventCode": "0x0000001e",
> + "BriefDescription": "Retired Load/Store instructions"
> + },
> + {
> + "EventName": "INST_VECTOR",
> + "EventCode": "0x0000001f",
> + "BriefDescription": "Retired Vector instructions"
> + },
> + {
> + "EventName": "INST_CSR",
> + "EventCode": "0x00000020",
> + "BriefDescription": "Retired CSR instructions"
> + },
> + {
> + "EventName": "INST_SYNC",
> + "EventCode": "0x00000021",
> + "BriefDescription": "Retired sync instructions (AMO/LR/SC instructions)"
> + },
> + {
> + "EventName": "INST_UNALIGNED_ACCESS",
> + "EventCode": "0x00000022",
> + "BriefDescription": "Retired Store/Load instructions with unaligned memory access"
> + },
> + {
> + "EventName": "INST_ECALL",
> + "EventCode": "0x00000025",
> + "BriefDescription": "Retired ecall instructions"
> + },
> + {
> + "EventName": "INST_LONG_JP",
> + "EventCode": "0x00000026",
> + "BriefDescription": "Retired long jump instructions"
> + },
> + {
> + "EventName": "INST_FP",
> + "EventCode": "0x0000002a",
> + "BriefDescription": "Retired FPU instructions"
> + }
> +]
> diff --git a/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/microarch.json b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/microarch.json
> new file mode 100644
> index 000000000000..0ab6f288af91
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/thead/c900-legacy/microarch.json
> @@ -0,0 +1,80 @@
> +[
> + {
> + "EventName": "LSU_SPEC_FAIL",
> + "EventCode": "0x0000000a",
> + "BriefDescription": "LSU speculation fail"
> + },
> + {
> + "EventName": "IDU_RF_PIPE_FAIL",
> + "EventCode": "0x00000014",
> + "BriefDescription": "Instruction decode unit launch pipeline failed in RF state"
> + },
> + {
> + "EventName": "IDU_RF_REG_FAIL",
> + "EventCode": "0x00000015",
> + "BriefDescription": "Instruction decode unit launch register file fail in RF state"
> + },
> + {
> + "EventName": "IDU_RF_INSTRUCTION",
> + "EventCode": "0x00000016",
> + "BriefDescription": "retired instruction count of Instruction decode unit in RF (Register File) stage"
> + },
> + {
> + "EventName": "LSU_4K_STALL",
> + "EventCode": "0x00000017",
> + "BriefDescription": "LSU stall times for long distance data access (Over 4K)",
> + "PublicDescription": "This stall occurs when translate virtual address with page offset over 4k"
> + },
> + {
> + "EventName": "LSU_OTHER_STALL",
> + "EventCode": "0x00000018",
> + "BriefDescription": "LSU stall times for other reasons (except the 4k stall)"
> + },
> + {
> + "EventName": "LSU_SQ_OTHER_DIS",
> + "EventCode": "0x00000019",
> + "BriefDescription": "LSU store queue discard others"
> + },
> + {
> + "EventName": "LSU_SQ_DATA_DISCARD",
> + "EventCode": "0x0000001a",
> + "BriefDescription": "LSU store queue discard data (uops)"
> + },
> + {
> + "EventName": "BRANCH_DIRECTION_MISPREDICTION",
> + "EventCode": "0x0000001b",
> + "BriefDescription": "Branch misprediction in BTB"
> + },
> + {
> + "EventName": "BRANCH_DIRECTION_PREDICTION",
> + "EventCode": "0x0000001c",
> + "BriefDescription": "All branch prediction in BTB",
> + "PublicDescription": "This event including both successful prediction and failed prediction in BTB"
> + },
> + {
> + "EventName": "INTERRUPT_ACK_COUNT",
> + "EventCode": "0x00000023",
> + "BriefDescription": "acknowledged interrupt count"
> + },
> + {
> + "EventName": "INTERRUPT_OFF_CYCLE",
> + "EventCode": "0x00000024",
> + "BriefDescription": "PLIC arbitration time when the interrupt is not responded",
> + "PublicDescription": "The arbitration time is recorded while meeting any of the following:\n- CPU is M-mode and MIE == 0\n- CPU is S-mode and delegation and SIE == 0\n"
> + },
> + {
> + "EventName": "IFU_STALLED_CYCLE",
> + "EventCode": "0x00000027",
> + "BriefDescription": "Number of stall cycles of the instruction fetch unit (IFU)."
> + },
> + {
> + "EventName": "IDU_STALLED_CYCLE",
> + "EventCode": "0x00000028",
> + "BriefDescription": "hpcp_backend_stall Number of stall cycles of the instruction decoding unit (IDU) and next-level pipeline unit."
> + },
> + {
> + "EventName": "SYNC_STALL",
> + "EventCode": "0x00000029",
> + "BriefDescription": "Sync instruction stall cycle fence/fence.i/sync/sfence"
> + }
> +]
> --
> 2.41.0
>
--
Best Regards
Guo Ren
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2023-08-26 8:44 [PATCH V4] perf vendor events riscv: add T-HEAD C9xx JSON file Inochi Amaoto
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