* [PATCH] riscv: mm: update T-Head memory type definitions
@ 2023-08-27 9:06 Jisheng Zhang
2023-08-27 10:23 ` Guo Ren
2023-09-04 20:22 ` Drew Fustini
0 siblings, 2 replies; 3+ messages in thread
From: Jisheng Zhang @ 2023-08-27 9:06 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren
Cc: linux-riscv, linux-kernel
Update T-Head memory type definitions according to C910 doc [1]
For NC and IO, SH property isn't configurable, hardcoded as SH,
so set SH for NOCACHE and IO.
And also set bit[61](Bufferable) for NOCACHE according to the
table 6.1 in the doc [1].
Link: https://github.com/T-head-Semi/openc910 [1]
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
arch/riscv/include/asm/pgtable-64.h | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index 7a5097202e15..9a2c780a11e9 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -126,14 +126,18 @@ enum napot_cont_order {
/*
* [63:59] T-Head Memory Type definitions:
- *
- * 00000 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
+ * bit[63] SO - Strong Order
+ * bit[62] C - Cacheable
+ * bit[61] B - Bufferable
+ * bit[60] SH - Shareable
+ * bit[59] Sec - Trustable
+ * 00110 - NC Weakly-ordered, Non-cacheable, Bufferable, Shareable, Non-trustable
* 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable
- * 10000 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
+ * 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
*/
#define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60))
-#define _PAGE_NOCACHE_THEAD 0UL
-#define _PAGE_IO_THEAD (1UL << 63)
+#define _PAGE_NOCACHE_THEAD ((1UL < 61) | (1UL << 60))
+#define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60))
#define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
static inline u64 riscv_page_mtmask(void)
--
2.40.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: mm: update T-Head memory type definitions
2023-08-27 9:06 [PATCH] riscv: mm: update T-Head memory type definitions Jisheng Zhang
@ 2023-08-27 10:23 ` Guo Ren
2023-09-04 20:22 ` Drew Fustini
1 sibling, 0 replies; 3+ messages in thread
From: Guo Ren @ 2023-08-27 10:23 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-riscv, linux-kernel
On Sun, Aug 27, 2023 at 5:18 AM Jisheng Zhang <jszhang@kernel.org> wrote:
>
> Update T-Head memory type definitions according to C910 doc [1]
> For NC and IO, SH property isn't configurable, hardcoded as SH,
> so set SH for NOCACHE and IO.
>
> And also set bit[61](Bufferable) for NOCACHE according to the
> table 6.1 in the doc [1].
>
> Link: https://github.com/T-head-Semi/openc910 [1]
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/include/asm/pgtable-64.h | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> index 7a5097202e15..9a2c780a11e9 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -126,14 +126,18 @@ enum napot_cont_order {
>
> /*
> * [63:59] T-Head Memory Type definitions:
> - *
> - * 00000 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
> + * bit[63] SO - Strong Order
> + * bit[62] C - Cacheable
> + * bit[61] B - Bufferable
> + * bit[60] SH - Shareable
> + * bit[59] Sec - Trustable
> + * 00110 - NC Weakly-ordered, Non-cacheable, Bufferable, Shareable, Non-trustable
> * 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable
> - * 10000 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
> + * 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
> */
> #define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60))
> -#define _PAGE_NOCACHE_THEAD 0UL
> -#define _PAGE_IO_THEAD (1UL << 63)
> +#define _PAGE_NOCACHE_THEAD ((1UL < 61) | (1UL << 60))
> +#define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60))
Yes, SH does not affect D1, but let's keep th1520 & d1 & sg2042 with
the same definitions.
Reviewed-by: Guo Ren <guoren@kernel.org>
> #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
>
> static inline u64 riscv_page_mtmask(void)
> --
> 2.40.1
>
--
Best Regards
Guo Ren
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] riscv: mm: update T-Head memory type definitions
2023-08-27 9:06 [PATCH] riscv: mm: update T-Head memory type definitions Jisheng Zhang
2023-08-27 10:23 ` Guo Ren
@ 2023-09-04 20:22 ` Drew Fustini
1 sibling, 0 replies; 3+ messages in thread
From: Drew Fustini @ 2023-09-04 20:22 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Guo Ren, linux-riscv,
linux-kernel
On Sun, Aug 27, 2023 at 05:06:44PM +0800, Jisheng Zhang wrote:
> Update T-Head memory type definitions according to C910 doc [1]
> For NC and IO, SH property isn't configurable, hardcoded as SH,
> so set SH for NOCACHE and IO.
>
> And also set bit[61](Bufferable) for NOCACHE according to the
> table 6.1 in the doc [1].
>
> Link: https://github.com/T-head-Semi/openc910 [1]
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/include/asm/pgtable-64.h | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> index 7a5097202e15..9a2c780a11e9 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -126,14 +126,18 @@ enum napot_cont_order {
>
> /*
> * [63:59] T-Head Memory Type definitions:
> - *
> - * 00000 - NC Weakly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
> + * bit[63] SO - Strong Order
> + * bit[62] C - Cacheable
> + * bit[61] B - Bufferable
> + * bit[60] SH - Shareable
> + * bit[59] Sec - Trustable
> + * 00110 - NC Weakly-ordered, Non-cacheable, Bufferable, Shareable, Non-trustable
> * 01110 - PMA Weakly-ordered, Cacheable, Bufferable, Shareable, Non-trustable
> - * 10000 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Non-shareable, Non-trustable
> + * 10010 - IO Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
> */
> #define _PAGE_PMA_THEAD ((1UL << 62) | (1UL << 61) | (1UL << 60))
> -#define _PAGE_NOCACHE_THEAD 0UL
> -#define _PAGE_IO_THEAD (1UL << 63)
> +#define _PAGE_NOCACHE_THEAD ((1UL < 61) | (1UL << 60))
> +#define _PAGE_IO_THEAD ((1UL << 63) | (1UL << 60))
> #define _PAGE_MTMASK_THEAD (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
>
> static inline u64 riscv_page_mtmask(void)
> --
> 2.40.1
>
Tested-by: Drew Fustini <dfustini@baylibre.com>
I applied this on top of:
[1] riscv: errata: improve T-Head CMO
[2] riscv: dts: thead: set dma-noncoherent to soc bus
[3] RISC-V: Add basic eMMC support for BeagleV Ahead
The BeagleV Ahead eMMC continues to function okay in ADMA mode after
this patch was applied.
Thanks,
Drew
[1] https://lore.kernel.org/linux-riscv/20230827090813.1353-1-jszhang@kernel.org/
[2] https://lore.kernel.org/linux-riscv/ZOIBQI3L4kP7c%2FT1@xhacker/
[3] https://lore.kernel.org/linux-riscv/20230724-th1520-emmc-v2-0-132ed2e2171e@baylibre.com/
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