[PATCH v3 0/7] Add support for Allwinner H6 DVFS

[PATCH v3 0/7] Add support for Allwinner H6 DVFS

[Clément Péron]

Hi Sunxi maintainers and members,

Now that required drivers are merged we can contibute on DVFS
support for Allwinner H6.

This serie is based on Yangtao Li serie[0] and Ondřej Jirman work[1].

Most of the OPP tables are taken from original vendor kernel[2].
Plus there are new CPU frequencies at 1.6GHz, 1.7GHz and 1.8GHz.

I wrote a simple script to randomly set a frequency during
a random time[3]. This script is quite stressfull and set some high
frequency without checking temperature. This can result on behavior
that whould not occurs with the real cpufreq framework.
As Maxime point out I also tested with cpufreq-ljt-stress-test
(found here https://github.com/ssvb/cpuburn-arm).
This script doesn't trigger any issue.
I also test that that offlining CPU0 and doing DVFS on other CPUs
works. As CPU regulator is only set for CPU0.

The GPU devfreq was drop as the regulator is still not properly
drive by panfrost driver[4].
I will re-introduce it later.

Ondřej Jirman has an Orange Pi 3, Jernej has a PineH64 and a Tanix
TX6 boards and I have a Beelink GS1 board so I have enable these
boards. But CPU Devfreq is really touchy has it depends on:
board design, SoC speed_grade and environement which can affect
thermal cooling and have different behavior for different user.

If people can test this serie and give feedback, I will try to
introduce this in LibreElec tree, so LE community can test it.

Thanks,
Clément

0: https://patchwork.kernel.org/cover/10815117/
1: https://megous.com/git/linux/log/?h=ths-5.7
2: https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/arch/arm64/boot/dts/sunxi/sun50iw6p1.dtsi#L345-L517
3: https://gist.github.com/clementperon/55a055dae3f13bbd14fb39c0069fe2e2
4: https://patchwork.kernel.org/patch/11486893/

Changes since v2 (thanks to Maxime Ripard):
  - Change Orange Pi boards to Orange Pi 3
  - Change soc speed nvmem node name
  - Fix device tree warnings
  - Drop GPU opp tables

Changes since v1 (thanks to Ondřej Jirman):
  - Remove Polling thermal
  - Add Orange Pi boards
  - Remove minimal voltage change for Beelink GS1
  - Add ramp-deplay for GPU and CPU regulators
  - Push to thermal point to 85°C (Allwinner set them to 100°C and 115°C)
  - Added 1.6GHz and 1.7GHz to OPP table.

Clément Péron (6):
  arm64: configs: Enable sun50i cpufreq nvmem
  arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
  arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
  arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
  arm64: dts: allwinner: Sort Pine H64 device-tree nodes
  arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Pine H64

Ondrej Jirman (1):
  arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

 .../dts/allwinner/sun50i-h6-beelink-gs1.dts   |   9 +-
 .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
 .../dts/allwinner/sun50i-h6-orangepi-3.dts    |   3 +
 .../boot/dts/allwinner/sun50i-h6-pine-h64.dts |  41 +++---
 .../dts/allwinner/sun50i-h6-tanix-tx6.dts     |  13 ++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |   4 +
 arch/arm64/configs/defconfig                  |   1 +
 7 files changed, 174 insertions(+), 18 deletions(-)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi

-- 
2.20.1

[PATCH v3 1/7] arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

[Clément Péron]

From: Ondrej Jirman <megous@megous.com>

Add an Operating Performance Points table for the CPU cores to
enable Dynamic Voltage & Frequency Scaling on the H6.

Signed-off-by: Ondrej Jirman <megous@megous.com>
Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 .../boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi | 121 ++++++++++++++++++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  |   4 +
 2 files changed, 125 insertions(+)
 create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
new file mode 100644
index 000000000000..9ebd97b04b1a
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-cpu-opp.dtsi
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
+// Copyright (C) 2020 Clément Péron <peron.clem@gmail.com>
+
+/ {
+	cpu_opp_table: cpu-opp-table {
+		compatible = "allwinner,sun50i-h6-operating-points";
+		nvmem-cells = <&cpu_speed_grade>;
+		opp-shared;
+
+		opp@480000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <480000000>;
+
+			opp-microvolt-speed0 = <880000>;
+			opp-microvolt-speed1 = <820000>;
+			opp-microvolt-speed2 = <820000>;
+		};
+
+		opp@720000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <720000000>;
+
+			opp-microvolt-speed0 = <880000>;
+			opp-microvolt-speed1 = <820000>;
+			opp-microvolt-speed2 = <820000>;
+		};
+
+		opp@816000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <816000000>;
+
+			opp-microvolt-speed0 = <880000>;
+			opp-microvolt-speed1 = <820000>;
+			opp-microvolt-speed2 = <820000>;
+		};
+
+		opp@888000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <888000000>;
+
+			opp-microvolt-speed0 = <880000>;
+			opp-microvolt-speed1 = <820000>;
+			opp-microvolt-speed2 = <820000>;
+		};
+
+		opp@1080000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1080000000>;
+
+			opp-microvolt-speed0 = <940000>;
+			opp-microvolt-speed1 = <880000>;
+			opp-microvolt-speed2 = <880000>;
+		};
+
+		opp@1320000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1320000000>;
+
+			opp-microvolt-speed0 = <1000000>;
+			opp-microvolt-speed1 = <940000>;
+			opp-microvolt-speed2 = <940000>;
+		};
+
+		opp@1488000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1488000000>;
+
+			opp-microvolt-speed0 = <1060000>;
+			opp-microvolt-speed1 = <1000000>;
+			opp-microvolt-speed2 = <1000000>;
+		};
+
+		opp@1608000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1608000000>;
+
+			opp-microvolt-speed0 = <1090000>;
+			opp-microvolt-speed1 = <1030000>;
+			opp-microvolt-speed2 = <1030000>;
+		};
+
+		opp@1704000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1704000000>;
+
+			opp-microvolt-speed0 = <1120000>;
+			opp-microvolt-speed1 = <1060000>;
+			opp-microvolt-speed2 = <1060000>;
+		};
+
+		opp@1800000000 {
+			clock-latency-ns = <244144>; /* 8 32k periods */
+			opp-hz = /bits/ 64 <1800000000>;
+
+			opp-microvolt-speed0 = <1160000>;
+			opp-microvolt-speed1 = <1100000>;
+			opp-microvolt-speed2 = <1100000>;
+		};
+	};
+};
+
+&cpu0 {
+	operating-points-v2 = <&cpu_opp_table>;
+	#cooling-cells = <2>;
+};
+
+&cpu1 {
+	operating-points-v2 = <&cpu_opp_table>;
+	#cooling-cells = <2>;
+};
+
+&cpu2 {
+	operating-points-v2 = <&cpu_opp_table>;
+	#cooling-cells = <2>;
+};
+
+&cpu3 {
+	operating-points-v2 = <&cpu_opp_table>;
+	#cooling-cells = <2>;
+};
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 60da1627772b..83e32f9c4977 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -258,6 +258,10 @@
 			ths_calibration: thermal-sensor-calibration@14 {
 				reg = <0x14 0x8>;
 			};
+
+			cpu_speed_grade: cpu-speed-grade@1c {
+				reg = <0x1c 0x4>;
+			};
 		};
 
 		watchdog: watchdog@30090a0 {
-- 
2.20.1

[PATCH v3 2/7] arm64: configs: Enable sun50i cpufreq nvmem

[Clément Péron]

Allwinner H6 needs this driver to be able to get
the correct speed_bin required for DVFS.

Enable this option in arm64 defconfig.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f9eefb5940ca..37e512c135ba 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -84,6 +84,7 @@ CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
 CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
 CONFIG_CPUFREQ_DT=y
 CONFIG_ACPI_CPPC_CPUFREQ=m
+CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
 CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
 CONFIG_ARM_SCPI_CPUFREQ=y
 CONFIG_ARM_IMX_CPUFREQ_DT=m
-- 
2.20.1

[PATCH v3 3/7] arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1

[Clément Péron]

Enable CPU opp tables for Beelink GS1.

This needs to change the CPU regulator max voltage to fit
the OPP table.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 8f09d209359b..3f7ceeb1a767 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -77,6 +78,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdca>;
+};
+
 &de {
 	status = "okay";
 };
@@ -234,7 +239,8 @@
 			reg_dcdca: dcdca {
 				regulator-always-on;
 				regulator-min-microvolt = <810000>;
-				regulator-max-microvolt = <1080000>;
+				regulator-max-microvolt = <1160000>;
+				regulator-ramp-delay = <2500>;
 				regulator-name = "vdd-cpu";
 			};
 
@@ -242,6 +248,7 @@
 				regulator-enable-ramp-delay = <32000>;
 				regulator-min-microvolt = <810000>;
 				regulator-max-microvolt = <1080000>;
+				regulator-ramp-delay = <2500>;
 				regulator-name = "vdd-gpu";
 			};
 
-- 
2.20.1

[PATCH v3 4/7] arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3

[Clément Péron]

Enable CPU opp tables for Orange Pi 3.

This needs to change the CPU regulator max voltage to fit
the OPP table.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 47f579610dcc..15c9dd8c4479 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -257,6 +258,7 @@
 				regulator-always-on;
 				regulator-min-microvolt = <800000>;
 				regulator-max-microvolt = <1160000>;
+				regulator-ramp-delay = <2500>;
 				regulator-name = "vdd-cpu";
 			};
 
@@ -264,6 +266,7 @@
 				regulator-enable-ramp-delay = <32000>;
 				regulator-min-microvolt = <810000>;
 				regulator-max-microvolt = <1080000>;
+				regulator-ramp-delay = <2500>;
 				regulator-name = "vdd-gpu";
 			};
 
-- 
2.20.1

[PATCH v3 5/7] arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6

[Clément Péron]

Enable CPU opp tables for Tanix TX6.

Also add the fixed regulator that provided vdd-cpu-gpu required for
CPU opp tables.

This voltage has been found using a voltmeter and could be wrong.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 .../boot/dts/allwinner/sun50i-h6-tanix-tx6.dts      | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
index 83e6cb0e59ce..be81330db14f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6.dts
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -37,6 +38,17 @@
 		regulator-min-microvolt = <3300000>;
 		regulator-max-microvolt = <3300000>;
 	};
+
+	reg_vdd_cpu_gpu: vdd-cpu-gpu {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-cpu-gpu";
+		regulator-min-microvolt = <1135000>;
+		regulator-max-microvolt = <1135000>;
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&reg_vdd_cpu_gpu>;
 };
 
 &de {
@@ -56,6 +68,7 @@
 };
 
 &gpu {
+	mali-supply = <&reg_vdd_cpu_gpu>;
 	status = "okay";
 };
 
-- 
2.20.1

[PATCH v3 6/7] arm64: dts: allwinner: Sort Pine H64 device-tree nodes

[Clément Péron]

Pine H64 device-tree have some nodes not properly sorted.

Fix this.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 34 +++++++++----------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index b0642d841933..63a785b534e1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -80,6 +80,18 @@
 	};
 };
 
+&de {
+	status = "okay";
+};
+
+&ehci0 {
+	status = "okay";
+};
+
+&ehci3 {
+	status = "okay";
+};
+
 &emac {
 	pinctrl-names = "default";
 	pinctrl-0 = <&ext_rgmii_pins>;
@@ -91,17 +103,6 @@
 	status = "okay";
 };
 
-&mdio {
-	ext_rgmii_phy: ethernet-phy@1 {
-		compatible = "ethernet-phy-ieee802.3-c22";
-		reg = <1>;
-	};
-};
-
-&de {
-	status = "okay";
-};
-
 &gpu {
 	mali-supply = <&reg_dcdcc>;
 	status = "okay";
@@ -117,12 +118,11 @@
 	};
 };
 
-&ehci0 {
-	status = "okay";
-};
-
-&ehci3 {
-	status = "okay";
+&mdio {
+	ext_rgmii_phy: ethernet-phy@1 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <1>;
+	};
 };
 
 &mmc0 {
-- 
2.20.1

[PATCH v3 7/7] arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Pine H64

[Clément Péron]

Enable CPU and GPU opp tables for Pine H64.

Also add the ramp-delay information to avoid any out of spec
running as the regulator is slower at reaching the voltage
requested compare to the PLL reaching the frequency.

There is no such information for AXP805 but similar PMIC (AXP813)
has a DVM (Dynamic Voltage scaling Management) ramp rate equal
to 2500uV/us.

Signed-off-by: Clément Péron <peron.clem@gmail.com>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 63a785b534e1..60fd33f657dc 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -4,6 +4,7 @@
 /dts-v1/;
 
 #include "sun50i-h6.dtsi"
+#include "sun50i-h6-cpu-opp.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 
@@ -80,6 +81,10 @@
 	};
 };
 
+&cpu0 {
+	cpu-supply = <&reg_dcdca>;
+};
+
 &de {
 	status = "okay";
 };
@@ -239,6 +244,7 @@
 				regulator-always-on;
 				regulator-min-microvolt = <810000>;
 				regulator-max-microvolt = <1080000>;
+				regulator-ramp-delay = <2500>;
 				regulator-name = "vdd-cpu";
 			};
 
@@ -246,6 +252,7 @@
 				regulator-enable-ramp-delay = <32000>;
 				regulator-min-microvolt = <810000>;
 				regulator-max-microvolt = <1080000>;
+				regulator-ramp-delay = <2500>;
 				regulator-name = "vdd-gpu";
 			};
 
-- 
2.20.1

Re: [PATCH v3 0/7] Add support for Allwinner H6 DVFS

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 1583 bytes --]

Hi,

On Sun, Apr 19, 2020 at 03:50:04PM +0200, Clément Péron wrote:
> Now that required drivers are merged we can contibute on DVFS
> support for Allwinner H6.
> 
> This serie is based on Yangtao Li serie[0] and Ondřej Jirman work[1].
> 
> Most of the OPP tables are taken from original vendor kernel[2].
> Plus there are new CPU frequencies at 1.6GHz, 1.7GHz and 1.8GHz.
> 
> I wrote a simple script to randomly set a frequency during
> a random time[3]. This script is quite stressfull and set some high
> frequency without checking temperature. This can result on behavior
> that whould not occurs with the real cpufreq framework.
> As Maxime point out I also tested with cpufreq-ljt-stress-test
> (found here https://github.com/ssvb/cpuburn-arm).
> This script doesn't trigger any issue.
> I also test that that offlining CPU0 and doing DVFS on other CPUs
> works. As CPU regulator is only set for CPU0.
> 
> The GPU devfreq was drop as the regulator is still not properly
> drive by panfrost driver[4].
> I will re-introduce it later.
> 
> Ondřej Jirman has an Orange Pi 3, Jernej has a PineH64 and a Tanix
> TX6 boards and I have a Beelink GS1 board so I have enable these
> boards. But CPU Devfreq is really touchy has it depends on:
> board design, SoC speed_grade and environement which can affect
> thermal cooling and have different behavior for different user.
> 
> If people can test this serie and give feedback, I will try to
> introduce this in LibreElec tree, so LE community can test it.

Applied all of them, thanks!
Maxime

[-- Attachment #2: signature.asc --]
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Re: [PATCH v3 0/7] Add support for Allwinner H6 DVFS

[Ondřej Jirman]

Hi Maxime,

On Mon, Apr 20, 2020 at 10:45:47AM +0200, Maxime Ripard wrote:
> Hi,
> 
> On Sun, Apr 19, 2020 at 03:50:04PM +0200, Clément Péron wrote:
> > Now that required drivers are merged we can contibute on DVFS
> > support for Allwinner H6.
> > 
> > This serie is based on Yangtao Li serie[0] and Ondřej Jirman work[1].
> > 
> > Most of the OPP tables are taken from original vendor kernel[2].
> > Plus there are new CPU frequencies at 1.6GHz, 1.7GHz and 1.8GHz.
> > 
> > I wrote a simple script to randomly set a frequency during
> > a random time[3]. This script is quite stressfull and set some high
> > frequency without checking temperature. This can result on behavior
> > that whould not occurs with the real cpufreq framework.
> > As Maxime point out I also tested with cpufreq-ljt-stress-test
> > (found here https://github.com/ssvb/cpuburn-arm).
> > This script doesn't trigger any issue.
> > I also test that that offlining CPU0 and doing DVFS on other CPUs
> > works. As CPU regulator is only set for CPU0.
> > 
> > The GPU devfreq was drop as the regulator is still not properly
> > drive by panfrost driver[4].
> > I will re-introduce it later.
> > 
> > Ondřej Jirman has an Orange Pi 3, Jernej has a PineH64 and a Tanix
> > TX6 boards and I have a Beelink GS1 board so I have enable these
> > boards. But CPU Devfreq is really touchy has it depends on:
> > board design, SoC speed_grade and environement which can affect
> > thermal cooling and have different behavior for different user.
> > 
> > If people can test this serie and give feedback, I will try to
> > introduce this in LibreElec tree, so LE community can test it.
> 
> Applied all of them, thanks!

Please also apply "[PATCH v2 1/7] arm64: dts: allwinner: h6: Add
clock to CPU cores" from the v2 series, otherwise cpufreq will
not work.

I can also send a missing patch adding the trip points, and cpu
as a cooling device, that I linked in my other reply to this patch
series afterwards, if Clément wants.

regards,
	o.

> Maxime

Re: [PATCH v3 0/7] Add support for Allwinner H6 DVFS

[Clément Péron]

Hi Ondrej, Maxime,

On Mon, 20 Apr 2020 at 12:39, Ondřej Jirman <megous@megous.com> wrote:
>
> Hi Maxime,
>
> On Mon, Apr 20, 2020 at 10:45:47AM +0200, Maxime Ripard wrote:
> > Hi,
> >
> > On Sun, Apr 19, 2020 at 03:50:04PM +0200, Clément Péron wrote:
> > > Now that required drivers are merged we can contibute on DVFS
> > > support for Allwinner H6.
> > >
> > > This serie is based on Yangtao Li serie[0] and Ondřej Jirman work[1].
> > >
> > > Most of the OPP tables are taken from original vendor kernel[2].
> > > Plus there are new CPU frequencies at 1.6GHz, 1.7GHz and 1.8GHz.
> > >
> > > I wrote a simple script to randomly set a frequency during
> > > a random time[3]. This script is quite stressfull and set some high
> > > frequency without checking temperature. This can result on behavior
> > > that whould not occurs with the real cpufreq framework.
> > > As Maxime point out I also tested with cpufreq-ljt-stress-test
> > > (found here https://github.com/ssvb/cpuburn-arm).
> > > This script doesn't trigger any issue.
> > > I also test that that offlining CPU0 and doing DVFS on other CPUs
> > > works. As CPU regulator is only set for CPU0.
> > >
> > > The GPU devfreq was drop as the regulator is still not properly
> > > drive by panfrost driver[4].
> > > I will re-introduce it later.
> > >
> > > Ondřej Jirman has an Orange Pi 3, Jernej has a PineH64 and a Tanix
> > > TX6 boards and I have a Beelink GS1 board so I have enable these
> > > boards. But CPU Devfreq is really touchy has it depends on:
> > > board design, SoC speed_grade and environement which can affect
> > > thermal cooling and have different behavior for different user.
> > >
> > > If people can test this serie and give feedback, I will try to
> > > introduce this in LibreElec tree, so LE community can test it.
> >
> > Applied all of them, thanks!
>
> Please also apply "[PATCH v2 1/7] arm64: dts: allwinner: h6: Add
> clock to CPU cores" from the v2 series, otherwise cpufreq will
> not work.
>
> I can also send a missing patch adding the trip points, and cpu
> as a cooling device, that I linked in my other reply to this patch
> series afterwards, if Clément wants.

Indeed I have sent using the following cmd : "git send-email --to=XXXX HEAD~7"
from the previous version.

I should had do Instead: "git send-email --to=XXXX next/master "

Sorry for that :(
Clément

>
> regards,
>         o.
>
> > Maxime
>
>

Re: [PATCH v3 0/7] Add support for Allwinner H6 DVFS

[Maxime Ripard]

[-- Attachment #1: Type: text/plain, Size: 2685 bytes --]

On Mon, Apr 20, 2020 at 02:36:32PM +0200, Clément Péron wrote:
> Hi Ondrej, Maxime,
> 
> On Mon, 20 Apr 2020 at 12:39, Ondřej Jirman <megous@megous.com> wrote:
> >
> > Hi Maxime,
> >
> > On Mon, Apr 20, 2020 at 10:45:47AM +0200, Maxime Ripard wrote:
> > > Hi,
> > >
> > > On Sun, Apr 19, 2020 at 03:50:04PM +0200, Clément Péron wrote:
> > > > Now that required drivers are merged we can contibute on DVFS
> > > > support for Allwinner H6.
> > > >
> > > > This serie is based on Yangtao Li serie[0] and Ondřej Jirman work[1].
> > > >
> > > > Most of the OPP tables are taken from original vendor kernel[2].
> > > > Plus there are new CPU frequencies at 1.6GHz, 1.7GHz and 1.8GHz.
> > > >
> > > > I wrote a simple script to randomly set a frequency during
> > > > a random time[3]. This script is quite stressfull and set some high
> > > > frequency without checking temperature. This can result on behavior
> > > > that whould not occurs with the real cpufreq framework.
> > > > As Maxime point out I also tested with cpufreq-ljt-stress-test
> > > > (found here https://github.com/ssvb/cpuburn-arm).
> > > > This script doesn't trigger any issue.
> > > > I also test that that offlining CPU0 and doing DVFS on other CPUs
> > > > works. As CPU regulator is only set for CPU0.
> > > >
> > > > The GPU devfreq was drop as the regulator is still not properly
> > > > drive by panfrost driver[4].
> > > > I will re-introduce it later.
> > > >
> > > > Ondřej Jirman has an Orange Pi 3, Jernej has a PineH64 and a Tanix
> > > > TX6 boards and I have a Beelink GS1 board so I have enable these
> > > > boards. But CPU Devfreq is really touchy has it depends on:
> > > > board design, SoC speed_grade and environement which can affect
> > > > thermal cooling and have different behavior for different user.
> > > >
> > > > If people can test this serie and give feedback, I will try to
> > > > introduce this in LibreElec tree, so LE community can test it.
> > >
> > > Applied all of them, thanks!
> >
> > Please also apply "[PATCH v2 1/7] arm64: dts: allwinner: h6: Add
> > clock to CPU cores" from the v2 series, otherwise cpufreq will
> > not work.
> >
> > I can also send a missing patch adding the trip points, and cpu
> > as a cooling device, that I linked in my other reply to this patch
> > series afterwards, if Clément wants.
> 
> Indeed I have sent using the following cmd : "git send-email --to=XXXX HEAD~7"
> from the previous version.
> 
> I should had do Instead: "git send-email --to=XXXX next/master "
> 
> Sorry for that :(

I haven't pushed anything yet, can you resend the proper branch?

Thanks!
Maxime

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v3 0/7] Add support for Allwinner H6 DVFS

[Clément Péron]

Hi Maxime

On Mon, 20 Apr 2020 at 14:47, Maxime Ripard <maxime@cerno.tech> wrote:
>
> On Mon, Apr 20, 2020 at 02:36:32PM +0200, Clément Péron wrote:
> > Hi Ondrej, Maxime,
> >
> > On Mon, 20 Apr 2020 at 12:39, Ondřej Jirman <megous@megous.com> wrote:
> > >
> > > Hi Maxime,
> > >
> > > On Mon, Apr 20, 2020 at 10:45:47AM +0200, Maxime Ripard wrote:
> > > > Hi,
> > > >
> > > > On Sun, Apr 19, 2020 at 03:50:04PM +0200, Clément Péron wrote:
> > > > > Now that required drivers are merged we can contibute on DVFS
> > > > > support for Allwinner H6.
> > > > >
> > > > > This serie is based on Yangtao Li serie[0] and Ondřej Jirman work[1].
> > > > >
> > > > > Most of the OPP tables are taken from original vendor kernel[2].
> > > > > Plus there are new CPU frequencies at 1.6GHz, 1.7GHz and 1.8GHz.
> > > > >
> > > > > I wrote a simple script to randomly set a frequency during
> > > > > a random time[3]. This script is quite stressfull and set some high
> > > > > frequency without checking temperature. This can result on behavior
> > > > > that whould not occurs with the real cpufreq framework.
> > > > > As Maxime point out I also tested with cpufreq-ljt-stress-test
> > > > > (found here https://github.com/ssvb/cpuburn-arm).
> > > > > This script doesn't trigger any issue.
> > > > > I also test that that offlining CPU0 and doing DVFS on other CPUs
> > > > > works. As CPU regulator is only set for CPU0.
> > > > >
> > > > > The GPU devfreq was drop as the regulator is still not properly
> > > > > drive by panfrost driver[4].
> > > > > I will re-introduce it later.
> > > > >
> > > > > Ondřej Jirman has an Orange Pi 3, Jernej has a PineH64 and a Tanix
> > > > > TX6 boards and I have a Beelink GS1 board so I have enable these
> > > > > boards. But CPU Devfreq is really touchy has it depends on:
> > > > > board design, SoC speed_grade and environement which can affect
> > > > > thermal cooling and have different behavior for different user.
> > > > >
> > > > > If people can test this serie and give feedback, I will try to
> > > > > introduce this in LibreElec tree, so LE community can test it.
> > > >
> > > > Applied all of them, thanks!
> > >
> > > Please also apply "[PATCH v2 1/7] arm64: dts: allwinner: h6: Add
> > > clock to CPU cores" from the v2 series, otherwise cpufreq will
> > > not work.
> > >
> > > I can also send a missing patch adding the trip points, and cpu
> > > as a cooling device, that I linked in my other reply to this patch
> > > series afterwards, if Clément wants.
> >
> > Indeed I have sent using the following cmd : "git send-email --to=XXXX HEAD~7"
> > from the previous version.
> >
> > I should had do Instead: "git send-email --to=XXXX next/master "
> >
> > Sorry for that :(
>
> I haven't pushed anything yet, can you resend the proper branch?

Yes, I will,

Thanks!
>
> Thanks!
> Maxime

Re: [linux-sunxi] [PATCH v3 0/7] Add support for Allwinner H6 DVFS

[Ondřej Jirman]

Hello Clément,

On Sun, Apr 19, 2020 at 03:50:04PM +0200, Clément Péron wrote:
> Hi Sunxi maintainers and members,
> 
> Now that required drivers are merged we can contibute on DVFS
> support for Allwinner H6.
> 

[ snip ]

> 
> Changes since v2 (thanks to Maxime Ripard):
>   - Change Orange Pi boards to Orange Pi 3
>   - Change soc speed nvmem node name
>   - Fix device tree warnings
>   - Drop GPU opp tables

Looks like you may have also inadverently dropped the second patch from v2
series that implemented CPU thermal trip points.

> Changes since v1 (thanks to Ondřej Jirman):
>   - Remove Polling thermal
>   - Add Orange Pi boards
>   - Remove minimal voltage change for Beelink GS1
>   - Add ramp-deplay for GPU and CPU regulators
>   - Push to thermal point to 85°C (Allwinner set them to 100°C and 115°C)
>   - Added 1.6GHz and 1.7GHz to OPP table.
> 
> Clément Péron (6):
>   arm64: configs: Enable sun50i cpufreq nvmem
>   arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
>   arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
>   arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
>   arm64: dts: allwinner: Sort Pine H64 device-tree nodes
>   arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Pine H64

You may also want to fix title of this patch to drop the GPU reference.

thank you and regards,
	o.

> Ondrej Jirman (1):
>   arm64: dts: allwinner: h6: Add CPU Operating Performance Points table

Re: [linux-sunxi] [PATCH v3 0/7] Add support for Allwinner H6 DVFS

[Ondřej Jirman]

On Mon, Apr 20, 2020 at 11:48:01AM +0200, megous hlavni wrote:
> Hello Clément,
> 
> On Sun, Apr 19, 2020 at 03:50:04PM +0200, Clément Péron wrote:
> > Hi Sunxi maintainers and members,
> > 
> > Now that required drivers are merged we can contibute on DVFS
> > support for Allwinner H6.
> > 
> 
> [ snip ]
> 
> > 
> > Changes since v2 (thanks to Maxime Ripard):
> >   - Change Orange Pi boards to Orange Pi 3
> >   - Change soc speed nvmem node name
> >   - Fix device tree warnings
> >   - Drop GPU opp tables
> 
> Looks like you may have also inadverently dropped the second patch from v2
> series that implemented CPU thermal trip points.

Also it looks like the patch 1 from v2 implementing the clock properties
is missing from v3, and I don't see it being already applied anywhere.
Without that cpufreq doesn't work.

Also, thermal trip points need to be in the opp.dtsi to avoid dtc warnings
during build.

https://megous.com/git/linux/commit/?h=ths-5.7&id=cacefd7decf5ae0ce42ab4d48a13a58552929ebd

regards,
	o.

> > Changes since v1 (thanks to Ondřej Jirman):
> >   - Remove Polling thermal
> >   - Add Orange Pi boards
> >   - Remove minimal voltage change for Beelink GS1
> >   - Add ramp-deplay for GPU and CPU regulators
> >   - Push to thermal point to 85°C (Allwinner set them to 100°C and 115°C)
> >   - Added 1.6GHz and 1.7GHz to OPP table.
> > 
> > Clément Péron (6):
> >   arm64: configs: Enable sun50i cpufreq nvmem
> >   arm64: dts: allwinner: h6: Enable CPU opp tables for Beelink GS1
> >   arm64: dts: allwinner: h6: Enable CPU opp tables for Orange Pi 3
> >   arm64: dts: allwinner: h6: Enable CPU opp tables for Tanix TX6
> >   arm64: dts: allwinner: Sort Pine H64 device-tree nodes
> >   arm64: dts: allwinner: h6: Enable CPU and GPU opp tables for Pine H64
> 
> You may also want to fix title of this patch to drop the GPU reference.
> 
> thank you and regards,
> 	o.
> 
> > Ondrej Jirman (1):
> >   arm64: dts: allwinner: h6: Add CPU Operating Performance Points table