* [PATCH v2 0/3] Add SPI dts node for UniPhier SoCs
@ 2018-07-26 7:09 Keiji Hayashibara
2018-07-26 7:09 ` [PATCH v2 1/3] ARM: dts: uniphier: add SPI pin-mux node Keiji Hayashibara
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Keiji Hayashibara @ 2018-07-26 7:09 UTC (permalink / raw)
To: robh+dt, mark.rutland, yamada.masahiro, catalin.marinas,
will.deacon, devicetree, linux-arm-kernel
Cc: masami.hiramatsu, jaswinder.singh, linux-kernel, hayashibara.keiji
This series adds SPI pin-mux node and SPI node for UniPhier SoCs.
Changes since v1:
- remove the node for MCSSI which support multiple channels.
Since the current driver doesn't support MCSSI, it deletes this node.
Kunihiko Hayashi (3):
ARM: dts: uniphier: add SPI pin-mux node
ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs
arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3
arch/arm/boot/dts/uniphier-ld4.dtsi | 11 ++++++
arch/arm/boot/dts/uniphier-pinctrl.dtsi | 20 +++++++++++
arch/arm/boot/dts/uniphier-pro4.dtsi | 11 ++++++
arch/arm/boot/dts/uniphier-pro5.dtsi | 22 ++++++++++++
arch/arm/boot/dts/uniphier-pxs2.dtsi | 22 ++++++++++++
arch/arm/boot/dts/uniphier-sld8.dtsi | 11 ++++++
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 22 ++++++++++++
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 44 ++++++++++++++++++++++++
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 22 ++++++++++++
9 files changed, 185 insertions(+)
--
2.7.4
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v2 1/3] ARM: dts: uniphier: add SPI pin-mux node
2018-07-26 7:09 [PATCH v2 0/3] Add SPI dts node for UniPhier SoCs Keiji Hayashibara
@ 2018-07-26 7:09 ` Keiji Hayashibara
2018-07-26 7:09 ` [PATCH v2 2/3] ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs Keiji Hayashibara
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Keiji Hayashibara @ 2018-07-26 7:09 UTC (permalink / raw)
To: robh+dt, mark.rutland, yamada.masahiro, catalin.marinas,
will.deacon, devicetree, linux-arm-kernel
Cc: masami.hiramatsu, jaswinder.singh, linux-kernel,
hayashibara.keiji, Kunihiko Hayashi
From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
This commit adds pin-mux nodes for SPI controller.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm/boot/dts/uniphier-pinctrl.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
index 51f0e69..5dc4cf7 100644
--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
@@ -126,6 +126,26 @@
function = "sd1";
};
+ pinctrl_spi0: spi0 {
+ groups = "spi0";
+ function = "spi0";
+ };
+
+ pinctrl_spi1: spi1 {
+ groups = "spi1";
+ function = "spi1";
+ };
+
+ pinctrl_spi2: spi2 {
+ groups = "spi2";
+ function = "spi2";
+ };
+
+ pinctrl_spi3: spi3 {
+ groups = "spi3";
+ function = "spi3";
+ };
+
pinctrl_system_bus: system-bus {
groups = "system_bus", "system_bus_cs1";
function = "system_bus";
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 2/3] ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs
2018-07-26 7:09 [PATCH v2 0/3] Add SPI dts node for UniPhier SoCs Keiji Hayashibara
2018-07-26 7:09 ` [PATCH v2 1/3] ARM: dts: uniphier: add SPI pin-mux node Keiji Hayashibara
@ 2018-07-26 7:09 ` Keiji Hayashibara
2018-07-26 7:10 ` [PATCH v2 3/3] arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3 Keiji Hayashibara
2018-08-28 14:25 ` [PATCH v2 0/3] Add SPI dts node for UniPhier SoCs Masahiro Yamada
3 siblings, 0 replies; 5+ messages in thread
From: Keiji Hayashibara @ 2018-07-26 7:09 UTC (permalink / raw)
To: robh+dt, mark.rutland, yamada.masahiro, catalin.marinas,
will.deacon, devicetree, linux-arm-kernel
Cc: masami.hiramatsu, jaswinder.singh, linux-kernel,
hayashibara.keiji, Kunihiko Hayashi
From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Add nodes of SPI controller for LD4, Pro4, sLD8, Pro5 and PXs2.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm/boot/dts/uniphier-ld4.dtsi | 11 +++++++++++
arch/arm/boot/dts/uniphier-pro4.dtsi | 11 +++++++++++
arch/arm/boot/dts/uniphier-pro5.dtsi | 22 ++++++++++++++++++++++
arch/arm/boot/dts/uniphier-pxs2.dtsi | 22 ++++++++++++++++++++++
arch/arm/boot/dts/uniphier-sld8.dtsi | 11 +++++++++++
5 files changed, 77 insertions(+)
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 37950ad..b7849be 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -63,6 +63,17 @@
cache-level = <2>;
};
+ spi: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index 49539f0..4d20692 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -71,6 +71,17 @@
cache-level = <2>;
};
+ spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 06c2cef..02d837d 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -156,6 +156,28 @@
cache-level = <3>;
};
+ spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
+ spi1: spi@54006100 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006100 0x100>;
+ interrupts = <0 216 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 641d961..15b4f75 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -164,6 +164,28 @@
cache-level = <2>;
};
+ spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
+ spi1: spi@54006100 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006100 0x100>;
+ interrupts = <0 216 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index e9b9b4f..83f832b 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -63,6 +63,17 @@
cache-level = <2>;
};
+ spi: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 3/3] arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3
2018-07-26 7:09 [PATCH v2 0/3] Add SPI dts node for UniPhier SoCs Keiji Hayashibara
2018-07-26 7:09 ` [PATCH v2 1/3] ARM: dts: uniphier: add SPI pin-mux node Keiji Hayashibara
2018-07-26 7:09 ` [PATCH v2 2/3] ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs Keiji Hayashibara
@ 2018-07-26 7:10 ` Keiji Hayashibara
2018-08-28 14:25 ` [PATCH v2 0/3] Add SPI dts node for UniPhier SoCs Masahiro Yamada
3 siblings, 0 replies; 5+ messages in thread
From: Keiji Hayashibara @ 2018-07-26 7:10 UTC (permalink / raw)
To: robh+dt, mark.rutland, yamada.masahiro, catalin.marinas,
will.deacon, devicetree, linux-arm-kernel
Cc: masami.hiramatsu, jaswinder.singh, linux-kernel,
hayashibara.keiji, Kunihiko Hayashi
From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Add nodes of SPI controller for UniPhier SoCs.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 22 ++++++++++++
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 44 ++++++++++++++++++++++++
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 22 ++++++++++++
3 files changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index d63b56e..0edab17 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -116,6 +116,28 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
+ spi1: spi@54006100 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006100 0x100>;
+ interrupts = <0 216 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 0298bd0..1213101 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -222,6 +222,50 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
+ spi1: spi@54006100 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006100 0x100>;
+ interrupts = <0 216 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
+ spi2: spi@54006200 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006200 0x100>;
+ interrupts = <0 229 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi2>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
+ spi3: spi@54006300 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006300 0x100>;
+ interrupts = <0 230 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi3>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 2a4cf42..5b40ec7 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -144,6 +144,28 @@
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
+ spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006000 0x100>;
+ interrupts = <0 39 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
+ spi1: spi@54006100 {
+ compatible = "socionext,uniphier-scssi";
+ status = "disabled";
+ reg = <0x54006100 0x100>;
+ interrupts = <0 216 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+ };
+
serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2 0/3] Add SPI dts node for UniPhier SoCs
2018-07-26 7:09 [PATCH v2 0/3] Add SPI dts node for UniPhier SoCs Keiji Hayashibara
` (2 preceding siblings ...)
2018-07-26 7:10 ` [PATCH v2 3/3] arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3 Keiji Hayashibara
@ 2018-08-28 14:25 ` Masahiro Yamada
3 siblings, 0 replies; 5+ messages in thread
From: Masahiro Yamada @ 2018-08-28 14:25 UTC (permalink / raw)
To: Keiji Hayashibara
Cc: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon, DTML,
linux-arm-kernel, Masami Hiramatsu, Jassi Brar,
Linux Kernel Mailing List
2018-07-26 16:09 GMT+09:00 Keiji Hayashibara <hayashibara.keiji@socionext.com>:
> This series adds SPI pin-mux node and SPI node for UniPhier SoCs.
>
> Changes since v1:
> - remove the node for MCSSI which support multiple channels.
> Since the current driver doesn't support MCSSI, it deletes this node.
Applied. Thanks.
> Kunihiko Hayashi (3):
> ARM: dts: uniphier: add SPI pin-mux node
> ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs
> arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3
>
> arch/arm/boot/dts/uniphier-ld4.dtsi | 11 ++++++
> arch/arm/boot/dts/uniphier-pinctrl.dtsi | 20 +++++++++++
> arch/arm/boot/dts/uniphier-pro4.dtsi | 11 ++++++
> arch/arm/boot/dts/uniphier-pro5.dtsi | 22 ++++++++++++
> arch/arm/boot/dts/uniphier-pxs2.dtsi | 22 ++++++++++++
> arch/arm/boot/dts/uniphier-sld8.dtsi | 11 ++++++
> arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 22 ++++++++++++
> arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 44 ++++++++++++++++++++++++
> arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 22 ++++++++++++
> 9 files changed, 185 insertions(+)
>
> --
> 2.7.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-08-28 14:27 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-26 7:09 [PATCH v2 0/3] Add SPI dts node for UniPhier SoCs Keiji Hayashibara
2018-07-26 7:09 ` [PATCH v2 1/3] ARM: dts: uniphier: add SPI pin-mux node Keiji Hayashibara
2018-07-26 7:09 ` [PATCH v2 2/3] ARM: dts: uniphier: add SPI node for UniPhier 32bit SoCs Keiji Hayashibara
2018-07-26 7:10 ` [PATCH v2 3/3] arm64: dts: uniphier: add SPI node for LD20, LD11 and PXs3 Keiji Hayashibara
2018-08-28 14:25 ` [PATCH v2 0/3] Add SPI dts node for UniPhier SoCs Masahiro Yamada
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).