From: Brad Larson <brad@pensando.io>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: Linux ARM <linux-arm-kernel@lists.infradead.org>,
Arnd Bergmann <arnd@arndb.de>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
Mark Brown <broonie@kernel.org>,
Serge Semin <fancer.lancer@gmail.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Olof Johansson <olof@lixom.net>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
linux-spi <linux-spi@vger.kernel.org>,
linux-mmc <linux-mmc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/8] spi: dw: Add support for Pensando Elba SoC SPI
Date: Tue, 9 Mar 2021 19:52:54 -0800 [thread overview]
Message-ID: <CAK9rFnyqkPSvSAJP12ORkSC4J0OGuYeQPNFSgbokor9HpbUh+A@mail.gmail.com> (raw)
In-Reply-To: <CACRpkdbqkmUXTPyX8OFxBRJahEL-vdxR0wP=rMAWud34bq7tcQ@mail.gmail.com>
On Thu, Mar 4, 2021 at 12:48 AM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Thu, Mar 4, 2021 at 4:42 AM Brad Larson <brad@pensando.io> wrote:
>
> > The Pensando Elba SoC uses a GPIO based chip select
> > for two DW SPI busses with each bus having two
> > chip selects.
> >
> > Signed-off-by: Brad Larson <brad@pensando.io>
>
> I agree with Serge's comments here: the existing cs callback should
> work for your SoC, you should only need the new compatible string.
>
> I see why you need the special GPIO driver for this now, as that
> is obviously driven by totally different hardware.
>
> Yours,
> Linus Walleij
Thanks Serge and Linus for the review.
In the SPI driver, the reason we need our own set_cs function is that
our DW SPI controller only supports intrinsic 2 chip-select pins.
This is the standard DW set_cs function:
void dw_spi_set_cs(struct spi_device *spi, bool enable)
{
struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
bool cs_high = !!(spi->mode & SPI_CS_HIGH);
/*
* DW SPI controller demands any native CS being set in order to
* proceed with data transfer. So in order to activate the SPI
* communications we must set a corresponding bit in the Slave
* Enable register no matter whether the SPI core is configured to
* support active-high or active-low CS level.
*/
if (cs_high == enable)
dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
else
dw_writel(dws, DW_SPI_SER, 0);
}
The dw_writel function argument DW_SPI_SER, BIT(spi->chip_select)
works for chip-select 0 & 1, but not for 2 & 3, as the IP only
implements bits [1:0] in the DW_SPI_SER register. In the Elba SoC we
require GPIO-style chip-selects, our own set_cs function, and we
always use bit 0 of DW_SPI_SER to start the serial machine, not as a
chip-select control. In the dw_spi_set_cs() function the below else
clause is never taken and leads to confusion.
} else {
/*
* Using the intrinsic DW chip-select; set the
* appropriate CS.
*/
dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
}
This else clause will be removed in patch set V2. I tried the generic
dw_spi_set_cs() thinking it would just start the serial machine while
the Elba spics drives the gpio chip select, that didn't work. I will
take another look at it as I work on V2 of the patchset to see exactly
what breaks during spi init.
Best,
Brad
next prev parent reply other threads:[~2021-03-10 3:54 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-04 3:41 [PATCH 0/8] Support Pensando Elba SoC Brad Larson
2021-03-04 3:41 ` [PATCH 1/8] gpio: Add Elba SoC gpio driver for spi cs control Brad Larson
2021-03-04 8:29 ` Linus Walleij
2021-03-04 9:10 ` Serge Semin
2021-03-04 13:38 ` Linus Walleij
2021-08-23 1:05 ` Brad Larson
2021-08-29 21:09 ` Linus Walleij
2021-10-04 16:46 ` Brad Larson
2021-10-12 23:51 ` Linus Walleij
2021-10-14 20:06 ` Brad Larson
2021-03-30 2:44 ` Brad Larson
2021-08-23 1:05 ` Brad Larson
2021-03-04 20:43 ` Elliott, Robert (Servers)
2021-08-23 1:06 ` Brad Larson
2021-03-05 11:25 ` Krzysztof Kozlowski
2021-08-23 1:07 ` Brad Larson
2021-03-05 13:57 ` Geert Uytterhoeven
2021-08-23 1:08 ` Brad Larson
2021-03-07 19:21 ` Andy Shevchenko
2021-03-29 1:19 ` Brad Larson
2021-03-29 10:39 ` Andy Shevchenko
2021-08-23 1:13 ` Brad Larson
2021-08-23 7:50 ` Geert Uytterhoeven
2021-08-23 16:30 ` Brad Larson
2021-08-23 20:11 ` Geert Uytterhoeven
2021-10-04 17:14 ` Brad Larson
2021-10-04 17:16 ` Geert Uytterhoeven
2021-08-23 1:10 ` Brad Larson
2021-03-04 3:41 ` [PATCH 2/8] spi: cadence-quadspi: Add QSPI support for Pensando Elba SoC Brad Larson
2021-03-04 9:29 ` Arnd Bergmann
2021-03-04 3:41 ` [PATCH 3/8] spi: dw: Add support for Pensando Elba SoC SPI Brad Larson
2021-03-04 6:44 ` Serge Semin
2021-08-23 1:17 ` Brad Larson
2021-03-04 8:48 ` Linus Walleij
2021-03-10 3:52 ` Brad Larson [this message]
2021-03-04 3:41 ` [PATCH 4/8] spidev: Add Pensando CPLD compatible Brad Larson
2021-03-04 9:33 ` Arnd Bergmann
2021-03-04 3:41 ` [PATCH 5/8] mmc: sdhci-cadence: Add Pensando Elba SoC support Brad Larson
2021-03-04 9:41 ` Arnd Bergmann
2021-03-04 3:41 ` [PATCH 6/8] arm64: Add config for Pensando SoC platforms Brad Larson
2021-03-04 9:42 ` Arnd Bergmann
2021-03-04 3:41 ` [PATCH 7/8] arm64: dts: Add Pensando Elba SoC support Brad Larson
2021-03-04 8:03 ` Serge Semin
2021-03-29 1:07 ` Brad Larson
2021-08-23 0:54 ` Brad Larson
2021-03-04 8:51 ` Linus Walleij
2021-03-29 0:54 ` Brad Larson
2021-03-04 9:06 ` Arnd Bergmann
2021-03-04 20:47 ` Rob Herring
2021-03-05 11:22 ` Krzysztof Kozlowski
2021-03-04 3:41 ` [PATCH 8/8] MAINTAINERS: Add entry for PENSANDO Brad Larson
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