From: Viresh Kumar <viresh.kumar@linaro.org>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pi-Cheng Chen <pi-cheng.chen@linaro.org>,
Mike Turquette <mturquette@linaro.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Henry Chen <henryc.chen@mediatek.com>,
James Liao <jamesjj.liao@mediatek.com>,
Chen Fan <fan.chen@mediatek.com>,
Eddie Huang <eddie.huang@mediatek.com>,
"Joe.C" <yingjoe.chen@mediatek.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Linaro Kernel Mailman List <linaro-kernel@lists.linaro.org>,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH] clk: mediatek: Export CPU mux clocks for CPU frequency control
Date: Thu, 5 Mar 2015 15:53:35 +0530 [thread overview]
Message-ID: <CAKohpokVxxxTY9DpQVxNPnq92pyK=2J2dDeLmis_+WD16aatOg@mail.gmail.com> (raw)
In-Reply-To: <20150305091948.GH11010@pengutronix.de>
On 5 March 2015 at 14:49, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> The sequence to change the CPU frequency on the Mediatek SoCs is like this:
>
> - Change CPU from CPU PLL to another clock source (intermediate source)
> - Change CPU PLL frequency
> - wait until PLL has settled
> - switch back to CPU PLL
This should be the case for most of the intermediate-freq users..
> The frequency of the intermediate source is irrelevant, the important
> thing is that the CPU is switched to this source while the CPU PLL is
> reconfigured.
Right.
> In Pi-Chengs patches the switch to th eintermediate clock is done like:
>
> rate = clk_get_rate(intermediate_clk);
> clk_set_rate(cpu_clk, rate);
>
> Now the clk framework does the switch not because it's told to switch
> to another parent, but only because the other parent happens to be the
> only provider for that rate. That's rubbish, when the parent must be
> changed, then it should be done explicitly.
> What if the CPU PLL and the intermediate clk happen to have the same
> rate? Then the clk_set_rate above simply does nothing, no parent is
> changed and the following rate change of the CPU PLL just crashes the
> system.
The problem is that the code is common across platforms that need to
reparent or just change rate for intermediate clocks. And the best we
can do is clk_set_rate() and so probably the clk driver need to take care
of this somehow and make sure we don't result in a crash like you just
demonstrated.
next prev parent reply other threads:[~2015-03-05 10:23 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-04 10:49 [PATCH] clk: mediatek: Export CPU mux clocks for CPU frequency control pi-cheng.chen
2015-03-04 11:21 ` Sascha Hauer
2015-03-05 2:43 ` Pi-Cheng Chen
2015-03-05 7:42 ` Sascha Hauer
2015-03-05 8:58 ` Pi-Cheng Chen
2015-03-05 8:59 ` Viresh Kumar
2015-03-05 9:19 ` Sascha Hauer
2015-03-05 9:39 ` Pi-Cheng Chen
2015-03-05 10:51 ` Sascha Hauer
2015-03-05 11:02 ` Viresh Kumar
2015-03-11 0:13 ` Mike Turquette
2015-03-12 9:21 ` Viresh Kumar
2015-03-12 10:36 ` Russell King - ARM Linux
2015-03-05 11:33 ` Pi-Cheng Chen
2015-03-05 10:23 ` Viresh Kumar [this message]
2015-03-05 10:59 ` Sascha Hauer
2015-03-10 23:59 ` Mike Turquette
2015-03-12 9:22 ` Viresh Kumar
2015-03-10 1:53 ` Pi-Cheng Chen
2015-03-10 7:55 ` Sascha Hauer
2015-03-11 7:00 ` Pi-Cheng Chen
2015-07-14 12:47 [PATCH v4] " Daniel Kurtz
2015-07-15 6:38 ` [PATCH] " Pi-Cheng Chen
2015-08-03 11:13 ` Pi-Cheng Chen
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