From: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
To: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Mike Turquette <mturquette@linaro.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>, Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Henry Chen <henryc.chen@mediatek.com>,
James Liao <jamesjj.liao@mediatek.com>,
Chen Fan <fan.chen@mediatek.com>,
Eddie Huang <eddie.huang@mediatek.com>,
"Joe.C" <yingjoe.chen@mediatek.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Linaro Kernel Mailman List <linaro-kernel@lists.linaro.org>,
linux-mediatek@lists.infradead.org,
Viresh Kumar <viresh.kumar@linaro.org>
Subject: Re: [PATCH] clk: mediatek: Export CPU mux clocks for CPU frequency control
Date: Tue, 10 Mar 2015 09:53:19 +0800 [thread overview]
Message-ID: <CALx668V4KJBmpSg3PKfXuzJsMHWgY=RCh8L=TzTC7-fEUh5HBw@mail.gmail.com> (raw)
In-Reply-To: <20150305074207.GC11010@pengutronix.de>
On 5 March 2015 at 15:42, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> +Cc Viresh Kumar
>
> Viresh, this is the patch for the underlying clocks for the Mediatek
> cpufreq driver.
>
> On Thu, Mar 05, 2015 at 10:43:21AM +0800, Pi-Cheng Chen wrote:
>> Hi Sascha,
>>
>> On 4 March 2015 at 19:21, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>> > On Wed, Mar 04, 2015 at 06:49:11PM +0800, pi-cheng.chen wrote:
>> >> This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
>> >> for intermediate clock source switching. This patch is based on Mediatek
>> >> clock driver patches[1].
>> >>
>> >> [1] http://thread.gmane.org/gmane.linux.kernel/1892436
>> >>
>> >> Signed-off-by: pi-cheng.chen <pi-cheng.chen@linaro.org>
>> >> ---
>> >> +static long clk_cpumux_determine_rate(struct clk_hw *hw, unsigned long rate,
>> >> + unsigned long min_rate,
>> >> + unsigned long max_rate,
>> >> + unsigned long *best_parent_rate,
>> >> + struct clk_hw **best_parent_p)
>> >> +{
>> >> + struct clk *clk = hw->clk, *parent;
>> >> + unsigned long parent_rate;
>> >> + int i;
>> >> +
>> >> + for (i = MAINPLL_INDEX; i >= ARMPLL_INDEX; i--) {
>> >> + parent = clk_get_parent_by_index(clk, i);
>> >> + if (!parent)
>> >> + return 0;
>> >> +
>> >> + if (i == MAINPLL_INDEX) {
>> >> + parent_rate = __clk_get_rate(parent);
>> >> + if (parent_rate == rate)
>> >> + break;
>> >> + }
>> >> +
>> >> + parent_rate = __clk_round_rate(parent, rate);
>> >> + }
>> >> +
>> >> + *best_parent_rate = parent_rate;
>> >> + *best_parent_p = __clk_get_hw(parent);
>> >> + return parent_rate;
>> >> +}
>> >
>> > Why this determine_rate hook? If you want to switch the clock to some
>> > intermediate parent I would assume you do this explicitly by setting the
>> > parent and not implicitly by setting a rate.
>> >
>>
>> I use determine_rate hook here because I am using generic cpufreq-dt
>> driver and I want to make clock switching transparent to cpufreq-dt.
>> I.e. when I am trying to switch the clock from ARMPLL to MAINPLL, I
>> call clk_set_rate() with the rate of MAINPLL, and determine_rate will
>> select MAINPLL as the new parent.
>
> We have clk_set_parent for changing the parent and clk_set_rate to
> change the rate. Use the former for changing the parent and the latter
> for changing the rate. What you are interested in is changing the
> parent, so use clk_set_parent for this and not abuse a side effect
> of clk_set_rate.
>
> My suggestion is to take another approach. Implement clk_set_rate for
> these muxes and in the set_rate hook:
>
> - switch mux to intermediate PLL parent
> - call clk_set_rate() for the real parent PLL
> - switch mux back to real parent PLL
Hi Sascha,
Thanks for your suggestion. I've tried to take this approach, but there's some
issues here.
Calling clk_set_rate() inside the set_rate callback of cpumux will cause
an infinite recursive calling in the clock framework:
mux.set_rate() -> pll.set_rate() -> mux.set_rate -> ...
I've also tries to update pll register settings in the set_rate()
callback of cpumux,
but the PLL clock information will not be correctly updated in this case.
How do you think to create a new "CPU PLL" type of clock and do underlying
mux switching in the set_rate callback of "CPU PLL"?
Best Regards,
Pi-Cheng
>
> This way the things happening behind the scenes are completely transparent
> to the cpufreq driver and you can use cpufreq-dt as is without changes.
>
> Sascha
>
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
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next prev parent reply other threads:[~2015-03-10 1:53 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-04 10:49 [PATCH] clk: mediatek: Export CPU mux clocks for CPU frequency control pi-cheng.chen
2015-03-04 11:21 ` Sascha Hauer
2015-03-05 2:43 ` Pi-Cheng Chen
2015-03-05 7:42 ` Sascha Hauer
2015-03-05 8:58 ` Pi-Cheng Chen
2015-03-05 8:59 ` Viresh Kumar
2015-03-05 9:19 ` Sascha Hauer
2015-03-05 9:39 ` Pi-Cheng Chen
2015-03-05 10:51 ` Sascha Hauer
2015-03-05 11:02 ` Viresh Kumar
2015-03-11 0:13 ` Mike Turquette
2015-03-12 9:21 ` Viresh Kumar
2015-03-12 10:36 ` Russell King - ARM Linux
2015-03-05 11:33 ` Pi-Cheng Chen
2015-03-05 10:23 ` Viresh Kumar
2015-03-05 10:59 ` Sascha Hauer
2015-03-10 23:59 ` Mike Turquette
2015-03-12 9:22 ` Viresh Kumar
2015-03-10 1:53 ` Pi-Cheng Chen [this message]
2015-03-10 7:55 ` Sascha Hauer
2015-03-11 7:00 ` Pi-Cheng Chen
2015-07-14 12:47 [PATCH v4] " Daniel Kurtz
2015-07-15 6:38 ` [PATCH] " Pi-Cheng Chen
2015-08-03 11:13 ` Pi-Cheng Chen
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