From: Andy Lutomirski <luto@kernel.org>
To: Nadav Amit <nadav.amit@gmail.com>
Cc: Andy Lutomirski <luto@kernel.org>,
Masami Hiramatsu <mhiramat@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Kees Cook <keescook@chromium.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jiri Kosina <jkosina@suse.cz>, Will Deacon <will.deacon@arm.com>,
Benjamin Herrenschmidt <benh@au1.ibm.com>,
Nick Piggin <npiggin@gmail.com>,
"the arch/x86 maintainers" <x86@kernel.org>,
Borislav Petkov <bp@alien8.de>, Rik van Riel <riel@surriel.com>,
Jann Horn <jannh@google.com>,
Adin Scannell <ascannell@google.com>,
Dave Hansen <dave.hansen@intel.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-mm <linux-mm@kvack.org>, David Miller <davem@davemloft.net>,
Martin Schwidefsky <schwidefsky@de.ibm.com>,
Michael Ellerman <mpe@ellerman.id.au>
Subject: Re: TLB flushes on fixmap changes
Date: Mon, 27 Aug 2018 15:32:02 -0700 [thread overview]
Message-ID: <CALCETrWaYgyaGcHYdvbcwXBEwHx61qbX_T99+XGD7qnRpRVGuA@mail.gmail.com> (raw)
In-Reply-To: <4F72D40A-25A3-4C64-B8DD-56970CFDE61E@gmail.com>
On Mon, Aug 27, 2018 at 2:55 PM, Nadav Amit <nadav.amit@gmail.com> wrote:
> at 1:16 PM, Nadav Amit <nadav.amit@gmail.com> wrote:
>
>> at 12:58 PM, Andy Lutomirski <luto@kernel.org> wrote:
>>
>>> On Mon, Aug 27, 2018 at 12:43 PM, Nadav Amit <nadav.amit@gmail.com> wrote:
>>>> at 12:10 PM, Nadav Amit <nadav.amit@gmail.com> wrote:
>>>>
>>>>> at 11:58 AM, Andy Lutomirski <luto@kernel.org> wrote:
>>>>>
>>>>>> On Mon, Aug 27, 2018 at 11:54 AM, Nadav Amit <nadav.amit@gmail.com> wrote:
>>>>>>>> On Mon, Aug 27, 2018 at 10:34 AM, Nadav Amit <nadav.amit@gmail.com> wrote:
>>>>>>>> What do you all think?
>>>>>>>
>>>>>>> I agree in general. But I think that current->mm would need to be loaded, as
>>>>>>> otherwise I am afraid it would break switch_mm_irqs_off().
>>>>>>
>>>>>> What breaks?
>>>>>
>>>>> Actually nothing. I just saw the IBPB stuff regarding tsk, but it should not
>>>>> matter.
>>>>
>>>> So here is what I got. It certainly needs some cleanup, but it boots.
>>>>
>>>> Let me know how crappy you find it...
>>>>
>>>>
>>>> diff --git a/arch/x86/include/asm/mmu_context.h b/arch/x86/include/asm/mmu_context.h
>>>> index bbc796eb0a3b..336779650a41 100644
>>>> --- a/arch/x86/include/asm/mmu_context.h
>>>> +++ b/arch/x86/include/asm/mmu_context.h
>>>> @@ -343,4 +343,24 @@ static inline unsigned long __get_current_cr3_fast(void)
>>>> return cr3;
>>>> }
>>>>
>>>> +typedef struct {
>>>> + struct mm_struct *prev;
>>>> +} temporary_mm_state_t;
>>>> +
>>>> +static inline temporary_mm_state_t use_temporary_mm(struct mm_struct *mm)
>>>> +{
>>>> + temporary_mm_state_t state;
>>>> +
>>>> + lockdep_assert_irqs_disabled();
>>>> + state.prev = this_cpu_read(cpu_tlbstate.loaded_mm);
>>>> + switch_mm_irqs_off(NULL, mm, current);
>>>> + return state;
>>>> +}
>>>> +
>>>> +static inline void unuse_temporary_mm(temporary_mm_state_t prev)
>>>> +{
>>>> + lockdep_assert_irqs_disabled();
>>>> + switch_mm_irqs_off(NULL, prev.prev, current);
>>>> +}
>>>> +
>>>> #endif /* _ASM_X86_MMU_CONTEXT_H */
>>>> diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
>>>> index 5715647fc4fe..ef62af9a0ef7 100644
>>>> --- a/arch/x86/include/asm/pgtable.h
>>>> +++ b/arch/x86/include/asm/pgtable.h
>>>> @@ -976,6 +976,10 @@ static inline void __meminit init_trampoline_default(void)
>>>> /* Default trampoline pgd value */
>>>> trampoline_pgd_entry = init_top_pgt[pgd_index(__PAGE_OFFSET)];
>>>> }
>>>> +
>>>> +void __init patching_mm_init(void);
>>>> +#define patching_mm_init patching_mm_init
>>>> +
>>>> # ifdef CONFIG_RANDOMIZE_MEMORY
>>>> void __meminit init_trampoline(void);
>>>> # else
>>>> diff --git a/arch/x86/include/asm/pgtable_64_types.h b/arch/x86/include/asm/pgtable_64_types.h
>>>> index 054765ab2da2..9f44262abde0 100644
>>>> --- a/arch/x86/include/asm/pgtable_64_types.h
>>>> +++ b/arch/x86/include/asm/pgtable_64_types.h
>>>> @@ -116,6 +116,9 @@ extern unsigned int ptrs_per_p4d;
>>>> #define LDT_PGD_ENTRY (pgtable_l5_enabled() ? LDT_PGD_ENTRY_L5 : LDT_PGD_ENTRY_L4)
>>>> #define LDT_BASE_ADDR (LDT_PGD_ENTRY << PGDIR_SHIFT)
>>>>
>>>> +#define TEXT_POKE_PGD_ENTRY -5UL
>>>> +#define TEXT_POKE_ADDR (TEXT_POKE_PGD_ENTRY << PGDIR_SHIFT)
>>>> +
>>>> #define __VMALLOC_BASE_L4 0xffffc90000000000UL
>>>> #define __VMALLOC_BASE_L5 0xffa0000000000000UL
>>>>
>>>> diff --git a/arch/x86/include/asm/pgtable_types.h b/arch/x86/include/asm/pgtable_types.h
>>>> index 99fff853c944..840c72ec8c4f 100644
>>>> --- a/arch/x86/include/asm/pgtable_types.h
>>>> +++ b/arch/x86/include/asm/pgtable_types.h
>>>> @@ -505,6 +505,9 @@ pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
>>>> /* Install a pte for a particular vaddr in kernel space. */
>>>> void set_pte_vaddr(unsigned long vaddr, pte_t pte);
>>>>
>>>> +struct mm_struct;
>>>> +void set_mm_pte_vaddr(struct mm_struct *mm, unsigned long vaddr, pte_t pte);
>>>> +
>>>> #ifdef CONFIG_X86_32
>>>> extern void native_pagetable_init(void);
>>>> #else
>>>> diff --git a/arch/x86/include/asm/text-patching.h b/arch/x86/include/asm/text-patching.h
>>>> index 2ecd34e2d46c..cb364ea5b19d 100644
>>>> --- a/arch/x86/include/asm/text-patching.h
>>>> +++ b/arch/x86/include/asm/text-patching.h
>>>> @@ -38,4 +38,6 @@ extern void *text_poke(void *addr, const void *opcode, size_t len);
>>>> extern int poke_int3_handler(struct pt_regs *regs);
>>>> extern void *text_poke_bp(void *addr, const void *opcode, size_t len, void *handler);
>>>>
>>>> +extern struct mm_struct *patching_mm;
>>>> +
>>>> #endif /* _ASM_X86_TEXT_PATCHING_H */
>>>> diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
>>>> index a481763a3776..fd8a950b0d62 100644
>>>> --- a/arch/x86/kernel/alternative.c
>>>> +++ b/arch/x86/kernel/alternative.c
>>>> @@ -11,6 +11,7 @@
>>>> #include <linux/stop_machine.h>
>>>> #include <linux/slab.h>
>>>> #include <linux/kdebug.h>
>>>> +#include <linux/mmu_context.h>
>>>> #include <asm/text-patching.h>
>>>> #include <asm/alternative.h>
>>>> #include <asm/sections.h>
>>>> @@ -701,8 +702,36 @@ void *text_poke(void *addr, const void *opcode, size_t len)
>>>> WARN_ON(!PageReserved(pages[0]));
>>>> pages[1] = virt_to_page(addr + PAGE_SIZE);
>>>> }
>>>> - BUG_ON(!pages[0]);
>>>> +
>>>> local_irq_save(flags);
>>>> + BUG_ON(!pages[0]);
>>>> +
>>>> + /*
>>>> + * During initial boot, it is hard to initialize patching_mm due to
>>>> + * dependencies in boot order.
>>>> + */
>>>> + if (patching_mm) {
>>>> + pte_t pte;
>>>> + temporary_mm_state_t prev;
>>>> +
>>>> + prev = use_temporary_mm(patching_mm);
>>>> + pte = mk_pte(pages[0], PAGE_KERNEL);
>>>> + set_mm_pte_vaddr(patching_mm, TEXT_POKE_ADDR, pte);
>>>> + pte = mk_pte(pages[1], PAGE_KERNEL);
>>>> + set_mm_pte_vaddr(patching_mm, TEXT_POKE_ADDR + PAGE_SIZE, pte);
>>>> +
>>>> + memcpy((void *)(TEXT_POKE_ADDR | ((unsigned long)addr & ~PAGE_MASK)),
>>>> + opcode, len);
>>>> +
>>>> + set_mm_pte_vaddr(patching_mm, TEXT_POKE_ADDR, __pte(0));
>>>> + set_mm_pte_vaddr(patching_mm, TEXT_POKE_ADDR + PAGE_SIZE, __pte(0));
>>>> + local_flush_tlb();
>>>
>>> Hmm. This is stuff busted on SMP, and it's IMO more complicated than
>>> needed. How about getting rid of all the weird TLB flushing stuff and
>>> instead putting the mapping at vaddr - __START_KERNEL_map or whatever
>>> it is? You *might* need to flush_tlb_mm_range() on module unload, but
>>> that's it.
>>
>> I don’t see what’s wrong in SMP, since this entire piece of code should be
>> running under text_mutex.
>>
>> I don’t quite understand your proposal. I really don’t want to have any
>> chance in which the page-tables for the poked address is not preallocated.
>>
>> It is more complicated than needed, and there are redundant TLB flushes. The
>> reason I preferred to do it this way, is in order not to use other functions
>> that take locks during the software page-walk and not to duplicate existing
>> code. Yet, duplication might be the way to go.
>>
>>>> + sync_core();
>>>
>>> I can't think of any case where sync_core() is needed. The mm switch
>>> serializes.
>>
>> Good point!
>>
>>> Also, is there any circumstance in which any of this is used before at
>>> least jump table init? All the early stuff is text_poke_early(),
>>> right?
>>
>> Not before jump_label_init. However, I did not manage to get rid of the two
>> code-patches in text_poke(), since text_poke is used relatively early by
>> x86_late_time_init(), and at this stage kmem_cache_alloc() - which is needed
>> to duplicate init_mm - still fails.
>
> Another correction: the populate_extra_pte() is not needed.
>
> Anyhow, if you want to do this whole thing differently, I obviously will not
> object, but I think it will end up more complicated.
>
> I think I finally understood your comment about "vaddr -
> __START_KERNEL_map”. I did something like that before, and it is not
> super-simple. You need not only to conditionally flush the TLB, but also
> to synchronize the PUD/PMD on changes. Don’t forget that module memory
> is installed even when BPF programs are installed.
>
> Let me know if you want me to submit cleaner patches or you want to carry on
> yourself.
>
I think your approach is a good start and should be good enough (with
cleanups) as a fix for the bug. But I think your code has the same
bug that we have now! You're reusing the same address on multiple
CPUs without flushing. You can easily fix it by forcing a flush
before loading the mm, which should be as simple as adding
flush_tlb_mm() before you load the mm. (It won't actually flush
anything by itself, since the mm isn't loaded, but it will update the
bookkeeping so that switch_mm_irqs_off() flushes the mm.)
Also, please at least get rid of TEXT_POKE_ADDR. If you don't want to
do the vaddr - __START_KERNEL_map thing, then at least pick an address
in the low half of the address space such as 0 :) Ideally you'd only
use this thing late enough that you could even use the normal
insert_pfn (or similar) API for it, but that doesn't really matter.
next prev parent reply other threads:[~2018-08-27 22:32 UTC|newest]
Thread overview: 96+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-22 15:30 [PATCH 0/4] x86: TLB invalidate fixes Peter Zijlstra
2018-08-22 15:30 ` [PATCH 1/4] x86/mm/tlb: Revert the recent lazy TLB patches Peter Zijlstra
2018-08-22 21:37 ` Linus Torvalds
2018-08-22 22:11 ` Rik van Riel
2018-08-22 15:30 ` [PATCH 2/4] mm/tlb: Remove tlb_remove_table() non-concurrent condition Peter Zijlstra
2018-08-23 3:31 ` Nicholas Piggin
2018-08-23 3:35 ` Linus Torvalds
2018-08-23 3:44 ` Linus Torvalds
2018-08-23 4:16 ` Nicholas Piggin
2018-08-23 4:54 ` Linus Torvalds
2018-08-23 5:15 ` Nicholas Piggin
2018-08-24 8:42 ` Peter Zijlstra
2018-08-23 13:40 ` Will Deacon
2018-08-22 15:30 ` [PATCH 3/4] mm/tlb, x86/mm: Support invalidating TLB caches for RCU_TABLE_FREE Peter Zijlstra
2018-08-22 15:55 ` Peter Zijlstra
2018-08-23 3:45 ` Nicholas Piggin
2018-08-23 3:59 ` Linus Torvalds
2018-08-23 4:33 ` Nicholas Piggin
2018-08-23 5:03 ` Linus Torvalds
2018-08-23 5:58 ` Nicholas Piggin
2018-08-23 4:54 ` Benjamin Herrenschmidt
2018-08-23 5:11 ` Linus Torvalds
2018-08-23 5:20 ` Linus Torvalds
2018-08-23 6:48 ` Martin Schwidefsky
2018-08-23 5:21 ` Benjamin Herrenschmidt
2018-08-23 6:15 ` Nicholas Piggin
2018-08-23 13:39 ` Will Deacon
2018-08-24 8:47 ` Peter Zijlstra
2018-08-24 11:32 ` Peter Zijlstra
2018-08-24 11:39 ` Peter Zijlstra
2018-08-27 5:00 ` Nicholas Piggin
2018-08-27 7:47 ` Peter Zijlstra
2018-08-27 8:04 ` Nicholas Piggin
2018-08-27 8:09 ` Benjamin Herrenschmidt
2018-08-27 8:20 ` Peter Zijlstra
2018-08-27 8:54 ` Nicholas Piggin
2018-08-27 9:02 ` Nicholas Piggin
2018-08-27 22:13 ` Benjamin Herrenschmidt
2018-08-27 13:36 ` Rik van Riel
2018-08-27 14:29 ` Nicholas Piggin
2018-08-27 8:57 ` removig ia64, was: " Christoph Hellwig
2018-08-27 11:28 ` Peter Zijlstra
2018-08-27 11:45 ` Jason Duerstock
2018-08-27 11:00 ` Peter Zijlstra
2018-08-30 0:13 ` Vineet Gupta
2018-08-30 10:23 ` Peter Zijlstra
2018-08-24 17:26 ` Nadav Amit
2018-08-24 18:04 ` Peter Zijlstra
2018-08-24 18:35 ` TLB flushes on fixmap changes Nadav Amit
2018-08-24 19:31 ` Linus Torvalds
2018-08-24 20:24 ` Nadav Amit
2018-08-25 0:58 ` Linus Torvalds
2018-08-25 2:29 ` nadav.amit
2018-08-25 4:23 ` Andy Lutomirski
2018-08-26 2:23 ` Masami Hiramatsu
2018-08-26 4:21 ` Andy Lutomirski
2018-08-26 4:43 ` Kees Cook
2018-08-26 5:53 ` Nadav Amit
2018-08-26 14:20 ` Andy Lutomirski
2018-08-26 16:47 ` Kees Cook
2018-08-26 17:25 ` Andy Lutomirski
2018-08-26 20:15 ` Thomas Gleixner
2018-08-26 22:03 ` Kees Cook
2018-08-26 22:15 ` Matthew Wilcox
2018-08-26 22:29 ` Jann Horn
2018-08-26 9:09 ` Peter Zijlstra
2018-08-27 3:03 ` Masami Hiramatsu
2018-08-27 3:26 ` Nadav Amit
2018-08-27 8:05 ` Masami Hiramatsu
2018-08-27 17:34 ` Nadav Amit
2018-08-27 18:45 ` Andy Lutomirski
2018-08-27 18:54 ` Nadav Amit
2018-08-27 18:58 ` Andy Lutomirski
2018-08-27 19:10 ` Nadav Amit
2018-08-27 19:43 ` Nadav Amit
2018-08-27 19:58 ` Andy Lutomirski
2018-08-27 20:16 ` Nadav Amit
2018-08-27 21:55 ` Nadav Amit
2018-08-27 22:32 ` Andy Lutomirski [this message]
2018-08-27 22:54 ` Nadav Amit
2018-08-27 23:01 ` Andy Lutomirski
2018-08-28 8:49 ` Masami Hiramatsu
2018-08-28 17:33 ` Nadav Amit
2018-08-27 8:13 ` Peter Zijlstra
2018-08-27 9:39 ` Masami Hiramatsu
2018-08-27 9:55 ` Jann Horn
2018-08-26 22:48 ` Jann Horn
2018-08-24 8:35 ` [PATCH 3/4] mm/tlb, x86/mm: Support invalidating TLB caches for RCU_TABLE_FREE Peter Zijlstra
2018-08-24 13:13 ` Peter Zijlstra
2018-08-24 13:14 ` Peter Zijlstra
2018-08-24 15:49 ` Will Deacon
2018-08-23 23:31 ` Will Deacon
2018-08-22 21:34 ` Linus Torvalds
2018-08-23 8:46 ` Nicholas Piggin
2018-08-22 15:30 ` [PATCH 4/4] x86/mm: Only use tlb_remove_table() for paravirt Peter Zijlstra
2018-08-22 22:12 ` Eduardo Valentin
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