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From: Dan Streetman <ddstreet@ieee.org>
To: Keith Busch <keith.busch@intel.com>
Cc: Jens Axboe <axboe@fb.com>,
	linux-nvme@lists.infradead.org,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Dan Streetman <dan.streetman@canonical.com>
Subject: Re: [PATCH] nvme: use the correct msix vector for each queue
Date: Wed, 7 Dec 2016 17:46:34 -0500	[thread overview]
Message-ID: <CALZtONAyqjK4RG0PAJJczzHkZrhzpvT2v9eUu3yXs949-Q51dg@mail.gmail.com> (raw)
In-Reply-To: <20161207224941.GA25959@localhost.localdomain>

On Wed, Dec 7, 2016 at 5:49 PM, Keith Busch <keith.busch@intel.com> wrote:
> On Wed, Dec 07, 2016 at 05:36:00PM -0500, Dan Streetman wrote:
>> On Wed, Dec 7, 2016 at 5:44 PM, Keith Busch <keith.busch@intel.com> wrote:
>> > pci_alloc_irq_vectors doesn't know you intend to make the first
>> > vector special, so it's going to come up with a CPU affinity from
>> > blk_mq_pci_map_queues that clashes with what you've programmed in the
>> > IO completion queues.
>>
>> I don't follow.  You're saying you mean to share cq_vector 0 between
>> the admin queue and io queue 1?
>
> I'm just saying that blk-mq's hctx mapping will end up choosing a queue
> who's vector is mapped to a different CPU, and we don't want that.
>
> We are currently sharing the first IO queue's interrupt vector with
> the admin queue's on purpose. Are you saying there's something wrong
> with that?

that's intentional?  Ok then.  That's extremely non-obvious.

Is there a reason you want to share the interrupt between the queues?

  parent reply	other threads:[~2016-12-07 22:47 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-07 22:03 [PATCH] nvme: use the correct msix vector for each queue Dan Streetman
2016-12-07 22:44 ` Keith Busch
2016-12-07 22:36   ` Dan Streetman
2016-12-07 22:49     ` Keith Busch
2016-12-07 22:46       ` Christoph Hellwig
2016-12-07 22:49         ` Dan Streetman
2016-12-07 22:46       ` Dan Streetman [this message]
2016-12-07 23:05         ` Keith Busch

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