* [PATCH v5 1/6] PCI: OF: Don't remap iospace on unsupported platform
2020-04-24 13:08 [PATCH v5 0/6] Loongson PCI Generic Driver Jiaxun Yang
@ 2020-04-24 13:08 ` Jiaxun Yang
2020-04-24 17:47 ` Rob Herring
2020-04-24 13:08 ` [PATCH v5 2/6] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
` (4 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Jiaxun Yang @ 2020-04-24 13:08 UTC (permalink / raw)
To: linux-pci
Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
Huacai Chen, Lorenzo Pieralisi, Andrew Murray, Paul Burton,
devicetree, linux-kernel, linux-mips
There are some platforms that don't support I/O space remapping
like MIPS. However, our PCI code will try to remap iospace
unconditionally and reject io resources on these platforms.
So we should remove I/O space remapping check and use a range
check instead on these platforms.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
--
v4: Fix a typo in commit message.
v5: Commit message massage
---
drivers/pci/of.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index 81ceeaa6f1d5..36e8761b66c6 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -547,12 +547,21 @@ int pci_parse_request_of_pci_ranges(struct device *dev,
switch (resource_type(res)) {
case IORESOURCE_IO:
+#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
err = devm_pci_remap_iospace(dev, res, iobase);
if (err) {
dev_warn(dev, "error %d: failed to map resource %pR\n",
err, res);
resource_list_destroy_entry(win);
}
+#else
+ /* Simply check if IO is inside the range */
+ if (res->end > IO_SPACE_LIMIT) {
+ dev_warn(dev, "resource %pR out of the I/O range\n",
+ res);
+ resource_list_destroy_entry(win);
+ }
+#endif
break;
case IORESOURCE_MEM:
res_valid |= !(res->flags & IORESOURCE_PREFETCH);
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v5 1/6] PCI: OF: Don't remap iospace on unsupported platform
2020-04-24 13:08 ` [PATCH v5 1/6] PCI: OF: Don't remap iospace on unsupported platform Jiaxun Yang
@ 2020-04-24 17:47 ` Rob Herring
2020-04-24 18:03 ` Jiaxun Yang
0 siblings, 1 reply; 13+ messages in thread
From: Rob Herring @ 2020-04-24 17:47 UTC (permalink / raw)
To: Jiaxun Yang
Cc: PCI, Bjorn Helgaas, Thomas Bogendoerfer, Huacai Chen,
Lorenzo Pieralisi, Andrew Murray, Paul Burton, devicetree,
linux-kernel, open list:MIPS
On Fri, Apr 24, 2020 at 8:09 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> There are some platforms that don't support I/O space remapping
> like MIPS. However, our PCI code will try to remap iospace
> unconditionally and reject io resources on these platforms.
>
> So we should remove I/O space remapping check and use a range
> check instead on these platforms.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> --
> v4: Fix a typo in commit message.
> v5: Commit message massage
> ---
> drivers/pci/of.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> index 81ceeaa6f1d5..36e8761b66c6 100644
> --- a/drivers/pci/of.c
> +++ b/drivers/pci/of.c
> @@ -547,12 +547,21 @@ int pci_parse_request_of_pci_ranges(struct device *dev,
>
> switch (resource_type(res)) {
> case IORESOURCE_IO:
> +#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
We already have the same condition in pci_remap_iospace(). All this
does is suppress a WARN. If a WARN is not desired, then change it.
Perhaps just a single line rather than backtrace would be okay.
Whether to WARN or not shouldn't be a decision for firmware code.
Though really, if I/O space can never be supported, then it's an error
in your DT to describe it.
> err = devm_pci_remap_iospace(dev, res, iobase);
> if (err) {
> dev_warn(dev, "error %d: failed to map resource %pR\n",
> err, res);
> resource_list_destroy_entry(win);
> }
> +#else
> + /* Simply check if IO is inside the range */
Why do you care if it's never used?
> + if (res->end > IO_SPACE_LIMIT) {
> + dev_warn(dev, "resource %pR out of the I/O range\n",
> + res);
> + resource_list_destroy_entry(win);
> + }
> +#endif
> break;
> case IORESOURCE_MEM:
> res_valid |= !(res->flags & IORESOURCE_PREFETCH);
> --
> 2.26.0.rc2
>
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v5 1/6] PCI: OF: Don't remap iospace on unsupported platform
2020-04-24 17:47 ` Rob Herring
@ 2020-04-24 18:03 ` Jiaxun Yang
2020-04-24 19:05 ` Rob Herring
0 siblings, 1 reply; 13+ messages in thread
From: Jiaxun Yang @ 2020-04-24 18:03 UTC (permalink / raw)
To: Rob Herring
Cc: PCI, Bjorn Helgaas, Thomas Bogendoerfer, Huacai Chen,
Lorenzo Pieralisi, Andrew Murray, Paul Burton, devicetree,
linux-kernel, open list:MIPS
于 2020年4月25日 GMT+08:00 上午1:47:23, Rob Herring <robh+dt@kernel.org> 写到:
>On Fri, Apr 24, 2020 at 8:09 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>>
>> There are some platforms that don't support I/O space remapping
>> like MIPS. However, our PCI code will try to remap iospace
>> unconditionally and reject io resources on these platforms.
>>
>> So we should remove I/O space remapping check and use a range
>> check instead on these platforms.
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> --
>> v4: Fix a typo in commit message.
>> v5: Commit message massage
>> ---
>> drivers/pci/of.c | 9 +++++++++
>> 1 file changed, 9 insertions(+)
>>
>> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
>> index 81ceeaa6f1d5..36e8761b66c6 100644
>> --- a/drivers/pci/of.c
>> +++ b/drivers/pci/of.c
>> @@ -547,12 +547,21 @@ int pci_parse_request_of_pci_ranges(struct device *dev,
>>
>> switch (resource_type(res)) {
>> case IORESOURCE_IO:
>> +#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
>
>We already have the same condition in pci_remap_iospace(). All this
>does is suppress a WARN. If a WARN is not desired, then change it.
>Perhaps just a single line rather than backtrace would be okay.
>Whether to WARN or not shouldn't be a decision for firmware code.
>
>Though really, if I/O space can never be supported, then it's an error
>in your DT to describe it.
In MIPS world, we do have inb/oub family of I/O functions
to support I/O space. But we're not using remap_iospace as it's breaking
some of our assumptions.
We have our own inb/outb implementation.
In that case, I think make a range check instead of remapping would
be more practical.
Thanks.
>
>> err = devm_pci_remap_iospace(dev, res, iobase);
>> if (err) {
>> dev_warn(dev, "error %d: failed to map resource %pR\n",
>> err, res);
>> resource_list_destroy_entry(win);
>> }
>> +#else
>> + /* Simply check if IO is inside the range */
>
>Why do you care if it's never used?
>
>> + if (res->end > IO_SPACE_LIMIT) {
>> + dev_warn(dev, "resource %pR out of the I/O range\n",
>> + res);
>> + resource_list_destroy_entry(win);
>> + }
>> +#endif
>> break;
>> case IORESOURCE_MEM:
>> res_valid |= !(res->flags & IORESOURCE_PREFETCH);
>> --
>> 2.26.0.rc2
>>
--
Jiaxun Yang
^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH v5 1/6] PCI: OF: Don't remap iospace on unsupported platform
2020-04-24 18:03 ` Jiaxun Yang
@ 2020-04-24 19:05 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-04-24 19:05 UTC (permalink / raw)
To: Jiaxun Yang
Cc: PCI, Bjorn Helgaas, Thomas Bogendoerfer, Huacai Chen,
Lorenzo Pieralisi, Andrew Murray, Paul Burton, devicetree,
linux-kernel, open list:MIPS
On Fri, Apr 24, 2020 at 1:03 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
>
>
> 于 2020年4月25日 GMT+08:00 上午1:47:23, Rob Herring <robh+dt@kernel.org> 写到:
> >On Fri, Apr 24, 2020 at 8:09 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> >>
> >> There are some platforms that don't support I/O space remapping
> >> like MIPS. However, our PCI code will try to remap iospace
> >> unconditionally and reject io resources on these platforms.
> >>
> >> So we should remove I/O space remapping check and use a range
> >> check instead on these platforms.
> >>
> >> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >> --
> >> v4: Fix a typo in commit message.
> >> v5: Commit message massage
> >> ---
> >> drivers/pci/of.c | 9 +++++++++
> >> 1 file changed, 9 insertions(+)
> >>
> >> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> >> index 81ceeaa6f1d5..36e8761b66c6 100644
> >> --- a/drivers/pci/of.c
> >> +++ b/drivers/pci/of.c
> >> @@ -547,12 +547,21 @@ int pci_parse_request_of_pci_ranges(struct device *dev,
> >>
> >> switch (resource_type(res)) {
> >> case IORESOURCE_IO:
> >> +#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
> >
> >We already have the same condition in pci_remap_iospace(). All this
> >does is suppress a WARN. If a WARN is not desired, then change it.
> >Perhaps just a single line rather than backtrace would be okay.
> >Whether to WARN or not shouldn't be a decision for firmware code.
> >
> >Though really, if I/O space can never be supported, then it's an error
> >in your DT to describe it.
>
> In MIPS world, we do have inb/oub family of I/O functions
> to support I/O space. But we're not using remap_iospace as it's breaking
> some of our assumptions.
I suspect that's largely because most MIPS drivers pre-date the common
iospace handling. Really MIPS should start using this.
> We have our own inb/outb implementation.
That's orthogonal to mapping the iospace.
> In that case, I think make a range check instead of remapping would
> be more practical.
Not the kernel's job to validate the DT especially if you aren't using
this data anywhere.
Just remove the WARN, make it a single line print, or add
!IS_ENABLED(CONFIG_MIPS) where the warning is.
Rob
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 2/6] PCI: Don't disable decoding when mmio_always_on is set
2020-04-24 13:08 [PATCH v5 0/6] Loongson PCI Generic Driver Jiaxun Yang
2020-04-24 13:08 ` [PATCH v5 1/6] PCI: OF: Don't remap iospace on unsupported platform Jiaxun Yang
@ 2020-04-24 13:08 ` Jiaxun Yang
2020-04-24 13:08 ` [PATCH v5 3/6] PCI: Add Loongson PCI Controller support Jiaxun Yang
` (3 subsequent siblings)
5 siblings, 0 replies; 13+ messages in thread
From: Jiaxun Yang @ 2020-04-24 13:08 UTC (permalink / raw)
To: linux-pci
Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
Huacai Chen, Lorenzo Pieralisi, Andrew Murray, Paul Burton,
devicetree, linux-kernel, linux-mips
Don't disable MEM/IO decoing when a device have both non_compliant_bars
and mmio_always_on.
That would allow us quirk devices with junk in BARs but can't disable
their decoding.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
drivers/pci/probe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 77b8a145c39b..d9c2c3301a8a 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1822,7 +1822,7 @@ int pci_setup_device(struct pci_dev *dev)
/* Device class may be changed after fixup */
class = dev->class >> 8;
- if (dev->non_compliant_bars) {
+ if (dev->non_compliant_bars && !dev->mmio_always_on) {
pci_read_config_word(dev, PCI_COMMAND, &cmd);
if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH v5 3/6] PCI: Add Loongson PCI Controller support
2020-04-24 13:08 [PATCH v5 0/6] Loongson PCI Generic Driver Jiaxun Yang
2020-04-24 13:08 ` [PATCH v5 1/6] PCI: OF: Don't remap iospace on unsupported platform Jiaxun Yang
2020-04-24 13:08 ` [PATCH v5 2/6] PCI: Don't disable decoding when mmio_always_on is set Jiaxun Yang
@ 2020-04-24 13:08 ` Jiaxun Yang
2020-04-24 18:22 ` Rob Herring
2020-04-24 13:08 ` [PATCH v5 4/6] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
` (2 subsequent siblings)
5 siblings, 1 reply; 13+ messages in thread
From: Jiaxun Yang @ 2020-04-24 13:08 UTC (permalink / raw)
To: linux-pci
Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
Huacai Chen, Lorenzo Pieralisi, Andrew Murray, Paul Burton,
devicetree, linux-kernel, linux-mips
This controller can be found on Loongson-2K SoC, Loongson-3
systems with RS780E/LS7A PCH.
The RS780E part of code was previously located at
arch/mips/pci/ops-loongson3.c and now it can use generic PCI
driver implementation.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
--
v2:
- Clean up according to rob's suggestions
- Claim that it can't work as a module
v3:
- Fix a typo
---
drivers/pci/controller/Kconfig | 9 +
drivers/pci/controller/Makefile | 1 +
drivers/pci/controller/pci-loongson.c | 257 ++++++++++++++++++++++++++
3 files changed, 267 insertions(+)
create mode 100644 drivers/pci/controller/pci-loongson.c
diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 91bfdb784829..7d7e70402ebd 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
The Hyper-V PCI Interface is a helper driver allows other drivers to
have a common interface with the Hyper-V PCI frontend driver.
+config PCI_LOONGSON
+ bool "LOONGSON PCI Controller"
+ depends on MACH_LOONGSON64 || COMPILE_TEST
+ depends on OF
+ depends on PCI_QUIRKS
+ default MACH_LOONGSON64
+ help
+ Say Y here if you want to enable PCI controller support on
+ Loongson systems.
+
source "drivers/pci/controller/dwc/Kconfig"
source "drivers/pci/controller/mobiveil/Kconfig"
source "drivers/pci/controller/cadence/Kconfig"
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index 158c59771824..fbac4b0190a0 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
obj-$(CONFIG_VMD) += vmd.o
obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
+obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
obj-y += dwc/
obj-y += mobiveil/
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
new file mode 100644
index 000000000000..0bd3b52c14fb
--- /dev/null
+++ b/drivers/pci/controller/pci-loongson.c
@@ -0,0 +1,257 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Loongson PCI Host Controller Driver
+ *
+ * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
+ */
+
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+
+#include "../pci.h"
+
+/* Device IDs */
+#define DEV_PCIE_PORT_0 0x7a09
+#define DEV_PCIE_PORT_1 0x7a19
+#define DEV_PCIE_PORT_2 0x7a29
+
+#define DEV_LS2K_APB 0x7a02
+#define DEV_LS7A_CONF 0x7a10
+#define DEV_LS7A_LPC 0x7a0c
+
+#define FLAG_CFG0 BIT(0)
+#define FLAG_CFG1 BIT(1)
+#define FLAG_DEV_FIX BIT(2)
+
+struct loongson_pci {
+ void __iomem *cfg0_base;
+ void __iomem *cfg1_base;
+ struct platform_device *pdev;
+ u32 flags;
+};
+
+/* Fixup wrong class code in PCIe bridges */
+static void bridge_class_quirk(struct pci_dev *dev)
+{
+ dev->class = PCI_CLASS_BRIDGE_PCI << 8;
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_0, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_1, bridge_class_quirk);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
+ DEV_PCIE_PORT_2, bridge_class_quirk);
+
+static void system_bus_quirk(struct pci_dev *pdev)
+{
+ u16 tmp;
+
+ pdev->mmio_always_on = 1;
+ pdev->non_compliant_bars = 1;
+ /* Enable MEM & IO Decoding */
+ pci_read_config_word(pdev, PCI_STATUS, &tmp);
+ tmp |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+ pci_write_config_word(pdev, PCI_STATUS, tmp);
+}
+
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS2K_APB, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_CONF, system_bus_quirk);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
+ DEV_LS7A_LPC, system_bus_quirk);
+
+static void loongson_mrrs_quirk(struct pci_dev *dev)
+{
+ struct pci_bus *bus = dev->bus;
+ struct pci_dev *bridge;
+ static const struct pci_device_id bridge_devids[] = {
+ { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
+ { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
+ { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
+ { 0, },
+ };
+
+
+ /* look for the matching bridge */
+ while (!pci_is_root_bus(bus)) {
+ bridge = bus->self;
+ bus = bus->parent;
+ /*
+ * Some Loongson PCIE ports has a h/w limitation of
+ * 256 bytes maximum read request size. It can't handle
+ * anything higher than this. So force this limit on
+ * any devices attached under these ports.
+ */
+ if (pci_match_id(bridge_devids, bridge)) {
+ if (pcie_get_readrq(dev) > 256) {
+ dev_info(&dev->dev, "limiting MRRS to 256\n");
+ pcie_set_readrq(dev, 256);
+ }
+ break;
+ }
+ }
+}
+DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
+
+static void __iomem *cfg1_map(struct loongson_pci *priv, int bus, int dev,
+ int func, int where)
+{
+ unsigned long addroff = 0x0;
+
+ if (bus != 0)
+ addroff |= BIT(28); /* Type 1 Access */
+ addroff |= (where & 0xff) | ((where & 0xf00) << 16);
+ addroff |= (bus << 16) | (dev << 11) | (func << 8);
+ return priv->cfg1_base + addroff;
+}
+
+static void __iomem *cfg0_map(struct loongson_pci *priv, int bus, int dev,
+ int func, int where)
+{
+ unsigned long addroff = 0x0;
+
+ if (bus != 0)
+ addroff |= BIT(24); /* Type 1 Access */
+ addroff |= (bus << 16) | (dev << 11) | (func << 8) | where;
+ return priv->cfg0_base + addroff;
+}
+
+void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
+ int where)
+{
+ unsigned char busnum = bus->number;
+ int device = PCI_SLOT(devfn);
+ int function = PCI_FUNC(devfn);
+ struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
+ struct loongson_pci *priv = pci_host_bridge_priv(bridge);
+
+ /*
+ * Do not read more than one device on the bus other than
+ * the host bridge.
+ */
+ if (bus->primary != 0 && device > 0 &&
+ priv->flags & FLAG_DEV_FIX)
+ return NULL;
+
+ /* CFG0 can only access standard space */
+ if (where < PCI_CFG_SPACE_SIZE && priv->flags & FLAG_CFG0 &&
+ priv->cfg0_base)
+ return cfg0_map(priv, busnum, device, function, where);
+
+ /* CFG1 can access exp space */
+ if (where < PCI_CFG_SPACE_EXP_SIZE && priv->flags & FLAG_CFG1 &&
+ priv->cfg1_base)
+ return cfg1_map(priv, busnum, device, function, where);
+
+ return NULL;
+}
+
+static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+ int irq;
+ u8 val;
+
+ irq = of_irq_parse_and_map_pci(dev, slot, pin);
+ if (irq > 0)
+ return irq;
+
+ /* Care i8259 legacy systems */
+ pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
+ /* 0xff is also invalid */
+ if (val == 0xff)
+ return 0;
+
+ return val;
+}
+
+/* H/w only accept 32-bit PCI operations */
+static struct pci_ops loongson_pci_ops = {
+ .map_bus = pci_loongson_map_bus,
+ .read = pci_generic_config_read32,
+ .write = pci_generic_config_write32,
+};
+
+static const struct of_device_id loongson_pci_of_match[] = {
+ { .compatible = "loongson,rs780e-pci",
+ .data = (void *)(FLAG_CFG0), },
+ { .compatible = "loongson,ls2k-pci",
+ .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+ { .compatible = "loongson,ls7a-pci",
+ .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
+ {}
+};
+
+static int loongson_pci_probe(struct platform_device *pdev)
+{
+ struct loongson_pci *priv;
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ struct pci_host_bridge *bridge;
+ struct resource *regs;
+ int err;
+
+ if (!node)
+ return -ENODEV;
+
+ bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
+ if (!bridge)
+ return -ENODEV;
+
+ priv = pci_host_bridge_priv(bridge);
+ priv->pdev = pdev;
+ priv->flags = (unsigned long)of_device_get_match_data(dev);
+
+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!regs) {
+ dev_err(dev, "missing mem resources for cfg0\n");
+ return -EINVAL;
+ }
+
+ priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
+ if (IS_ERR(priv->cfg0_base))
+ return PTR_ERR(priv->cfg0_base);
+
+ /* CFG1 is optional */
+ if (priv->flags & FLAG_CFG1) {
+ regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (!regs)
+ dev_info(dev, "missing mem resource for cfg1\n");
+ else {
+ priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
+ if (IS_ERR(priv->cfg1_base))
+ priv->cfg1_base = NULL;
+ }
+ }
+
+
+ err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
+ &bridge->dma_ranges, NULL);
+ if (err) {
+ dev_err(dev, "Failed to get bridge resources\n");
+ return err;
+ }
+
+ bridge->dev.parent = dev;
+ bridge->sysdata = priv;
+ bridge->ops = &loongson_pci_ops;
+ bridge->map_irq = loongson_map_irq;
+
+ err = pci_host_probe(bridge);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+static struct platform_driver loongson_pci_driver = {
+ .driver = {
+ .name = "loongson-pci",
+ .of_match_table = loongson_pci_of_match,
+ },
+ .probe = loongson_pci_probe,
+};
+builtin_platform_driver(loongson_pci_driver);
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v5 3/6] PCI: Add Loongson PCI Controller support
2020-04-24 13:08 ` [PATCH v5 3/6] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-04-24 18:22 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-04-24 18:22 UTC (permalink / raw)
To: Jiaxun Yang
Cc: PCI, Bjorn Helgaas, Thomas Bogendoerfer, Huacai Chen,
Lorenzo Pieralisi, Andrew Murray, Paul Burton, devicetree,
linux-kernel, open list:MIPS
On Fri, Apr 24, 2020 at 8:10 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> This controller can be found on Loongson-2K SoC, Loongson-3
> systems with RS780E/LS7A PCH.
>
> The RS780E part of code was previously located at
> arch/mips/pci/ops-loongson3.c and now it can use generic PCI
> driver implementation.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> --
> v2:
> - Clean up according to rob's suggestions
> - Claim that it can't work as a module
> v3:
> - Fix a typo
> ---
> drivers/pci/controller/Kconfig | 9 +
> drivers/pci/controller/Makefile | 1 +
> drivers/pci/controller/pci-loongson.c | 257 ++++++++++++++++++++++++++
> 3 files changed, 267 insertions(+)
> create mode 100644 drivers/pci/controller/pci-loongson.c
>
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index 91bfdb784829..7d7e70402ebd 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -258,6 +258,16 @@ config PCI_HYPERV_INTERFACE
> The Hyper-V PCI Interface is a helper driver allows other drivers to
> have a common interface with the Hyper-V PCI frontend driver.
>
> +config PCI_LOONGSON
> + bool "LOONGSON PCI Controller"
> + depends on MACH_LOONGSON64 || COMPILE_TEST
> + depends on OF
> + depends on PCI_QUIRKS
> + default MACH_LOONGSON64
> + help
> + Say Y here if you want to enable PCI controller support on
> + Loongson systems.
> +
> source "drivers/pci/controller/dwc/Kconfig"
> source "drivers/pci/controller/mobiveil/Kconfig"
> source "drivers/pci/controller/cadence/Kconfig"
> diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
> index 158c59771824..fbac4b0190a0 100644
> --- a/drivers/pci/controller/Makefile
> +++ b/drivers/pci/controller/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
> obj-$(CONFIG_VMD) += vmd.o
> obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
> +obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
> # pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
> obj-y += dwc/
> obj-y += mobiveil/
> diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c
> new file mode 100644
> index 000000000000..0bd3b52c14fb
> --- /dev/null
> +++ b/drivers/pci/controller/pci-loongson.c
> @@ -0,0 +1,257 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Loongson PCI Host Controller Driver
> + *
> + * Copyright (C) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com>
> + */
> +
> +#include <linux/of_address.h>
Don't think this is needed.
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
This should be of_device.h instead.
> +#include <linux/pci.h>
> +#include <linux/pci_ids.h>
> +
> +#include "../pci.h"
> +
> +/* Device IDs */
> +#define DEV_PCIE_PORT_0 0x7a09
> +#define DEV_PCIE_PORT_1 0x7a19
> +#define DEV_PCIE_PORT_2 0x7a29
> +
> +#define DEV_LS2K_APB 0x7a02
> +#define DEV_LS7A_CONF 0x7a10
> +#define DEV_LS7A_LPC 0x7a0c
> +
> +#define FLAG_CFG0 BIT(0)
> +#define FLAG_CFG1 BIT(1)
> +#define FLAG_DEV_FIX BIT(2)
> +
> +struct loongson_pci {
> + void __iomem *cfg0_base;
> + void __iomem *cfg1_base;
> + struct platform_device *pdev;
> + u32 flags;
> +};
> +
> +/* Fixup wrong class code in PCIe bridges */
> +static void bridge_class_quirk(struct pci_dev *dev)
> +{
> + dev->class = PCI_CLASS_BRIDGE_PCI << 8;
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> + DEV_PCIE_PORT_0, bridge_class_quirk);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> + DEV_PCIE_PORT_1, bridge_class_quirk);
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_LOONGSON,
> + DEV_PCIE_PORT_2, bridge_class_quirk);
> +
> +static void system_bus_quirk(struct pci_dev *pdev)
> +{
> + u16 tmp;
> +
> + pdev->mmio_always_on = 1;
> + pdev->non_compliant_bars = 1;
> + /* Enable MEM & IO Decoding */
> + pci_read_config_word(pdev, PCI_STATUS, &tmp);
> + tmp |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
> + pci_write_config_word(pdev, PCI_STATUS, tmp);
> +}
> +
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> + DEV_LS2K_APB, system_bus_quirk);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> + DEV_LS7A_CONF, system_bus_quirk);
> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON,
> + DEV_LS7A_LPC, system_bus_quirk);
> +
> +static void loongson_mrrs_quirk(struct pci_dev *dev)
> +{
> + struct pci_bus *bus = dev->bus;
> + struct pci_dev *bridge;
> + static const struct pci_device_id bridge_devids[] = {
> + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_0) },
> + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_1) },
> + { PCI_VDEVICE(LOONGSON, DEV_PCIE_PORT_2) },
> + { 0, },
> + };
> +
> +
> + /* look for the matching bridge */
> + while (!pci_is_root_bus(bus)) {
> + bridge = bus->self;
> + bus = bus->parent;
> + /*
> + * Some Loongson PCIE ports has a h/w limitation of
> + * 256 bytes maximum read request size. It can't handle
> + * anything higher than this. So force this limit on
> + * any devices attached under these ports.
> + */
> + if (pci_match_id(bridge_devids, bridge)) {
> + if (pcie_get_readrq(dev) > 256) {
> + dev_info(&dev->dev, "limiting MRRS to 256\n");
> + pcie_set_readrq(dev, 256);
> + }
> + break;
> + }
> + }
> +}
> +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_mrrs_quirk);
> +
> +static void __iomem *cfg1_map(struct loongson_pci *priv, int bus, int dev,
> + int func, int where)
> +{
> + unsigned long addroff = 0x0;
> +
> + if (bus != 0)
> + addroff |= BIT(28); /* Type 1 Access */
> + addroff |= (where & 0xff) | ((where & 0xf00) << 16);
> + addroff |= (bus << 16) | (dev << 11) | (func << 8);
You already had 'devfn', so just pass that in here and use it.
> + return priv->cfg1_base + addroff;
> +}
> +
> +static void __iomem *cfg0_map(struct loongson_pci *priv, int bus, int dev,
> + int func, int where)
> +{
> + unsigned long addroff = 0x0;
> +
> + if (bus != 0)
> + addroff |= BIT(24); /* Type 1 Access */
> + addroff |= (bus << 16) | (dev << 11) | (func << 8) | where;
And here.
> + return priv->cfg0_base + addroff;
> +}
> +
> +void __iomem *pci_loongson_map_bus(struct pci_bus *bus, unsigned int devfn,
> + int where)
> +{
> + unsigned char busnum = bus->number;
> + int device = PCI_SLOT(devfn);
> + int function = PCI_FUNC(devfn);
> + struct pci_host_bridge *bridge = pci_find_host_bridge(bus);
> + struct loongson_pci *priv = pci_host_bridge_priv(bridge);
> +
> + /*
> + * Do not read more than one device on the bus other than
> + * the host bridge.
> + */
> + if (bus->primary != 0 && device > 0 &&
> + priv->flags & FLAG_DEV_FIX)
> + return NULL;
> +
> + /* CFG0 can only access standard space */
> + if (where < PCI_CFG_SPACE_SIZE && priv->flags & FLAG_CFG0 &&
> + priv->cfg0_base)
> + return cfg0_map(priv, busnum, device, function, where);
> +
> + /* CFG1 can access exp space */
> + if (where < PCI_CFG_SPACE_EXP_SIZE && priv->flags & FLAG_CFG1 &&
> + priv->cfg1_base)
No need to check both priv->cfg1_base and FLAG_CFG1. I'd drop the flag.
> + return cfg1_map(priv, busnum, device, function, where);
> +
> + return NULL;
> +}
> +
> +static int loongson_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> +{
> + int irq;
> + u8 val;
> +
> + irq = of_irq_parse_and_map_pci(dev, slot, pin);
> + if (irq > 0)
> + return irq;
> +
> + /* Care i8259 legacy systems */
> + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &val);
> + /* 0xff is also invalid */
> + if (val == 0xff)
> + return 0;
> +
> + return val;
> +}
> +
> +/* H/w only accept 32-bit PCI operations */
> +static struct pci_ops loongson_pci_ops = {
> + .map_bus = pci_loongson_map_bus,
> + .read = pci_generic_config_read32,
> + .write = pci_generic_config_write32,
> +};
> +
> +static const struct of_device_id loongson_pci_of_match[] = {
> + { .compatible = "loongson,rs780e-pci",
> + .data = (void *)(FLAG_CFG0), },
> + { .compatible = "loongson,ls2k-pci",
> + .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
> + { .compatible = "loongson,ls7a-pci",
> + .data = (void *)(FLAG_CFG0 | FLAG_CFG1 | FLAG_DEV_FIX), },
> + {}
> +};
> +
> +static int loongson_pci_probe(struct platform_device *pdev)
> +{
> + struct loongson_pci *priv;
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->of_node;
> + struct pci_host_bridge *bridge;
> + struct resource *regs;
> + int err;
> +
> + if (!node)
> + return -ENODEV;
> +
> + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*priv));
> + if (!bridge)
> + return -ENODEV;
> +
> + priv = pci_host_bridge_priv(bridge);
> + priv->pdev = pdev;
> + priv->flags = (unsigned long)of_device_get_match_data(dev);
> +
> + regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!regs) {
> + dev_err(dev, "missing mem resources for cfg0\n");
> + return -EINVAL;
> + }
> +
> + priv->cfg0_base = devm_pci_remap_cfg_resource(dev, regs);
> + if (IS_ERR(priv->cfg0_base))
> + return PTR_ERR(priv->cfg0_base);
> +
> + /* CFG1 is optional */
> + if (priv->flags & FLAG_CFG1) {
> + regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + if (!regs)
> + dev_info(dev, "missing mem resource for cfg1\n");
> + else {
> + priv->cfg1_base = devm_pci_remap_cfg_resource(dev, regs);
> + if (IS_ERR(priv->cfg1_base))
> + priv->cfg1_base = NULL;
> + }
> + }
> +
> +
Drop the extra blank line.
> + err = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
> + &bridge->dma_ranges, NULL);
> + if (err) {
> + dev_err(dev, "Failed to get bridge resources\n");
> + return err;
> + }
> +
> + bridge->dev.parent = dev;
> + bridge->sysdata = priv;
> + bridge->ops = &loongson_pci_ops;
> + bridge->map_irq = loongson_map_irq;
> +
> + err = pci_host_probe(bridge);
> + if (err)
> + return err;
> +
> + return 0;
> +}
> +
> +static struct platform_driver loongson_pci_driver = {
> + .driver = {
> + .name = "loongson-pci",
> + .of_match_table = loongson_pci_of_match,
> + },
> + .probe = loongson_pci_probe,
> +};
> +builtin_platform_driver(loongson_pci_driver);
> --
> 2.26.0.rc2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 4/6] dt-bindings: Document Loongson PCI Host Controller
2020-04-24 13:08 [PATCH v5 0/6] Loongson PCI Generic Driver Jiaxun Yang
` (2 preceding siblings ...)
2020-04-24 13:08 ` [PATCH v5 3/6] PCI: Add Loongson PCI Controller support Jiaxun Yang
@ 2020-04-24 13:08 ` Jiaxun Yang
2020-04-24 18:38 ` Rob Herring
2020-04-24 13:08 ` [PATCH v5 5/6] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
2020-04-24 13:08 ` [PATCH v5 6/6] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
5 siblings, 1 reply; 13+ messages in thread
From: Jiaxun Yang @ 2020-04-24 13:08 UTC (permalink / raw)
To: linux-pci
Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
Huacai Chen, Lorenzo Pieralisi, Andrew Murray, Paul Burton,
devicetree, linux-kernel, linux-mips
PCI host controller found on Loongson PCHs and SoCs.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
--
v3: Fix ranges
---
.../devicetree/bindings/pci/loongson.yaml | 62 +++++++++++++++++++
1 file changed, 62 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml
diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Documentation/devicetree/bindings/pci/loongson.yaml
new file mode 100644
index 000000000000..20b4cf3fe696
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/loongson.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/loongson.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson PCI Host Controller
+
+maintainers:
+ - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description: |+
+ PCI host controller found on Loongson PCHs and SoCs.
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - const: loongson,rs780e-pci
+ - const: loongson,ls7a-pci
+ - const: loongson,ls2k-pci
+
+ reg:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: CFG0 standard config space register
+ - description: CFG1 extended config space register
+
+ ranges:
+ minItems: 1
+ maxItems: 3
+
+
+required:
+ - compatible
+ - reg
+ - ranges
+
+examples:
+ - |
+
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcie@1a000000 {
+ compatible = "loongson,rs780e-pci";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ // CPU_PHYSICAL(2) SIZE(2)
+ reg = <0x0 0x1a000000 0x0 0x2000000>;
+
+ // BUS_ADDRESS(3) CPU_PHYSICAL(2) SIZE(2)
+ ranges = <0x01000000 0x0 0x00004000 0x0 0x00004000 0x0 0x00004000>,
+ <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
+ };
+ };
+...
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v5 4/6] dt-bindings: Document Loongson PCI Host Controller
2020-04-24 13:08 ` [PATCH v5 4/6] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
@ 2020-04-24 18:38 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-04-24 18:38 UTC (permalink / raw)
To: Jiaxun Yang
Cc: PCI, Bjorn Helgaas, Thomas Bogendoerfer, Huacai Chen,
Lorenzo Pieralisi, Andrew Murray, Paul Burton, devicetree,
linux-kernel, open list:MIPS
On Fri, Apr 24, 2020 at 8:10 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> PCI host controller found on Loongson PCHs and SoCs.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>
> --
> v3: Fix ranges
> ---
> .../devicetree/bindings/pci/loongson.yaml | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/loongson.yaml
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 5/6] MIPS: DTS: Loongson64: Add PCI Controller Node
2020-04-24 13:08 [PATCH v5 0/6] Loongson PCI Generic Driver Jiaxun Yang
` (3 preceding siblings ...)
2020-04-24 13:08 ` [PATCH v5 4/6] dt-bindings: Document Loongson PCI Host Controller Jiaxun Yang
@ 2020-04-24 13:08 ` Jiaxun Yang
2020-04-24 19:10 ` Rob Herring
2020-04-24 13:08 ` [PATCH v5 6/6] MIPS: Loongson64: Switch to generic PCI driver Jiaxun Yang
5 siblings, 1 reply; 13+ messages in thread
From: Jiaxun Yang @ 2020-04-24 13:08 UTC (permalink / raw)
To: linux-pci
Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
Huacai Chen, Lorenzo Pieralisi, Andrew Murray, Paul Burton,
devicetree, linux-kernel, linux-mips
Add PCI Host controller node for Loongson64 with RS780E PCH dts.
Note that PCI interrupts are probed via legacy way, as different
machine have different interrupt arrangement, we can't cover all
of them in dt.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
--
v2: Clean-up
---
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
index 8687c4f7370a..5e68ceae20ca 100644
--- a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -5,10 +5,25 @@ bus@10000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0 0x10000000 0 0x10000000 0 0x10000000
+ ranges = <0 0x00000000 0 0x00000000 0 0x00010000 /* I/O Ports */
+ 0 0x10000000 0 0x10000000 0 0x10000000
0 0x40000000 0 0x40000000 0 0x40000000
0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
+ pci@1a000000 {
+ compatible = "loongson,rs780e-pci";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ reg = <0 0x1a000000 0 0x02000000>;
+
+ ranges = <0x01000000 0 0x00004000 0 0x00004000 0 0x00004000>,
+ <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
+
+ bus-range = <0x00 0xff>;
+ };
+
isa {
compatible = "isa";
#address-cells = <2>;
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH v5 5/6] MIPS: DTS: Loongson64: Add PCI Controller Node
2020-04-24 13:08 ` [PATCH v5 5/6] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
@ 2020-04-24 19:10 ` Rob Herring
0 siblings, 0 replies; 13+ messages in thread
From: Rob Herring @ 2020-04-24 19:10 UTC (permalink / raw)
To: Jiaxun Yang
Cc: PCI, Bjorn Helgaas, Thomas Bogendoerfer, Huacai Chen,
Lorenzo Pieralisi, Andrew Murray, Paul Burton, devicetree,
linux-kernel, open list:MIPS
On Fri, Apr 24, 2020 at 8:10 AM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
>
> Add PCI Host controller node for Loongson64 with RS780E PCH dts.
> Note that PCI interrupts are probed via legacy way, as different
> machine have different interrupt arrangement, we can't cover all
> of them in dt.
>
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> --
> v2: Clean-up
> ---
> arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> index 8687c4f7370a..5e68ceae20ca 100644
> --- a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> +++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
> @@ -5,10 +5,25 @@ bus@10000000 {
> compatible = "simple-bus";
> #address-cells = <2>;
> #size-cells = <2>;
> - ranges = <0 0x10000000 0 0x10000000 0 0x10000000
> + ranges = <0 0x00000000 0 0x00000000 0 0x00010000 /* I/O Ports */
You're changing the first entry, so bus@10000000 unit-address should change.
Are i/o addresses really at 0x0 physical address?
> + 0 0x10000000 0 0x10000000 0 0x10000000
> 0 0x40000000 0 0x40000000 0 0x40000000
> 0xfd 0xfe000000 0xfd 0xfe000000 0 0x2000000 /* PCI Config Space */>;
>
> + pci@1a000000 {
> + compatible = "loongson,rs780e-pci";
> + device_type = "pci";
> + #address-cells = <3>;
> + #size-cells = <2>;
> +
> + reg = <0 0x1a000000 0 0x02000000>;
> +
> + ranges = <0x01000000 0 0x00004000 0 0x00004000 0 0x00004000>,
> + <0x02000000 0 0x40000000 0 0x40000000 0 0x40000000>;
> +
> + bus-range = <0x00 0xff>;
Not needed.
> + };
> +
> isa {
> compatible = "isa";
> #address-cells = <2>;
> --
> 2.26.0.rc2
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH v5 6/6] MIPS: Loongson64: Switch to generic PCI driver
2020-04-24 13:08 [PATCH v5 0/6] Loongson PCI Generic Driver Jiaxun Yang
` (4 preceding siblings ...)
2020-04-24 13:08 ` [PATCH v5 5/6] MIPS: DTS: Loongson64: Add PCI Controller Node Jiaxun Yang
@ 2020-04-24 13:08 ` Jiaxun Yang
5 siblings, 0 replies; 13+ messages in thread
From: Jiaxun Yang @ 2020-04-24 13:08 UTC (permalink / raw)
To: linux-pci
Cc: Jiaxun Yang, Bjorn Helgaas, Rob Herring, Thomas Bogendoerfer,
Huacai Chen, Lorenzo Pieralisi, Andrew Murray, Paul Burton,
devicetree, linux-kernel, linux-mips
We can now enable generic PCI driver in Kconfig, and remove legacy
PCI driver code.
Radeon vbios quirk is moved to the platform folder to fit the
new structure.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/Kconfig | 1 +
arch/mips/loongson64/Makefile | 2 +-
arch/mips/loongson64/vbios_quirk.c | 29 ++++++++
arch/mips/pci/Makefile | 1 -
arch/mips/pci/fixup-loongson3.c | 71 ------------------
arch/mips/pci/ops-loongson3.c | 116 -----------------------------
6 files changed, 31 insertions(+), 189 deletions(-)
create mode 100644 arch/mips/loongson64/vbios_quirk.c
delete mode 100644 arch/mips/pci/fixup-loongson3.c
delete mode 100644 arch/mips/pci/ops-loongson3.c
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 9f15539a6342..16f7ffef54e1 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -481,6 +481,7 @@ config MACH_LOONGSON64
select IRQ_MIPS_CPU
select NR_CPUS_DEFAULT_64
select USE_GENERIC_EARLY_PRINTK_8250
+ select PCI_DRIVERS_GENERIC
select SYS_HAS_CPU_LOONGSON64
select SYS_HAS_EARLY_PRINTK
select SYS_SUPPORTS_SMP
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 6f3c2b47f66f..6f81b822aeae 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -8,5 +8,5 @@ obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o dma.o \
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_NUMA) += numa.o
obj-$(CONFIG_RS780_HPET) += hpet.o
-obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_SUSPEND) += pm.o
+obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
diff --git a/arch/mips/loongson64/vbios_quirk.c b/arch/mips/loongson64/vbios_quirk.c
new file mode 100644
index 000000000000..1f0a462aeddd
--- /dev/null
+++ b/arch/mips/loongson64/vbios_quirk.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/pci.h>
+#include <loongson.h>
+
+static void pci_fixup_radeon(struct pci_dev *pdev)
+{
+ struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
+
+ if (res->start)
+ return;
+
+ if (!loongson_sysconf.vgabios_addr)
+ return;
+
+ pci_disable_rom(pdev);
+ if (res->parent)
+ release_resource(res);
+
+ res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
+ res->end = res->start + 256*1024 - 1;
+ res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
+ IORESOURCE_PCI_FIXED;
+
+ dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
+ PCI_ROM_RESOURCE, res);
+}
+DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, 0x9615,
+ PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 342ce10ef593..438f10955d89 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o
obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o
obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o
-obj-$(CONFIG_MACH_LOONGSON64) += fixup-loongson3.o ops-loongson3.o
obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o pci-malta.o
obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o
obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o
diff --git a/arch/mips/pci/fixup-loongson3.c b/arch/mips/pci/fixup-loongson3.c
deleted file mode 100644
index 8a741c2c6685..000000000000
--- a/arch/mips/pci/fixup-loongson3.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * fixup-loongson3.c
- *
- * Copyright (C) 2012 Lemote, Inc.
- * Author: Xiang Yu, xiangy@lemote.com
- * Chen Huacai, chenhc@lemote.com
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <linux/pci.h>
-#include <boot_param.h>
-
-static void print_fixup_info(const struct pci_dev *pdev)
-{
- dev_info(&pdev->dev, "Device %x:%x, irq %d\n",
- pdev->vendor, pdev->device, pdev->irq);
-}
-
-int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
- print_fixup_info(dev);
- return dev->irq;
-}
-
-static void pci_fixup_radeon(struct pci_dev *pdev)
-{
- struct resource *res = &pdev->resource[PCI_ROM_RESOURCE];
-
- if (res->start)
- return;
-
- if (!loongson_sysconf.vgabios_addr)
- return;
-
- pci_disable_rom(pdev);
- if (res->parent)
- release_resource(res);
-
- res->start = virt_to_phys((void *) loongson_sysconf.vgabios_addr);
- res->end = res->start + 256*1024 - 1;
- res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
- IORESOURCE_PCI_FIXED;
-
- dev_info(&pdev->dev, "BAR %d: assigned %pR for Radeon ROM\n",
- PCI_ROM_RESOURCE, res);
-}
-
-DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
- PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_radeon);
-
-/* Do platform specific device initialization at pci_enable_device() time */
-int pcibios_plat_dev_init(struct pci_dev *dev)
-{
- return 0;
-}
diff --git a/arch/mips/pci/ops-loongson3.c b/arch/mips/pci/ops-loongson3.c
deleted file mode 100644
index 2f6ad36bdea6..000000000000
--- a/arch/mips/pci/ops-loongson3.c
+++ /dev/null
@@ -1,116 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-
-#include <asm/mips-boards/bonito64.h>
-
-#include <loongson.h>
-
-#define PCI_ACCESS_READ 0
-#define PCI_ACCESS_WRITE 1
-
-#define HT1LO_PCICFG_BASE 0x1a000000
-#define HT1LO_PCICFG_BASE_TP1 0x1b000000
-
-static int loongson3_pci_config_access(unsigned char access_type,
- struct pci_bus *bus, unsigned int devfn,
- int where, u32 *data)
-{
- unsigned char busnum = bus->number;
- int function = PCI_FUNC(devfn);
- int device = PCI_SLOT(devfn);
- int reg = where & ~3;
- void *addrp;
- u64 addr;
-
- if (where < PCI_CFG_SPACE_SIZE) { /* standard config */
- addr = (busnum << 16) | (device << 11) | (function << 8) | reg;
- if (busnum == 0) {
- if (device > 31)
- return PCIBIOS_DEVICE_NOT_FOUND;
- addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE | addr);
- } else {
- addrp = (void *)TO_UNCAC(HT1LO_PCICFG_BASE_TP1 | addr);
- }
- } else if (where < PCI_CFG_SPACE_EXP_SIZE) { /* extended config */
- struct pci_dev *rootdev;
-
- rootdev = pci_get_domain_bus_and_slot(0, 0, 0);
- if (!rootdev)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- addr = pci_resource_start(rootdev, 3);
- if (!addr)
- return PCIBIOS_DEVICE_NOT_FOUND;
-
- addr |= busnum << 20 | device << 15 | function << 12 | reg;
- addrp = (void *)TO_UNCAC(addr);
- } else {
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
-
- if (access_type == PCI_ACCESS_WRITE)
- writel(*data, addrp);
- else {
- *data = readl(addrp);
- if (*data == 0xffffffff) {
- *data = -1;
- return PCIBIOS_DEVICE_NOT_FOUND;
- }
- }
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_read(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 *val)
-{
- u32 data = 0;
- int ret = loongson3_pci_config_access(PCI_ACCESS_READ,
- bus, devfn, where, &data);
-
- if (ret != PCIBIOS_SUCCESSFUL)
- return ret;
-
- if (size == 1)
- *val = (data >> ((where & 3) << 3)) & 0xff;
- else if (size == 2)
- *val = (data >> ((where & 3) << 3)) & 0xffff;
- else
- *val = data;
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-static int loongson3_pci_pcibios_write(struct pci_bus *bus, unsigned int devfn,
- int where, int size, u32 val)
-{
- u32 data = 0;
- int ret;
-
- if (size == 4)
- data = val;
- else {
- ret = loongson3_pci_config_access(PCI_ACCESS_READ,
- bus, devfn, where, &data);
- if (ret != PCIBIOS_SUCCESSFUL)
- return ret;
-
- if (size == 1)
- data = (data & ~(0xff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- else if (size == 2)
- data = (data & ~(0xffff << ((where & 3) << 3))) |
- (val << ((where & 3) << 3));
- }
-
- ret = loongson3_pci_config_access(PCI_ACCESS_WRITE,
- bus, devfn, where, &data);
-
- return ret;
-}
-
-struct pci_ops loongson_pci_ops = {
- .read = loongson3_pci_pcibios_read,
- .write = loongson3_pci_pcibios_write
-};
--
2.26.0.rc2
^ permalink raw reply related [flat|nested] 13+ messages in thread