* [PATCH 1/5] arm: dts: qcom: Add pcie nodes for ipq8064
2018-08-03 14:10 [PATCH 0/5] arm: dts: qcom: Few updates for ipq8064 Sricharan R
@ 2018-08-03 14:10 ` Sricharan R
2018-08-03 14:10 ` [PATCH 2/5] arm: dts: qcom: Add sdcc " Sricharan R
` (3 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Sricharan R @ 2018-08-03 14:10 UTC (permalink / raw)
To: andy.gross, david.brown, robh+dt, linux-arm-msm, linux-soc,
devicetree, linux-kernel
Cc: sricharan
Adding the pcie nodes and pins.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 182 ++++++++++++++++++++++++++++++++++++
1 file changed, 182 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 70790ac..e02d588 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -2,8 +2,11 @@
/dts-v1/;
#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
#include <dt-bindings/soc/qcom,gsbi.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -114,6 +117,33 @@
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+
+ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
+ function = "pcie1_rst";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ };
+
+ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
+ function = "pcie2_rst";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ };
+
+ pcie2_pins: pcie2_pinmux {
+ mux {
+ pins = "gpio63";
+ function = "pcie3_rst";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ };
};
intc: interrupt-controller@2000000 {
@@ -373,5 +403,157 @@
#reset-cells = <1>;
};
+ pcie0: pci@1b500000 {
+ compatible = "qcom,pcie-ipq8064";
+ reg = <0x1b500000 0x1000
+ 0x1b502000 0x80
+ 0x1b600000 0x100
+ 0x0ff00000 0x100000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc PCIE_A_CLK>,
+ <&gcc PCIE_H_CLK>,
+ <&gcc PCIE_PHY_CLK>,
+ <&gcc PCIE_AUX_CLK>,
+ <&gcc PCIE_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+
+ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc PCIE_ACLK_RESET>,
+ <&gcc PCIE_HCLK_RESET>,
+ <&gcc PCIE_POR_RESET>,
+ <&gcc PCIE_PCI_RESET>,
+ <&gcc PCIE_PHY_RESET>,
+ <&gcc PCIE_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
+
+ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
+ };
+
+ pcie1: pci@1b700000 {
+ compatible = "qcom,pcie-ipq8064";
+ reg = <0x1b700000 0x1000
+ 0x1b702000 0x80
+ 0x1b800000 0x100
+ 0x31f00000 0x100000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc PCIE_1_A_CLK>,
+ <&gcc PCIE_1_H_CLK>,
+ <&gcc PCIE_1_PHY_CLK>,
+ <&gcc PCIE_1_AUX_CLK>,
+ <&gcc PCIE_1_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+
+ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc PCIE_1_ACLK_RESET>,
+ <&gcc PCIE_1_HCLK_RESET>,
+ <&gcc PCIE_1_POR_RESET>,
+ <&gcc PCIE_1_PCI_RESET>,
+ <&gcc PCIE_1_PHY_RESET>,
+ <&gcc PCIE_1_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
+
+ pinctrl-0 = <&pcie1_pins>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
+ };
+
+ pcie2: pci@1b900000 {
+ compatible = "qcom,pcie-ipq8064";
+ reg = <0x1b900000 0x1000
+ 0x1b902000 0x80
+ 0x1ba00000 0x100
+ 0x35f00000 0x100000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <2>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
+ 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc PCIE_2_A_CLK>,
+ <&gcc PCIE_2_H_CLK>,
+ <&gcc PCIE_2_PHY_CLK>,
+ <&gcc PCIE_2_AUX_CLK>,
+ <&gcc PCIE_2_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+
+ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ resets = <&gcc PCIE_2_ACLK_RESET>,
+ <&gcc PCIE_2_HCLK_RESET>,
+ <&gcc PCIE_2_POR_RESET>,
+ <&gcc PCIE_2_PCI_RESET>,
+ <&gcc PCIE_2_PHY_RESET>,
+ <&gcc PCIE_2_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
+
+ pinctrl-0 = <&pcie2_pins>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
+ };
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/5] arm: dts: qcom: Add sdcc nodes for ipq8064
2018-08-03 14:10 [PATCH 0/5] arm: dts: qcom: Few updates for ipq8064 Sricharan R
2018-08-03 14:10 ` [PATCH 1/5] arm: dts: qcom: Add pcie nodes " Sricharan R
@ 2018-08-03 14:10 ` Sricharan R
2018-08-03 14:10 ` [PATCH 3/5] arm: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi Sricharan R
` (2 subsequent siblings)
4 siblings, 0 replies; 8+ messages in thread
From: Sricharan R @ 2018-08-03 14:10 UTC (permalink / raw)
To: andy.gross, david.brown, robh+dt, linux-arm-msm, linux-soc,
devicetree, linux-kernel
Cc: sricharan
The relevant data for sdcc.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064.dtsi | 76 +++++++++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index e02d588..e78618e 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -555,5 +555,81 @@
status = "disabled";
perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
};
+
+ vsdcc_fixed: vsdcc-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "SDCC Power";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ sdcc1bam:dma@12402000 {
+ compatible = "qcom,bam-v1.3.0";
+ reg = <0x12402000 0x8000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC1_H_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ sdcc3bam:dma@12182000 {
+ compatible = "qcom,bam-v1.3.0";
+ reg = <0x12182000 0x8000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc SDC3_H_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sdcc@12400000 {
+ status = "disabled";
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ reg = <0x12400000 0x2000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ max-frequency = <96000000>;
+ non-removable;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ vmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
+ dma-names = "tx", "rx";
+ };
+
+ sdcc@12180000 {
+ compatible = "arm,pl18x", "arm,primecell";
+ arm,primecell-periphid = <0x00051180>;
+ status = "disabled";
+ reg = <0x12180000 0x2000>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cmd_irq";
+ clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
+ clock-names = "mclk", "apb_pclk";
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <192000000>;
+ #mmc-ddr-1_8v;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ vqmmc-supply = <&vsdcc_fixed>;
+ dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
+ dma-names = "tx", "rx";
+ };
+ };
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/5] arm: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi
2018-08-03 14:10 [PATCH 0/5] arm: dts: qcom: Few updates for ipq8064 Sricharan R
2018-08-03 14:10 ` [PATCH 1/5] arm: dts: qcom: Add pcie nodes " Sricharan R
2018-08-03 14:10 ` [PATCH 2/5] arm: dts: qcom: Add sdcc " Sricharan R
@ 2018-08-03 14:10 ` Sricharan R
2018-08-03 14:10 ` [PATCH 4/5] arm: dts: qcom: Add ipq8064-ap161.dts Sricharan R
2018-08-03 14:10 ` [PATCH 5/5] arm: dts: qcom: Add led and gpio-button nodes to ipq8064 boards Sricharan R
4 siblings, 0 replies; 8+ messages in thread
From: Sricharan R @ 2018-08-03 14:10 UTC (permalink / raw)
To: andy.gross, david.brown, robh+dt, linux-arm-msm, linux-soc,
devicetree, linux-kernel
Cc: sricharan
The nodes in ipq8064-ap148.dts currently are common with
boards that we will add next. So move the common data to
ipq8064-v.1.0.dtsi.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 83 ++------------------------------
arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 65 +++++++++++++++++++++++++
arch/arm/boot/dts/qcom-ipq8064.dtsi | 9 ++++
3 files changed, 77 insertions(+), 80 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index bcf53e3..f45b05e 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -2,26 +2,8 @@
#include "qcom-ipq8064-v1.0.dtsi"
/ {
- model = "Qualcomm IPQ8064/AP148";
- compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
-
- aliases {
- serial0 = &gsbi4_serial;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- reserved-memory {
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- rsvd@41200000 {
- reg = <0x41200000 0x300000>;
- no-map;
- };
- };
+ model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
+ compatible = "qcom,ipq8064-ap148";
soc {
pinmux@800000 {
@@ -30,74 +12,15 @@
function = "gsbi4";
bias-disable;
};
-
- spi_pins: spi_pins {
- mux {
- pins = "gpio18", "gpio19", "gpio21";
- function = "gsbi5";
- drive-strength = <10>;
- bias-none;
- };
- };
};
gsbi@16300000 {
- qcom,mode = <GSBI_PROT_I2C_UART>;
- status = "ok";
- serial@16340000 {
- status = "ok";
- };
-
- i2c4: i2c@16380000 {
+ i2c@16380000 {
status = "ok";
-
clock-frequency = <200000>;
-
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
};
};
-
- gsbi5: gsbi@1a200000 {
- qcom,mode = <GSBI_PROT_SPI>;
- status = "ok";
-
- spi4: spi@1a280000 {
- status = "ok";
- spi-max-frequency = <50000000>;
-
- pinctrl-0 = <&spi_pins>;
- pinctrl-names = "default";
-
- cs-gpios = <&qcom_pinmux 20 0>;
-
- flash: m25p80@0 {
- compatible = "s25fl256s1";
- #address-cells = <1>;
- #size-cells = <1>;
- spi-max-frequency = <50000000>;
- reg = <0>;
-
- partition@0 {
- label = "rootfs";
- reg = <0x0 0x1000000>;
- };
-
- partition@1 {
- label = "scratch";
- reg = <0x1000000 0x1000000>;
- };
- };
- };
- };
-
- sata-phy@1b400000 {
- status = "ok";
- };
-
- sata@29000000 {
- ports-implemented = <0x1>;
- status = "ok";
- };
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
index e118119..ee32f97 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -1,2 +1,67 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";
+
+ aliases {
+ serial0 = &gsbi4_serial;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ soc {
+ gsbi@16300000 {
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+ status = "ok";
+
+ serial@16340000 {
+ status = "ok";
+ };
+ };
+
+ gsbi5: gsbi@1a200000 {
+ qcom,mode = <GSBI_PROT_SPI>;
+ status = "ok";
+
+ spi4: spi@1a280000 {
+ status = "ok";
+ spi-max-frequency = <50000000>;
+
+ pinctrl-0 = <&spi_pins>;
+ pinctrl-names = "default";
+
+ cs-gpios = <&qcom_pinmux 20 0>;
+
+ flash: m25p80@0 {
+ compatible = "s25fl256s1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+
+ partition@0 {
+ label = "rootfs";
+ reg = <0x0 0x1000000>;
+ };
+
+ partition@1 {
+ label = "scratch";
+ reg = <0x1000000 0x1000000>;
+ };
+ };
+ };
+ };
+
+ sata-phy@1b400000 {
+ status = "ok";
+ };
+
+ sata@29000000 {
+ ports-implemented = <0x1>;
+ status = "ok";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index e78618e..04cc822 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -144,6 +144,15 @@
bias-disable;
};
};
+
+ spi_pins: spi_pins {
+ mux {
+ pins = "gpio18", "gpio19", "gpio21";
+ function = "gsbi5";
+ drive-strength = <10>;
+ bias-none;
+ };
+ };
};
intc: interrupt-controller@2000000 {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 4/5] arm: dts: qcom: Add ipq8064-ap161.dts
2018-08-03 14:10 [PATCH 0/5] arm: dts: qcom: Few updates for ipq8064 Sricharan R
` (2 preceding siblings ...)
2018-08-03 14:10 ` [PATCH 3/5] arm: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi Sricharan R
@ 2018-08-03 14:10 ` Sricharan R
2018-08-06 20:35 ` Rob Herring
2018-08-03 14:10 ` [PATCH 5/5] arm: dts: qcom: Add led and gpio-button nodes to ipq8064 boards Sricharan R
4 siblings, 1 reply; 8+ messages in thread
From: Sricharan R @ 2018-08-03 14:10 UTC (permalink / raw)
To: andy.gross, david.brown, robh+dt, linux-arm-msm, linux-soc,
devicetree, linux-kernel
Cc: sricharan
Add a new board dts for ipq8064-ap161.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 7 +++++++
3 files changed, 10 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap161.dts
diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
index ee532e7..2325135 100644
--- a/Documentation/devicetree/bindings/arm/qcom.txt
+++ b/Documentation/devicetree/bindings/arm/qcom.txt
@@ -15,6 +15,7 @@ The 'SoC' and 'board' elements are required. All other elements are optional.
The 'SoC' element must be one of the following strings:
+ ipq8064
apq8016
apq8074
apq8084
@@ -30,6 +31,7 @@ The 'SoC' element must be one of the following strings:
The 'board' element must be one of the following strings:
+ ap
cdp
liquid
dragonboard
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 37a3de7..233661a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -772,6 +772,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq4019-ap.dk07.1-c1.dtb \
qcom-ipq4019-ap.dk07.1-c2.dtb \
qcom-ipq8064-ap148.dtb \
+ qcom-ipq8064-ap161.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-fairphone-fp2.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
new file mode 100644
index 0000000..aab5174
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "qcom-ipq8064-v1.0.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ8064/AP-161";
+ compatible = "qcom,ipq8064-ap161";
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 4/5] arm: dts: qcom: Add ipq8064-ap161.dts
2018-08-03 14:10 ` [PATCH 4/5] arm: dts: qcom: Add ipq8064-ap161.dts Sricharan R
@ 2018-08-06 20:35 ` Rob Herring
2018-08-07 2:22 ` Sricharan R
0 siblings, 1 reply; 8+ messages in thread
From: Rob Herring @ 2018-08-06 20:35 UTC (permalink / raw)
To: Sricharan
Cc: Andy Gross, David Brown, linux-arm-msm,
open list:ARM/QUALCOMM SUPPORT, devicetree, linux-kernel
On Fri, Aug 3, 2018 at 8:10 AM Sricharan R <sricharan@codeaurora.org> wrote:
>
> Add a new board dts for ipq8064-ap161.
>
> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
> ---
> Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 7 +++++++
> 3 files changed, 10 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap161.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
> index ee532e7..2325135 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.txt
> +++ b/Documentation/devicetree/bindings/arm/qcom.txt
> @@ -15,6 +15,7 @@ The 'SoC' and 'board' elements are required. All other elements are optional.
>
> The 'SoC' element must be one of the following strings:
>
> + ipq8064
> apq8016
> apq8074
> apq8084
> @@ -30,6 +31,7 @@ The 'SoC' element must be one of the following strings:
>
> The 'board' element must be one of the following strings:
>
> + ap
> cdp
> liquid
> dragonboard
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 37a3de7..233661a 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -772,6 +772,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
> qcom-ipq4019-ap.dk07.1-c1.dtb \
> qcom-ipq4019-ap.dk07.1-c2.dtb \
> qcom-ipq8064-ap148.dtb \
> + qcom-ipq8064-ap161.dtb \
> qcom-msm8660-surf.dtb \
> qcom-msm8960-cdp.dtb \
> qcom-msm8974-fairphone-fp2.dtb \
> diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
> new file mode 100644
> index 0000000..aab5174
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
> @@ -0,0 +1,7 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include "qcom-ipq8064-v1.0.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. IPQ8064/AP-161";
> + compatible = "qcom,ipq8064-ap161";
Doesn't match what you documented above. I'm guessing the ap148 board
didn't either...
Rob
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 4/5] arm: dts: qcom: Add ipq8064-ap161.dts
2018-08-06 20:35 ` Rob Herring
@ 2018-08-07 2:22 ` Sricharan R
0 siblings, 0 replies; 8+ messages in thread
From: Sricharan R @ 2018-08-07 2:22 UTC (permalink / raw)
To: Rob Herring
Cc: Andy Gross, David Brown, linux-arm-msm,
open list:ARM/QUALCOMM SUPPORT, devicetree, linux-kernel
Hi Rob,
On 8/7/2018 2:05 AM, Rob Herring wrote:
> On Fri, Aug 3, 2018 at 8:10 AM Sricharan R <sricharan@codeaurora.org> wrote:
>>
>> Add a new board dts for ipq8064-ap161.
>>
>> Signed-off-by: Sricharan R <sricharan@codeaurora.org>
>> ---
>> Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
>> arch/arm/boot/dts/Makefile | 1 +
>> arch/arm/boot/dts/qcom-ipq8064-ap161.dts | 7 +++++++
>> 3 files changed, 10 insertions(+)
>> create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap161.dts
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.txt b/Documentation/devicetree/bindings/arm/qcom.txt
>> index ee532e7..2325135 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.txt
>> +++ b/Documentation/devicetree/bindings/arm/qcom.txt
>> @@ -15,6 +15,7 @@ The 'SoC' and 'board' elements are required. All other elements are optional.
>>
>> The 'SoC' element must be one of the following strings:
>>
>> + ipq8064
>> apq8016
>> apq8074
>> apq8084
>> @@ -30,6 +31,7 @@ The 'SoC' element must be one of the following strings:
>>
>> The 'board' element must be one of the following strings:
>>
>> + ap
>> cdp
>> liquid
>> dragonboard
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index 37a3de7..233661a 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -772,6 +772,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
>> qcom-ipq4019-ap.dk07.1-c1.dtb \
>> qcom-ipq4019-ap.dk07.1-c2.dtb \
>> qcom-ipq8064-ap148.dtb \
>> + qcom-ipq8064-ap161.dtb \
>> qcom-msm8660-surf.dtb \
>> qcom-msm8960-cdp.dtb \
>> qcom-msm8974-fairphone-fp2.dtb \
>> diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap161.dts b/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
>> new file mode 100644
>> index 0000000..aab5174
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/qcom-ipq8064-ap161.dts
>> @@ -0,0 +1,7 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +#include "qcom-ipq8064-v1.0.dtsi"
>> +
>> +/ {
>> + model = "Qualcomm Technologies, Inc. IPQ8064/AP-161";
>> + compatible = "qcom,ipq8064-ap161";
>
> Doesn't match what you documented above. I'm guessing the ap148 board
> didn't either...
oops. yeah, ap148 id not having it. will add that and also correct this.
would call it as 'ap161' as the name for the board part.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 5/5] arm: dts: qcom: Add led and gpio-button nodes to ipq8064 boards
2018-08-03 14:10 [PATCH 0/5] arm: dts: qcom: Few updates for ipq8064 Sricharan R
` (3 preceding siblings ...)
2018-08-03 14:10 ` [PATCH 4/5] arm: dts: qcom: Add ipq8064-ap161.dts Sricharan R
@ 2018-08-03 14:10 ` Sricharan R
4 siblings, 0 replies; 8+ messages in thread
From: Sricharan R @ 2018-08-03 14:10 UTC (permalink / raw)
To: andy.gross, david.brown, robh+dt, linux-arm-msm, linux-soc,
devicetree, linux-kernel
Cc: sricharan
Add the dt nodes for enabling the leds and gpio-buttons.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 8 +++++
arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 60 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/qcom-ipq8064.dtsi | 19 ++++++++++
3 files changed, 87 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
index f45b05e..554c65e 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
@@ -12,6 +12,14 @@
function = "gsbi4";
bias-disable;
};
+
+ buttons_pins: buttons_pins {
+ mux {
+ pins = "gpio54", "gpio65";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
gsbi@16300000 {
diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
index ee32f97..e239a04 100644
--- a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064.dtsi"
+#include <dt-bindings/input/input.h>
/ {
model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";
@@ -63,5 +64,64 @@
ports-implemented = <0x1>;
status = "ok";
};
+
+ gpio_keys {
+ compatible = "gpio-keys";
+ pinctrl-0 = <&buttons_pins>;
+ pinctrl-names = "default";
+
+ button@1 {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ debounce-interval = <60>;
+ };
+ button@2 {
+ label = "wps";
+ linux,code = <KEY_WPS_BUTTON>;
+ gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
+ linux,input-type = <1>;
+ debounce-interval = <60>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-0 = <&leds_pins>;
+ pinctrl-names = "default";
+
+ led@7 {
+ label = "led_usb1";
+ gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "usbdev";
+ default-state = "off";
+ };
+
+ led@8 {
+ label = "led_usb3";
+ gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "usbdev";
+ default-state = "off";
+ };
+
+ led@9 {
+ label = "status_led_fail";
+ gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@26 {
+ label = "sata_led";
+ gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@53 {
+ label = "status_led_pass";
+ gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
};
};
diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 04cc822..f793cd1 100644
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -153,6 +153,25 @@
bias-none;
};
};
+
+ leds_pins: leds_pins {
+ mux {
+ pins = "gpio7", "gpio8", "gpio9",
+ "gpio26", "gpio53";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ output-low;
+ };
+ };
+
+ buttons_pins: buttons_pins {
+ mux {
+ pins = "gpio54";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
};
intc: interrupt-controller@2000000 {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 8+ messages in thread