* [PATCH V2 2/3] arm64: dts: tegra210: Add SDMMC Auto-cal settings
2018-12-19 22:55 [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Sowjanya Komatineni
@ 2018-12-19 22:55 ` Sowjanya Komatineni
2018-12-19 22:55 ` [PATCH V2 3/3] mmc: tegra: SDMMC pads auto-calibration Sowjanya Komatineni
2018-12-27 21:33 ` [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Rob Herring
2 siblings, 0 replies; 6+ messages in thread
From: Sowjanya Komatineni @ 2018-12-19 22:55 UTC (permalink / raw)
To: robh+dt, mark.rutland, mperttunen, thierry.reding, jonathanh,
adrian.hunter, ulf.hansson, pchandru
Cc: devicetree, linux-tegra, linux-kernel, linux-mmc, Sowjanya Komatineni
Add SDMMC initial pad offsets used by auto calibration process.
Add SDMMC fixed drive strengths used when calibration timeouts.
Fixed drive strengths are based on Pre SI Analysis of the pads.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 2 ++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 34 +++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 57 ++++++++++++++++++++++++++++++--
3 files changed, 91 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 2f3c8e29520d..0631bb9bfcc3 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -311,6 +311,8 @@
nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
+ nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
+ nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
nvidia,default-tap = <0x5>;
nvidia,default-trim = <0x9>;
nvidia,dqs-trim = <63>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index c2091bb16546..3fab6802c335 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -301,6 +301,17 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA194_RESET_SDMMC1>;
reset-names = "sdhci";
+ nvidia,pad-autocal-pull-up-offset-3v3-timeout =
+ <0x07>;
+ nvidia,pad-autocal-pull-down-offset-3v3-timeout =
+ <0x07>;
+ nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
+ nvidia,pad-autocal-pull-down-offset-1v8-timeout =
+ <0x07>;
+ nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
+ nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
+ nvidia,default-tap = <0x9>;
+ nvidia,default-trim = <0x5>;
status = "disabled";
};
@@ -312,6 +323,18 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA194_RESET_SDMMC3>;
reset-names = "sdhci";
+ nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
+ nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
+ nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
+ nvidia,pad-autocal-pull-down-offset-3v3-timeout =
+ <0x07>;
+ nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
+ nvidia,pad-autocal-pull-down-offset-1v8-timeout =
+ <0x07>;
+ nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
+ nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
+ nvidia,default-tap = <0x9>;
+ nvidia,default-trim = <0x5>;
status = "disabled";
};
@@ -323,6 +346,17 @@
clock-names = "sdhci";
resets = <&bpmp TEGRA194_RESET_SDMMC4>;
reset-names = "sdhci";
+ nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
+ nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
+ nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
+ nvidia,pad-autocal-pull-down-offset-1v8-timeout =
+ <0x0a>;
+ nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
+ nvidia,pad-autocal-pull-down-offset-3v3-timeout =
+ <0x0a>;
+ nvidia,default-tap = <0x8>;
+ nvidia,default-trim = <0x14>;
+ nvidia,dqs-trim = <40>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index 2205d66b0443..41408df9d4e9 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -476,6 +476,48 @@
compatible = "nvidia,tegra210-pinmux";
reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
<0x0 0x70003000 0x0 0x294>; /* Mux registers */
+ sdmmc1_3v3_drv: sdmmc1-3v3-drv {
+ sdmmc1 {
+ nvidia,pins = "drive_sdmmc1";
+ nvidia,pull-down-strength = <0x8>;
+ nvidia,pull-up-strength = <0x8>;
+ };
+ };
+ sdmmc1_1v8_drv: sdmmc1-1v8-drv {
+ sdmmc1 {
+ nvidia,pins = "drive_sdmmc1";
+ nvidia,pull-down-strength = <0x4>;
+ nvidia,pull-up-strength = <0x3>;
+ };
+ };
+ sdmmc2_1v8_drv: sdmmc2-1v8-drv {
+ sdmmc2 {
+ nvidia,pins = "drive_sdmmc2";
+ nvidia,pull-down-strength = <0x10>;
+ nvidia,pull-up-strength = <0x10>;
+ };
+ };
+ sdmmc3_3v3_drv: sdmmc3-3v3-drv {
+ sdmmc3 {
+ nvidia,pins = "drive_sdmmc3";
+ nvidia,pull-down-strength = <0x8>;
+ nvidia,pull-up-strength = <0x8>;
+ };
+ };
+ sdmmc3_1v8_drv: sdmmc3-1v8-drv {
+ sdmmc3 {
+ nvidia,pins = "drive_sdmmc3";
+ nvidia,pull-down-strength = <0x4>;
+ nvidia,pull-up-strength = <0x3>;
+ };
+ };
+ sdmmc4_1v8_drv: sdmmc4-1v8-drv {
+ sdmmc4 {
+ nvidia,pins = "drive_sdmmc4";
+ nvidia,pull-down-strength = <0x10>;
+ nvidia,pull-up-strength = <0x10>;
+ };
+ };
};
/*
@@ -1050,9 +1092,12 @@
clock-names = "sdhci";
resets = <&tegra_car 14>;
reset-names = "sdhci";
- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
+ "sdmmc-3v3-drv", "sdmmc-1v8-drv";
pinctrl-0 = <&sdmmc1_3v3>;
pinctrl-1 = <&sdmmc1_1v8>;
+ pinctrl-2 = <&sdmmc1_3v3_drv>;
+ pinctrl-3 = <&sdmmc1_1v8_drv>;
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
@@ -1075,6 +1120,8 @@
clock-names = "sdhci";
resets = <&tegra_car 9>;
reset-names = "sdhci";
+ pinctrl-names = "sdmmc-1v8-drv";
+ pinctrl-0 = <&sdmmc2_1v8_drv>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
nvidia,default-tap = <0x8>;
@@ -1090,9 +1137,12 @@
clock-names = "sdhci";
resets = <&tegra_car 69>;
reset-names = "sdhci";
- pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
+ pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
+ "sdmmc-3v3-drv", "sdmmc-1v8-drv";
pinctrl-0 = <&sdmmc3_3v3>;
pinctrl-1 = <&sdmmc3_1v8>;
+ pinctrl-2 = <&sdmmc3_3v3_drv>;
+ pinctrl-3 = <&sdmmc3_1v8_drv>;
nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
@@ -1110,6 +1160,9 @@
clock-names = "sdhci";
resets = <&tegra_car 15>;
reset-names = "sdhci";
+ pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
+ pinctrl-0 = <&sdmmc4_1v8_drv>;
+ pinctrl-1 = <&sdmmc4_1v8_drv>;
nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
nvidia,default-tap = <0x8>;
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH V2 3/3] mmc: tegra: SDMMC pads auto-calibration
2018-12-19 22:55 [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Sowjanya Komatineni
2018-12-19 22:55 ` [PATCH V2 2/3] arm64: dts: tegra210: Add SDMMC Auto-cal settings Sowjanya Komatineni
@ 2018-12-19 22:55 ` Sowjanya Komatineni
2018-12-27 21:33 ` [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Rob Herring
2 siblings, 0 replies; 6+ messages in thread
From: Sowjanya Komatineni @ 2018-12-19 22:55 UTC (permalink / raw)
To: robh+dt, mark.rutland, mperttunen, thierry.reding, jonathanh,
adrian.hunter, ulf.hansson, pchandru
Cc: devicetree, linux-tegra, linux-kernel, linux-mmc, Sowjanya Komatineni
Programs initial drive code offsets which will be used by auto
calibration process.
Programs fixed drive strengths for SDMMC pads when auto cal
timeouts. Fixed settings are based on Pre-SI analysis of the
pad design.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/mmc/host/sdhci-tegra.c | 107 +++++++++++++++++++++++++++++++----------
1 file changed, 81 insertions(+), 26 deletions(-)
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 7b95d088fdef..f8361249cf57 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -75,6 +75,7 @@
#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f
#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_VAL 0x7
#define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_E_INPUT_E_PWRD BIT(31)
+#define SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK 0x07FFF000
#define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec
#define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31)
@@ -121,6 +122,8 @@ struct sdhci_tegra {
struct pinctrl *pinctrl_sdmmc;
struct pinctrl_state *pinctrl_state_3v3;
struct pinctrl_state *pinctrl_state_1v8;
+ struct pinctrl_state *pinctrl_state_3v3_drv;
+ struct pinctrl_state *pinctrl_state_1v8_drv;
struct sdhci_tegra_autocal_offsets autocal_offsets;
ktime_t last_calib;
@@ -130,6 +133,9 @@ struct sdhci_tegra {
u32 dqs_trim;
};
+static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
+ bool state_drvupdn);
+
static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
@@ -437,6 +443,7 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3;
}
+ /* Set initial offset before auto-calibration */
tegra_sdhci_set_pad_autocal_offset(host, pdpu);
card_clk_enabled = tegra_sdhci_configure_card_clk(host, false);
@@ -460,19 +467,15 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host)
if (ret) {
dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
- if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
- pdpu = offsets.pull_down_1v8_timeout << 8 |
- offsets.pull_up_1v8_timeout;
- else
- pdpu = offsets.pull_down_3v3_timeout << 8 |
- offsets.pull_up_3v3_timeout;
-
- /* Disable automatic calibration and use fixed offsets */
+ /* Disable automatic cal and use fixed Drive Strengths */
reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);
reg &= ~SDHCI_AUTO_CAL_ENABLE;
sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG);
- tegra_sdhci_set_pad_autocal_offset(host, pdpu);
+ ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false);
+ if (ret < 0)
+ dev_err(mmc_dev(host->mmc),
+ "Setting drive strengths failed %d\n", PTR_ERR(ret));
}
}
@@ -743,27 +746,73 @@ static int tegra_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode)
return mmc_send_tuning(host->mmc, opcode, NULL);
}
-static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage)
+static int tegra_sdhci_set_padctrl(struct sdhci_host *host, int voltage,
+ bool state_drvupdn)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host);
- int ret;
+ struct sdhci_tegra_autocal_offsets offsets =
+ tegra_host->autocal_offsets;
+ struct pinctrl_state *pinctrl_drvupdn = NULL;
+ int ret = 0;
+ u8 drvup = 0, drvdn = 0;
+ u32 reg;
- if (!tegra_host->pad_control_available)
- return 0;
+ if (!state_drvupdn) {
+ /* PADS Drive Strength */
+ if (voltage == MMC_SIGNAL_VOLTAGE_180) {
+ if (!IS_ERR(tegra_host->pinctrl_state_1v8_drv) &&
+ (tegra_host->pinctrl_state_1v8_drv != NULL)) {
+ pinctrl_drvupdn =
+ tegra_host->pinctrl_state_1v8_drv;
+ } else {
+ drvup = offsets.pull_up_1v8_timeout;
+ drvdn = offsets.pull_down_1v8_timeout;
+ }
+ } else {
+ if (!IS_ERR(tegra_host->pinctrl_state_3v3_drv) &&
+ (tegra_host->pinctrl_state_3v3_drv != NULL)) {
+ pinctrl_drvupdn =
+ tegra_host->pinctrl_state_3v3_drv;
+ } else {
+ drvup = offsets.pull_up_3v3_timeout;
+ drvdn = offsets.pull_down_3v3_timeout;
+ }
+ }
+
+ if (pinctrl_drvupdn != NULL) {
+ ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
+ pinctrl_drvupdn);
+ if (ret < 0)
+ dev_err(mmc_dev(host->mmc),
+ "failed pads drvupdn, ret: %d\n", ret);
+ } else if ((drvup) || (drvdn)) {
+ reg = sdhci_readl(host,
+ SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
+ reg &= ~SDHCI_COMP_PADCTRL_DRVUPDN_OFFSET_MASK;
+ reg |= (drvup << 20) | (drvdn << 12);
+ sdhci_writel(host, reg,
+ SDHCI_TEGRA_SDMEM_COMP_PADCTRL);
+ }
- if (voltage == MMC_SIGNAL_VOLTAGE_180) {
- ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
- tegra_host->pinctrl_state_1v8);
- if (ret < 0)
- dev_err(mmc_dev(host->mmc),
- "setting 1.8V failed, ret: %d\n", ret);
} else {
- ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
- tegra_host->pinctrl_state_3v3);
- if (ret < 0)
- dev_err(mmc_dev(host->mmc),
- "setting 3.3V failed, ret: %d\n", ret);
+ /* Dual Voltage PADS Voltage selection */
+ if (!tegra_host->pad_control_available)
+ return 0;
+
+ if (voltage == MMC_SIGNAL_VOLTAGE_180) {
+ ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
+ tegra_host->pinctrl_state_1v8);
+ if (ret < 0)
+ dev_err(mmc_dev(host->mmc),
+ "setting 1.8V failed, ret: %d\n", ret);
+ } else {
+ ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
+ tegra_host->pinctrl_state_3v3);
+ if (ret < 0)
+ dev_err(mmc_dev(host->mmc),
+ "setting 3.3V failed, ret: %d\n", ret);
+ }
}
return ret;
@@ -778,7 +827,7 @@ static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
int ret = 0;
if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
- ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage);
+ ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
if (ret < 0)
return ret;
ret = sdhci_start_signal_voltage_switch(mmc, ios);
@@ -786,7 +835,7 @@ static int sdhci_tegra_start_signal_voltage_switch(struct mmc_host *mmc,
ret = sdhci_start_signal_voltage_switch(mmc, ios);
if (ret < 0)
return ret;
- ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage);
+ ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
}
if (tegra_host->pad_calib_required)
@@ -805,6 +854,12 @@ static int tegra_sdhci_init_pinctrl_info(struct device *dev,
return -1;
}
+ tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state(
+ tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv");
+
+ tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state(
+ tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv");
+
tegra_host->pinctrl_state_3v3 =
pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config
2018-12-19 22:55 [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Sowjanya Komatineni
2018-12-19 22:55 ` [PATCH V2 2/3] arm64: dts: tegra210: Add SDMMC Auto-cal settings Sowjanya Komatineni
2018-12-19 22:55 ` [PATCH V2 3/3] mmc: tegra: SDMMC pads auto-calibration Sowjanya Komatineni
@ 2018-12-27 21:33 ` Rob Herring
2018-12-29 0:08 ` Sowjanya Komatineni
2 siblings, 1 reply; 6+ messages in thread
From: Rob Herring @ 2018-12-27 21:33 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: mark.rutland, mperttunen, thierry.reding, jonathanh,
adrian.hunter, ulf.hansson, pchandru, devicetree, linux-tegra,
linux-kernel, linux-mmc
On Wed, Dec 19, 2018 at 02:55:51PM -0800, Sowjanya Komatineni wrote:
> Add pinctrl for 3V3 and 1V8 pad drive strength configuration for
> Tegra210 sdmmc which has pad configuration registers in the pinmux
> reigster domain.
typo
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> index 32b4b4e41923..2cecdc71d94c 100644
> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> @@ -39,12 +39,16 @@ sdhci@c8000200 {
> bus-width = <8>;
> };
>
> -Optional properties for Tegra210 and Tegra186:
> +Optional properties for Tegra210, Tegra186 and Tegra194:
Adding Tegra194, but this patch concerns Tegra210...
> - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
> configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
> for controllers supporting multiple voltage levels. The order of names
> should correspond to the pin configuration states in pinctrl-0 and
> pinctrl-1.
> +- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
These are in addition to the previous values?
> + Tegra210 where pad config registers are in the pinmux register domain
> + for pull-up-strength and pull-down-strength values configuration when
> + using pads at 3V3 and 1V8 levels.
> - nvidia,only-1-8-v : The presence of this property indicates that the
> controller operates at a 1.8 V fixed I/O voltage.
> - nvidia,pad-autocal-pull-up-offset-3v3,
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 6+ messages in thread* RE: [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config
2018-12-27 21:33 ` [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config Rob Herring
@ 2018-12-29 0:08 ` Sowjanya Komatineni
2019-01-03 18:35 ` Rob Herring
0 siblings, 1 reply; 6+ messages in thread
From: Sowjanya Komatineni @ 2018-12-29 0:08 UTC (permalink / raw)
To: Rob Herring
Cc: mark.rutland, Mikko Perttunen, thierry.reding, Jonathan Hunter,
adrian.hunter, ulf.hansson, Preetham Chandru, devicetree,
linux-tegra, linux-kernel, linux-mmc
Hi Rob,
>> Add pinctrl for 3V3 and 1V8 pad drive strength configuration for
>> Tegra210 sdmmc which has pad configuration registers in the pinmux
>> reigster domain.
>
> typo
>
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6
>> +++++-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> index 32b4b4e41923..2cecdc71d94c 100644
>> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
>> @@ -39,12 +39,16 @@ sdhci@c8000200 {
>> bus-width = <8>;
>> };
>>
>> -Optional properties for Tegra210 and Tegra186:
>> +Optional properties for Tegra210, Tegra186 and Tegra194:
>
>Adding Tegra194, but this patch concerns Tegra210...
Yes this is mainly part of Tegra210 Patch but pinctrls sdmmc-1v8 and sdmmc-3v3
also applies for Tegra194 and since it was not mentioned, added Tegra194 as well.
Does adding Tegra194 in this should come as separate patch?
>
>> - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
>> configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
>> for controllers supporting multiple voltage levels. The order of names
>> should correspond to the pin configuration states in pinctrl-0 and
>> pinctrl-1.
>> +- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable
>> +for
>
>These are in addition to the previous values?
Yes these are additional pinctrl states for pad drive settings which are in pinmux
Domain and are applicable during calibration process.
>
>> + Tegra210 where pad config registers are in the pinmux register
>> + domain for pull-up-strength and pull-down-strength values
>> + configuration when using pads at 3V3 and 1V8 levels.
>> - nvidia,only-1-8-v : The presence of this property indicates that the
>> controller operates at a 1.8 V fixed I/O voltage.
>> - nvidia,pad-autocal-pull-up-offset-3v3,
>> --
>> 2.7.4
>>
Thanks & Regards,
sowjanya
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH V2 1/3] dt-bindings: mmc: tegra: Add pinctrl for pad drive strength config
2018-12-29 0:08 ` Sowjanya Komatineni
@ 2019-01-03 18:35 ` Rob Herring
0 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2019-01-03 18:35 UTC (permalink / raw)
To: Sowjanya Komatineni
Cc: mark.rutland, Mikko Perttunen, thierry.reding, Jonathan Hunter,
adrian.hunter, ulf.hansson, Preetham Chandru, devicetree,
linux-tegra, linux-kernel, linux-mmc
On Fri, Dec 28, 2018 at 6:08 PM Sowjanya Komatineni
<skomatineni@nvidia.com> wrote:
>
> Hi Rob,
>
> >> Add pinctrl for 3V3 and 1V8 pad drive strength configuration for
> >> Tegra210 sdmmc which has pad configuration registers in the pinmux
> >> reigster domain.
> >
> > typo
> >
> >>
> >> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> >> ---
> >> Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 6
> >> +++++-
> >> 1 file changed, 5 insertions(+), 1 deletion(-)
> >>
> >> diff --git
> >> a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> >> b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> >> index 32b4b4e41923..2cecdc71d94c 100644
> >> --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> >> +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt
> >> @@ -39,12 +39,16 @@ sdhci@c8000200 {
> >> bus-width = <8>;
> >> };
> >>
> >> -Optional properties for Tegra210 and Tegra186:
> >> +Optional properties for Tegra210, Tegra186 and Tegra194:
> >
> >Adding Tegra194, but this patch concerns Tegra210...
> Yes this is mainly part of Tegra210 Patch but pinctrls sdmmc-1v8 and sdmmc-3v3
> also applies for Tegra194 and since it was not mentioned, added Tegra194 as well.
> Does adding Tegra194 in this should come as separate patch?
Same patch is fine, just make the commit message match.
> >
> >> - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
> >> configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
> >> for controllers supporting multiple voltage levels. The order of names
> >> should correspond to the pin configuration states in pinctrl-0 and
> >> pinctrl-1.
> >> +- pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable
> >> +for
> >
> >These are in addition to the previous values?
> Yes these are additional pinctrl states for pad drive settings which are in pinmux
> Domain and are applicable during calibration process.
Maybe '-cal' instead of '-drv' since that's the mode they apply to.
Rob
^ permalink raw reply [flat|nested] 6+ messages in thread