From: Rob Herring <robh@kernel.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Will Deacon <will.deacon@arm.com>,
Marc Zyngier <marc.zyngier@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Sudeep Holla <sudeep.holla@arm.com>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Jonathan.Cameron@huawei.com,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH v3 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU
Date: Thu, 27 Jul 2017 10:52:37 -0500 [thread overview]
Message-ID: <CAL_JsqLkeaMh8afWvYwca61OrX7QYzDt+eup_b3rQuyxumLwfw@mail.gmail.com> (raw)
In-Reply-To: <1501168218-26741-6-git-send-email-suzuki.poulose@arm.com>
+DT list
On Thu, Jul 27, 2017 at 10:10 AM, Suzuki K Poulose
<suzuki.poulose@arm.com> wrote:
> This patch documents the devicetree bindings for ARM DSU PMU.
>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Rob Herring <robh@kernel.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> .../devicetree/bindings/arm/arm-dsu-pmu.txt | 27 ++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
>
> diff --git a/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> new file mode 100644
> index 0000000..b9935ac
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/arm-dsu-pmu.txt
> @@ -0,0 +1,27 @@
> +* ARM DynamIQ Shared Unit (DSU) Performance Monitor Unit (PMU)
> +
> +ARM DyanmIQ Shared Unit (DSU) integrates one or more CPU cores
> +with a shared L3 memory system, control logic and external interfaces to
> +form a multicore cluster. The PMU enables to gather various statistics on
> +the operations of the DSU. The PMU provides independent 32bit counters that
> +can count any of the supported events, along with a 64bit cycle counter.
> +The PMU is accessed via CPU system registers and has no MMIO component.
> +
> +** DSU PMU required properties:
> +
> +- compatible : should be one of :
> +
> + "arm,dsu-pmu"
Seems kind of generic. There's only one flavor is DSU?
> +
> +- interrupts : Exactly 1 SPI must be listed.
> +
> +- cpus : List of phandles for the CPUs connected to this DSU instance.
> +
> +
> +** Example:
> +
> +dsu_pmu@0 {
Don't use "_" in node names and unit-address is not valid without a
reg property.
> + compatible = "arm,dsu-pmu";
> + interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>;
> + cpus = <&cpu_0>, <&cpu_1>;
> +};
> --
> 2.7.5
>
next prev parent reply other threads:[~2017-07-27 15:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-27 15:10 [PATCH v3 0/6] perf: Support for ARM DynamIQ Shared Unit PMU Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 1/6] perf: Export perf_event_update_userpage Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 2/6] of: Add helper for mapping device node to logical CPU number Suzuki K Poulose
2017-07-27 15:48 ` Rob Herring
2017-07-27 16:27 ` Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 3/6] coresight: of: Use of_device_node_get_cpu helper Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 4/6] irqchip: gic-v3: " Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 5/6] dt-bindings: Document devicetree binding for ARM DSU PMU Suzuki K Poulose
2017-07-27 15:52 ` Rob Herring [this message]
2017-07-27 16:09 ` Suzuki K Poulose
2017-07-27 15:10 ` [PATCH v3 6/6] perf: ARM DynamIQ Shared Unit PMU support Suzuki K Poulose
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