* [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support
@ 2013-01-09 12:06 Abhilash Kesavan
2013-01-09 12:06 ` [PATCH 2/4] ARM: EXYNOS5: Support Exynos5-bus devfreq driver Abhilash Kesavan
` (4 more replies)
0 siblings, 5 replies; 18+ messages in thread
From: Abhilash Kesavan @ 2013-01-09 12:06 UTC (permalink / raw)
To: myungjoo.ham, linux-kernel, linux-pm, kgene.kim
Cc: kyungmin.park, rjw, jhbird.choi, Abhilash Kesavan
PPMU is required by the devfreq driver. Add a device tree
node for it.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Cc: Jonghwan Choi <jhbird.choi@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
---
.../bindings/arm/exynos/ppmu-exynos5.txt | 28 ++++++++++++++++++++
arch/arm/boot/dts/exynos5250.dtsi | 9 ++++++
2 files changed, 37 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
diff --git a/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
new file mode 100644
index 0000000..a424dfa
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt
@@ -0,0 +1,28 @@
+Exynos5 PPMU driver
+-------------------
+
+Performance events are primitive values used to get performance data. These
+events provide information about the behavior of the SoC that can be used
+when analyzing system performance. These events are made visible using the
+PPMU logic.
+Exynos5 PPMU driver is used by the exynos5 devfreq driver to control the bus
+frequency/voltage.
+
+Required properties:
+- compatible: should be one of the following.
+ * samsung,exynos5-ppmu - for exynos5250 type ppmu.
+- reg:
+ * physical base address of the PPMUs (DDR, Right Bus and CPU) and
+ length of memory mapped region.
+
+Example:
+--------
+
+ ppmu {
+ compatible = "samsung,exynos5250-ppmu";
+ reg = <0x10C40000 0x2000
+ 0x10C50000 0x2000
+ 0x10C60000 0x2000
+ 0x10CB0000 0x2000
+ 0x13660000 0x2000>;
+ };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 30485de..d504cba 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -732,4 +732,13 @@
interrupt-parent = <&combiner>;
interrupts = <24 1>;
};
+
+ ppmu {
+ compatible = "samsung,exynos5250-ppmu";
+ reg = <0x10C40000 0x2000 /* PPMU_DDR_C */
+ 0x10C50000 0x2000 /* PPMU_DDR_R1 */
+ 0x10CB0000 0x2000 /* PPMU_DDR_L */
+ 0x13660000 0x2000 /* PPMU_DDR_RIGHT */
+ 0x10C60000 0x2000>; /* PPMU_DDR_CPU */
+ };
};
--
1.7.8.6
^ permalink raw reply related [flat|nested] 18+ messages in thread* [PATCH 2/4] ARM: EXYNOS5: Support Exynos5-bus devfreq driver 2013-01-09 12:06 [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support Abhilash Kesavan @ 2013-01-09 12:06 ` Abhilash Kesavan 2013-01-14 14:29 ` MyungJoo Ham 2013-01-18 13:23 ` [PATCH v4 " Abhilash Kesavan 2013-01-09 12:06 ` [PATCH 3/4] PM: DEVFREQ: Move exynos4 devfreq driver into a new sub-directory Abhilash Kesavan ` (3 subsequent siblings) 4 siblings, 2 replies; 18+ messages in thread From: Abhilash Kesavan @ 2013-01-09 12:06 UTC (permalink / raw) To: myungjoo.ham, linux-kernel, linux-pm, kgene.kim Cc: kyungmin.park, rjw, jhbird.choi, Abhilash Kesavan Setup the INT clock ops to control/vary INT frequency Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Jonghwan Choi <jhbird.choi@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> --- arch/arm/mach-exynos/clock-exynos5.c | 143 ++++++++++++++++++++++++ arch/arm/mach-exynos/include/mach/regs-clock.h | 37 ++++++ 2 files changed, 180 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 0208c3a..050879c 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -108,6 +108,11 @@ static struct clk exynos5_clk_sclk_usbphy = { .rate = 48000000, }; +/* Virtual Bus INT clock */ +static struct clk exynos5_int_clk = { + .name = "int_clk", +}; + static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable); @@ -1426,6 +1431,141 @@ static struct clk *exynos5_clks[] __initdata = { &clk_fout_cpll, &clk_fout_mpll_div2, &exynos5_clk_armclk, + &exynos5_int_clk, +}; + +#define INT_FREQ(f, a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, \ + c0, c1, d0, e0) \ + { \ + .freq = (f) * 1000000, \ + .clk_div_top0 = ((a0) << 0 | (a1) << 8 | (a2) << 12 | \ + (a3) << 16 | (a4) << 20 | (a5) << 28), \ + .clk_div_top1 = ((b0) << 12 | (b1) << 16 | (b2) << 20 | \ + (b3) << 24), \ + .clk_div_lex = ((c0) << 4 | (c1) << 8), \ + .clk_div_r0x = ((d0) << 4), \ + .clk_div_r1x = ((e0) << 4), \ + } + +static struct { + unsigned long freq; + u32 clk_div_top0; + u32 clk_div_top1; + u32 clk_div_lex; + u32 clk_div_r0x; + u32 clk_div_r1x; +} int_freq[] = { + /* + * values: + * freq + * clock divider for ACLK66, ACLK166, ACLK200, ACLK266, + ACLK333, ACLK300_DISP1 + * clock divider for ACLK300_GSCL, ACLK400_IOP, ACLK400_ISP, ACLK66_PRE + * clock divider for PCLK_LEX, ATCLK_LEX + * clock divider for ACLK_PR0X + * clock divider for ACLK_PR1X + */ + INT_FREQ(266, 1, 1, 3, 2, 0, 0, 0, 1, 1, 5, 1, 0, 1, 1), + INT_FREQ(200, 1, 2, 4, 3, 1, 0, 0, 3, 2, 5, 1, 0, 1, 1), + INT_FREQ(160, 1, 3, 4, 4, 2, 0, 0, 3, 3, 5, 1, 0, 1, 1), + INT_FREQ(133, 1, 3, 5, 5, 2, 1, 1, 4, 4, 5, 1, 0, 1, 1), + INT_FREQ(100, 1, 7, 7, 7, 7, 3, 7, 7, 7, 5, 1, 0, 1, 1), +}; + +static unsigned long exynos5_clk_int_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static void exynos5_int_set_clkdiv(unsigned int div_index) +{ + unsigned int tmp; + + /* Change Divider - TOP0 */ + tmp = __raw_readl(EXYNOS5_CLKDIV_TOP0); + + tmp &= ~(EXYNOS5_CLKDIV_TOP0_ACLK266_MASK | + EXYNOS5_CLKDIV_TOP0_ACLK200_MASK | + EXYNOS5_CLKDIV_TOP0_ACLK66_MASK | + EXYNOS5_CLKDIV_TOP0_ACLK333_MASK | + EXYNOS5_CLKDIV_TOP0_ACLK166_MASK | + EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_MASK); + + tmp |= int_freq[div_index].clk_div_top0; + + __raw_writel(tmp, EXYNOS5_CLKDIV_TOP0); + + /* Wait for TOP0 divider to stabilize */ + while (__raw_readl(EXYNOS5_CLKDIV_STAT_TOP0) & 0x151101) + cpu_relax(); + + /* Change Divider - TOP1 */ + tmp = __raw_readl(EXYNOS5_CLKDIV_TOP1); + + tmp &= ~(EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_MASK | + EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_MASK | + EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_MASK | + EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_MASK); + + tmp |= int_freq[div_index].clk_div_top1; + + __raw_writel(tmp, EXYNOS5_CLKDIV_TOP1); + + /* Wait for TOP0 and TOP1 dividers to stabilize */ + while ((__raw_readl(EXYNOS5_CLKDIV_STAT_TOP1) & 0x1110000) && + (__raw_readl(EXYNOS5_CLKDIV_STAT_TOP0) & 0x80000)) + cpu_relax(); + + /* Change Divider - LEX */ + tmp = int_freq[div_index].clk_div_lex; + + __raw_writel(tmp, EXYNOS5_CLKDIV_LEX); + + /* Wait for LEX divider to stabilize */ + while (__raw_readl(EXYNOS5_CLKDIV_STAT_LEX) & 0x110) + cpu_relax(); + + /* Change Divider - R0X */ + tmp = int_freq[div_index].clk_div_r0x; + + __raw_writel(tmp, EXYNOS5_CLKDIV_R0X); + + /* Wait for R0X divider to stabilize */ + while (__raw_readl(EXYNOS5_CLKDIV_STAT_R0X) & 0x10) + cpu_relax(); + + /* Change Divider - R1X */ + tmp = int_freq[div_index].clk_div_r1x; + + __raw_writel(tmp, EXYNOS5_CLKDIV_R1X); + + /* Wait for R1X divider to stabilize */ + while (__raw_readl(EXYNOS5_CLKDIV_STAT_R1X) & 0x10) + cpu_relax(); +} + +static int exynos5_clk_int_set_rate(struct clk *clk, unsigned long rate) +{ + int index; + + for (index = 0; index < ARRAY_SIZE(int_freq); index++) + if (int_freq[index].freq == rate) + break; + + if (index == ARRAY_SIZE(int_freq)) + return -EINVAL; + + /* Change the system clock divider values */ + exynos5_int_set_clkdiv(index); + + clk->rate = rate; + + return 0; +} + +static struct clk_ops exynos5_clk_int_ops = { + .get_rate = exynos5_clk_int_get_rate, + .set_rate = exynos5_clk_int_set_rate }; static u32 epll_div[][6] = { @@ -1620,6 +1760,9 @@ void __init_or_cpufreq exynos5_setup_clocks(void) clk_fout_epll.ops = &exynos5_epll_ops; + exynos5_int_clk.ops = &exynos5_clk_int_ops; + exynos5_int_clk.rate = aclk_266; + if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll)) printk(KERN_ERR "Unable to set parent %s of clock %s.\n", clk_fout_epll.name, exynos5_clk_mout_epll.clk.name); diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index d36ad76..3d3cbc8 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -323,6 +323,9 @@ #define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C) #define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580) +#define EXYNOS5_CLKDIV_STAT_TOP0 EXYNOS_CLKREG(0x10610) +#define EXYNOS5_CLKDIV_STAT_TOP1 EXYNOS_CLKREG(0x10614) + #define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) #define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800) #define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804) @@ -337,6 +340,18 @@ #define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960) #define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980) +#define EXYNOS5_CLKGATE_BUS_SYSLFT EXYNOS_CLKREG(0x08920) + +#define EXYNOS5_CLKOUT_CMU_TOP EXYNOS_CLKREG(0x10A00) + +#define EXYNOS5_CLKDIV_LEX EXYNOS_CLKREG(0x14500) +#define EXYNOS5_CLKDIV_STAT_LEX EXYNOS_CLKREG(0x14600) + +#define EXYNOS5_CLKDIV_R0X EXYNOS_CLKREG(0x18500) +#define EXYNOS5_CLKDIV_STAT_R0X EXYNOS_CLKREG(0x18600) + +#define EXYNOS5_CLKDIV_R1X EXYNOS_CLKREG(0x1C500) +#define EXYNOS5_CLKDIV_STAT_R1X EXYNOS_CLKREG(0x1C600) #define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110) #define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) #define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) @@ -347,6 +362,28 @@ #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) +#define EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_SHIFT (28) +#define EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_SHIFT) +#define EXYNOS5_CLKDIV_TOP0_ACLK333_SHIFT (20) +#define EXYNOS5_CLKDIV_TOP0_ACLK333_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK333_SHIFT) +#define EXYNOS5_CLKDIV_TOP0_ACLK266_SHIFT (16) +#define EXYNOS5_CLKDIV_TOP0_ACLK266_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK266_SHIFT) +#define EXYNOS5_CLKDIV_TOP0_ACLK200_SHIFT (12) +#define EXYNOS5_CLKDIV_TOP0_ACLK200_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK200_SHIFT) +#define EXYNOS5_CLKDIV_TOP0_ACLK166_SHIFT (8) +#define EXYNOS5_CLKDIV_TOP0_ACLK166_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK166_SHIFT) +#define EXYNOS5_CLKDIV_TOP0_ACLK66_SHIFT (0) +#define EXYNOS5_CLKDIV_TOP0_ACLK66_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK66_SHIFT) + +#define EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_SHIFT (24) +#define EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_SHIFT) +#define EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_SHIFT (20) +#define EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_SHIFT) +#define EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_SHIFT (16) +#define EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_SHIFT) +#define EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_SHIFT (12) +#define EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_SHIFT) + #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) -- 1.7.8.6 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 2/4] ARM: EXYNOS5: Support Exynos5-bus devfreq driver 2013-01-09 12:06 ` [PATCH 2/4] ARM: EXYNOS5: Support Exynos5-bus devfreq driver Abhilash Kesavan @ 2013-01-14 14:29 ` MyungJoo Ham 2013-01-18 13:23 ` [PATCH v4 " Abhilash Kesavan 1 sibling, 0 replies; 18+ messages in thread From: MyungJoo Ham @ 2013-01-14 14:29 UTC (permalink / raw) To: Abhilash Kesavan Cc: linux-kernel, linux-pm, kgene.kim, kyungmin.park, rjw, jhbird.choi On Wed, Jan 9, 2013 at 9:06 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote: > Setup the INT clock ops to control/vary INT frequency > > Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> > Cc: Jonghwan Choi <jhbird.choi@samsung.com> > Cc: Kukjin Kim <kgene.kim@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Is this part going to be merged at exynos-tree? Anyways, as I don't have Exynos5 devices personally, I can't test the code. > --- > arch/arm/mach-exynos/clock-exynos5.c | 143 ++++++++++++++++++++++++ > arch/arm/mach-exynos/include/mach/regs-clock.h | 37 ++++++ > 2 files changed, 180 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c > index 0208c3a..050879c 100644 > --- a/arch/arm/mach-exynos/clock-exynos5.c > +++ b/arch/arm/mach-exynos/clock-exynos5.c > @@ -108,6 +108,11 @@ static struct clk exynos5_clk_sclk_usbphy = { > .rate = 48000000, > }; > > +/* Virtual Bus INT clock */ > +static struct clk exynos5_int_clk = { > + .name = "int_clk", > +}; > + > static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable) > { > return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable); > @@ -1426,6 +1431,141 @@ static struct clk *exynos5_clks[] __initdata = { > &clk_fout_cpll, > &clk_fout_mpll_div2, > &exynos5_clk_armclk, > + &exynos5_int_clk, > +}; > + > +#define INT_FREQ(f, a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, \ > + c0, c1, d0, e0) \ > + { \ > + .freq = (f) * 1000000, \ > + .clk_div_top0 = ((a0) << 0 | (a1) << 8 | (a2) << 12 | \ > + (a3) << 16 | (a4) << 20 | (a5) << 28), \ > + .clk_div_top1 = ((b0) << 12 | (b1) << 16 | (b2) << 20 | \ > + (b3) << 24), \ > + .clk_div_lex = ((c0) << 4 | (c1) << 8), \ > + .clk_div_r0x = ((d0) << 4), \ > + .clk_div_r1x = ((e0) << 4), \ > + } > + > +static struct { > + unsigned long freq; > + u32 clk_div_top0; > + u32 clk_div_top1; > + u32 clk_div_lex; > + u32 clk_div_r0x; > + u32 clk_div_r1x; > +} int_freq[] = { > + /* > + * values: > + * freq > + * clock divider for ACLK66, ACLK166, ACLK200, ACLK266, > + ACLK333, ACLK300_DISP1 > + * clock divider for ACLK300_GSCL, ACLK400_IOP, ACLK400_ISP, ACLK66_PRE > + * clock divider for PCLK_LEX, ATCLK_LEX > + * clock divider for ACLK_PR0X > + * clock divider for ACLK_PR1X > + */ > + INT_FREQ(266, 1, 1, 3, 2, 0, 0, 0, 1, 1, 5, 1, 0, 1, 1), > + INT_FREQ(200, 1, 2, 4, 3, 1, 0, 0, 3, 2, 5, 1, 0, 1, 1), > + INT_FREQ(160, 1, 3, 4, 4, 2, 0, 0, 3, 3, 5, 1, 0, 1, 1), > + INT_FREQ(133, 1, 3, 5, 5, 2, 1, 1, 4, 4, 5, 1, 0, 1, 1), > + INT_FREQ(100, 1, 7, 7, 7, 7, 3, 7, 7, 7, 5, 1, 0, 1, 1), > +}; > + > +static unsigned long exynos5_clk_int_get_rate(struct clk *clk) > +{ > + return clk->rate; > +} > + > +static void exynos5_int_set_clkdiv(unsigned int div_index) > +{ > + unsigned int tmp; > + > + /* Change Divider - TOP0 */ > + tmp = __raw_readl(EXYNOS5_CLKDIV_TOP0); > + > + tmp &= ~(EXYNOS5_CLKDIV_TOP0_ACLK266_MASK | > + EXYNOS5_CLKDIV_TOP0_ACLK200_MASK | > + EXYNOS5_CLKDIV_TOP0_ACLK66_MASK | > + EXYNOS5_CLKDIV_TOP0_ACLK333_MASK | > + EXYNOS5_CLKDIV_TOP0_ACLK166_MASK | > + EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_MASK); > + > + tmp |= int_freq[div_index].clk_div_top0; > + > + __raw_writel(tmp, EXYNOS5_CLKDIV_TOP0); > + > + /* Wait for TOP0 divider to stabilize */ > + while (__raw_readl(EXYNOS5_CLKDIV_STAT_TOP0) & 0x151101) > + cpu_relax(); > + > + /* Change Divider - TOP1 */ > + tmp = __raw_readl(EXYNOS5_CLKDIV_TOP1); > + > + tmp &= ~(EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_MASK | > + EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_MASK | > + EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_MASK | > + EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_MASK); > + > + tmp |= int_freq[div_index].clk_div_top1; > + > + __raw_writel(tmp, EXYNOS5_CLKDIV_TOP1); > + > + /* Wait for TOP0 and TOP1 dividers to stabilize */ > + while ((__raw_readl(EXYNOS5_CLKDIV_STAT_TOP1) & 0x1110000) && > + (__raw_readl(EXYNOS5_CLKDIV_STAT_TOP0) & 0x80000)) > + cpu_relax(); > + > + /* Change Divider - LEX */ > + tmp = int_freq[div_index].clk_div_lex; > + > + __raw_writel(tmp, EXYNOS5_CLKDIV_LEX); > + > + /* Wait for LEX divider to stabilize */ > + while (__raw_readl(EXYNOS5_CLKDIV_STAT_LEX) & 0x110) > + cpu_relax(); > + > + /* Change Divider - R0X */ > + tmp = int_freq[div_index].clk_div_r0x; > + > + __raw_writel(tmp, EXYNOS5_CLKDIV_R0X); > + > + /* Wait for R0X divider to stabilize */ > + while (__raw_readl(EXYNOS5_CLKDIV_STAT_R0X) & 0x10) > + cpu_relax(); > + > + /* Change Divider - R1X */ > + tmp = int_freq[div_index].clk_div_r1x; > + > + __raw_writel(tmp, EXYNOS5_CLKDIV_R1X); > + > + /* Wait for R1X divider to stabilize */ > + while (__raw_readl(EXYNOS5_CLKDIV_STAT_R1X) & 0x10) > + cpu_relax(); > +} > + > +static int exynos5_clk_int_set_rate(struct clk *clk, unsigned long rate) > +{ > + int index; > + > + for (index = 0; index < ARRAY_SIZE(int_freq); index++) > + if (int_freq[index].freq == rate) > + break; > + > + if (index == ARRAY_SIZE(int_freq)) > + return -EINVAL; > + > + /* Change the system clock divider values */ > + exynos5_int_set_clkdiv(index); > + > + clk->rate = rate; > + > + return 0; > +} > + > +static struct clk_ops exynos5_clk_int_ops = { > + .get_rate = exynos5_clk_int_get_rate, > + .set_rate = exynos5_clk_int_set_rate > }; > > static u32 epll_div[][6] = { > @@ -1620,6 +1760,9 @@ void __init_or_cpufreq exynos5_setup_clocks(void) > > clk_fout_epll.ops = &exynos5_epll_ops; > > + exynos5_int_clk.ops = &exynos5_clk_int_ops; > + exynos5_int_clk.rate = aclk_266; > + > if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll)) > printk(KERN_ERR "Unable to set parent %s of clock %s.\n", > clk_fout_epll.name, exynos5_clk_mout_epll.clk.name); > diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h > index d36ad76..3d3cbc8 100644 > --- a/arch/arm/mach-exynos/include/mach/regs-clock.h > +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h > @@ -323,6 +323,9 @@ > #define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C) > #define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580) > > +#define EXYNOS5_CLKDIV_STAT_TOP0 EXYNOS_CLKREG(0x10610) > +#define EXYNOS5_CLKDIV_STAT_TOP1 EXYNOS_CLKREG(0x10614) > + > #define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) > #define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800) > #define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804) > @@ -337,6 +340,18 @@ > #define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960) > #define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980) > > +#define EXYNOS5_CLKGATE_BUS_SYSLFT EXYNOS_CLKREG(0x08920) > + > +#define EXYNOS5_CLKOUT_CMU_TOP EXYNOS_CLKREG(0x10A00) > + > +#define EXYNOS5_CLKDIV_LEX EXYNOS_CLKREG(0x14500) > +#define EXYNOS5_CLKDIV_STAT_LEX EXYNOS_CLKREG(0x14600) > + > +#define EXYNOS5_CLKDIV_R0X EXYNOS_CLKREG(0x18500) > +#define EXYNOS5_CLKDIV_STAT_R0X EXYNOS_CLKREG(0x18600) > + > +#define EXYNOS5_CLKDIV_R1X EXYNOS_CLKREG(0x1C500) > +#define EXYNOS5_CLKDIV_STAT_R1X EXYNOS_CLKREG(0x1C600) > #define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110) > #define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) > #define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) > @@ -347,6 +362,28 @@ > > #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) > > +#define EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_SHIFT (28) > +#define EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_SHIFT) > +#define EXYNOS5_CLKDIV_TOP0_ACLK333_SHIFT (20) > +#define EXYNOS5_CLKDIV_TOP0_ACLK333_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK333_SHIFT) > +#define EXYNOS5_CLKDIV_TOP0_ACLK266_SHIFT (16) > +#define EXYNOS5_CLKDIV_TOP0_ACLK266_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK266_SHIFT) > +#define EXYNOS5_CLKDIV_TOP0_ACLK200_SHIFT (12) > +#define EXYNOS5_CLKDIV_TOP0_ACLK200_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK200_SHIFT) > +#define EXYNOS5_CLKDIV_TOP0_ACLK166_SHIFT (8) > +#define EXYNOS5_CLKDIV_TOP0_ACLK166_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK166_SHIFT) > +#define EXYNOS5_CLKDIV_TOP0_ACLK66_SHIFT (0) > +#define EXYNOS5_CLKDIV_TOP0_ACLK66_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK66_SHIFT) > + > +#define EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_SHIFT (24) > +#define EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_SHIFT) > +#define EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_SHIFT (20) > +#define EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_SHIFT) > +#define EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_SHIFT (16) > +#define EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_SHIFT) > +#define EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_SHIFT (12) > +#define EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_SHIFT) > + > #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) > #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) > #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) > -- > 1.7.8.6 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- MyungJoo Ham, Ph.D. Mobile Software Platform Lab, DMC Business, Samsung Electronics ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 2/4] ARM: EXYNOS5: Support Exynos5-bus devfreq driver 2013-01-09 12:06 ` [PATCH 2/4] ARM: EXYNOS5: Support Exynos5-bus devfreq driver Abhilash Kesavan 2013-01-14 14:29 ` MyungJoo Ham @ 2013-01-18 13:23 ` Abhilash Kesavan 1 sibling, 0 replies; 18+ messages in thread From: Abhilash Kesavan @ 2013-01-18 13:23 UTC (permalink / raw) To: myungjoo.ham, linux-kernel, linux-pm, kgene.kim Cc: kyungmin.park, rjw, jhbird.choi Setup the INT clock ops to control/vary INT frequency Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Jonghwan Choi <jhbird.choi@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> --- Changes since RFC v1: * Fixed the unnecessary clock manipulations being done * Moved the PPMU driver from drivers/devfreq to machine specific directory Changes since v2: * Moved the PPMU driver to drivers/devfreq/exynos directory * Moved ppmu mach headers to include/linux * Removed static mapping and switched to DT support for PPMU Changes since v3: * Updated clock divider values arch/arm/mach-exynos/clock-exynos5.c | 143 ++++++++++++++++++++++++ arch/arm/mach-exynos/include/mach/regs-clock.h | 37 ++++++ 2 files changed, 180 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c index 0208c3a..050879c 100644 --- a/arch/arm/mach-exynos/clock-exynos5.c +++ b/arch/arm/mach-exynos/clock-exynos5.c @@ -108,6 +108,11 @@ static struct clk exynos5_clk_sclk_usbphy = { .rate = 48000000, }; +/* Virtual Bus INT clock */ +static struct clk exynos5_int_clk = { + .name = "int_clk", +}; + static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable) { return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable); @@ -1426,6 +1431,141 @@ static struct clk *exynos5_clks[] __initdata = { &clk_fout_cpll, &clk_fout_mpll_div2, &exynos5_clk_armclk, + &exynos5_int_clk, +}; + +#define INT_FREQ(f, a0, a1, a2, a3, a4, a5, b0, b1, b2, b3, \ + c0, c1, d0, e0) \ + { \ + .freq = (f) * 1000000, \ + .clk_div_top0 = ((a0) << 0 | (a1) << 8 | (a2) << 12 | \ + (a3) << 16 | (a4) << 20 | (a5) << 28), \ + .clk_div_top1 = ((b0) << 12 | (b1) << 16 | (b2) << 20 | \ + (b3) << 24), \ + .clk_div_lex = ((c0) << 4 | (c1) << 8), \ + .clk_div_r0x = ((d0) << 4), \ + .clk_div_r1x = ((e0) << 4), \ + } + +static struct { + unsigned long freq; + u32 clk_div_top0; + u32 clk_div_top1; + u32 clk_div_lex; + u32 clk_div_r0x; + u32 clk_div_r1x; +} int_freq[] = { + /* + * values: + * freq + * clock divider for ACLK66, ACLK166, ACLK200, ACLK266, + ACLK333, ACLK300_DISP1 + * clock divider for ACLK300_GSCL, ACLK400_IOP, ACLK400_ISP, ACLK66_PRE + * clock divider for PCLK_LEX, ATCLK_LEX + * clock divider for ACLK_PR0X + * clock divider for ACLK_PR1X + */ + INT_FREQ(266, 5, 1, 3, 2, 0, 2, 2, 1, 1, 1, 1, 0, 1, 1), + INT_FREQ(200, 5, 2, 4, 3, 1, 2, 2, 3, 2, 1, 1, 0, 1, 1), + INT_FREQ(160, 5, 3, 4, 4, 2, 2, 2, 3, 3, 1, 1, 0, 1, 1), + INT_FREQ(133, 5, 3, 5, 5, 2, 2, 3, 4, 4, 1, 1, 0, 1, 1), + INT_FREQ(100, 5, 7, 7, 7, 7, 3, 7, 7, 7, 1, 1, 0, 1, 1), +}; + +static unsigned long exynos5_clk_int_get_rate(struct clk *clk) +{ + return clk->rate; +} + +static void exynos5_int_set_clkdiv(unsigned int div_index) +{ + unsigned int tmp; + + /* Change Divider - TOP0 */ + tmp = __raw_readl(EXYNOS5_CLKDIV_TOP0); + + tmp &= ~(EXYNOS5_CLKDIV_TOP0_ACLK266_MASK | + EXYNOS5_CLKDIV_TOP0_ACLK200_MASK | + EXYNOS5_CLKDIV_TOP0_ACLK66_MASK | + EXYNOS5_CLKDIV_TOP0_ACLK333_MASK | + EXYNOS5_CLKDIV_TOP0_ACLK166_MASK | + EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_MASK); + + tmp |= int_freq[div_index].clk_div_top0; + + __raw_writel(tmp, EXYNOS5_CLKDIV_TOP0); + + /* Wait for TOP0 divider to stabilize */ + while (__raw_readl(EXYNOS5_CLKDIV_STAT_TOP0) & 0x151101) + cpu_relax(); + + /* Change Divider - TOP1 */ + tmp = __raw_readl(EXYNOS5_CLKDIV_TOP1); + + tmp &= ~(EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_MASK | + EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_MASK | + EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_MASK | + EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_MASK); + + tmp |= int_freq[div_index].clk_div_top1; + + __raw_writel(tmp, EXYNOS5_CLKDIV_TOP1); + + /* Wait for TOP0 and TOP1 dividers to stabilize */ + while ((__raw_readl(EXYNOS5_CLKDIV_STAT_TOP1) & 0x1110000) && + (__raw_readl(EXYNOS5_CLKDIV_STAT_TOP0) & 0x80000)) + cpu_relax(); + + /* Change Divider - LEX */ + tmp = int_freq[div_index].clk_div_lex; + + __raw_writel(tmp, EXYNOS5_CLKDIV_LEX); + + /* Wait for LEX divider to stabilize */ + while (__raw_readl(EXYNOS5_CLKDIV_STAT_LEX) & 0x110) + cpu_relax(); + + /* Change Divider - R0X */ + tmp = int_freq[div_index].clk_div_r0x; + + __raw_writel(tmp, EXYNOS5_CLKDIV_R0X); + + /* Wait for R0X divider to stabilize */ + while (__raw_readl(EXYNOS5_CLKDIV_STAT_R0X) & 0x10) + cpu_relax(); + + /* Change Divider - R1X */ + tmp = int_freq[div_index].clk_div_r1x; + + __raw_writel(tmp, EXYNOS5_CLKDIV_R1X); + + /* Wait for R1X divider to stabilize */ + while (__raw_readl(EXYNOS5_CLKDIV_STAT_R1X) & 0x10) + cpu_relax(); +} + +static int exynos5_clk_int_set_rate(struct clk *clk, unsigned long rate) +{ + int index; + + for (index = 0; index < ARRAY_SIZE(int_freq); index++) + if (int_freq[index].freq == rate) + break; + + if (index == ARRAY_SIZE(int_freq)) + return -EINVAL; + + /* Change the system clock divider values */ + exynos5_int_set_clkdiv(index); + + clk->rate = rate; + + return 0; +} + +static struct clk_ops exynos5_clk_int_ops = { + .get_rate = exynos5_clk_int_get_rate, + .set_rate = exynos5_clk_int_set_rate }; static u32 epll_div[][6] = { @@ -1620,6 +1760,9 @@ void __init_or_cpufreq exynos5_setup_clocks(void) clk_fout_epll.ops = &exynos5_epll_ops; + exynos5_int_clk.ops = &exynos5_clk_int_ops; + exynos5_int_clk.rate = aclk_266; + if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll)) printk(KERN_ERR "Unable to set parent %s of clock %s.\n", clk_fout_epll.name, exynos5_clk_mout_epll.clk.name); diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index d36ad76..3d3cbc8 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -323,6 +323,9 @@ #define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C) #define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580) +#define EXYNOS5_CLKDIV_STAT_TOP0 EXYNOS_CLKREG(0x10610) +#define EXYNOS5_CLKDIV_STAT_TOP1 EXYNOS_CLKREG(0x10614) + #define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) #define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800) #define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804) @@ -337,6 +340,18 @@ #define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960) #define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980) +#define EXYNOS5_CLKGATE_BUS_SYSLFT EXYNOS_CLKREG(0x08920) + +#define EXYNOS5_CLKOUT_CMU_TOP EXYNOS_CLKREG(0x10A00) + +#define EXYNOS5_CLKDIV_LEX EXYNOS_CLKREG(0x14500) +#define EXYNOS5_CLKDIV_STAT_LEX EXYNOS_CLKREG(0x14600) + +#define EXYNOS5_CLKDIV_R0X EXYNOS_CLKREG(0x18500) +#define EXYNOS5_CLKDIV_STAT_R0X EXYNOS_CLKREG(0x18600) + +#define EXYNOS5_CLKDIV_R1X EXYNOS_CLKREG(0x1C500) +#define EXYNOS5_CLKDIV_STAT_R1X EXYNOS_CLKREG(0x1C600) #define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110) #define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) #define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) @@ -347,6 +362,28 @@ #define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) +#define EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_SHIFT (28) +#define EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK300_DISP1_SHIFT) +#define EXYNOS5_CLKDIV_TOP0_ACLK333_SHIFT (20) +#define EXYNOS5_CLKDIV_TOP0_ACLK333_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK333_SHIFT) +#define EXYNOS5_CLKDIV_TOP0_ACLK266_SHIFT (16) +#define EXYNOS5_CLKDIV_TOP0_ACLK266_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK266_SHIFT) +#define EXYNOS5_CLKDIV_TOP0_ACLK200_SHIFT (12) +#define EXYNOS5_CLKDIV_TOP0_ACLK200_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK200_SHIFT) +#define EXYNOS5_CLKDIV_TOP0_ACLK166_SHIFT (8) +#define EXYNOS5_CLKDIV_TOP0_ACLK166_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK166_SHIFT) +#define EXYNOS5_CLKDIV_TOP0_ACLK66_SHIFT (0) +#define EXYNOS5_CLKDIV_TOP0_ACLK66_MASK (0x7 << EXYNOS5_CLKDIV_TOP0_ACLK66_SHIFT) + +#define EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_SHIFT (24) +#define EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK66_PRE_SHIFT) +#define EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_SHIFT (20) +#define EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK400_ISP_SHIFT) +#define EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_SHIFT (16) +#define EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK400_IOP_SHIFT) +#define EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_SHIFT (12) +#define EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_MASK (0x7 << EXYNOS5_CLKDIV_TOP1_ACLK300_GSCL_SHIFT) + #define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) #define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) #define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) -- 1.7.8.6 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/4] PM: DEVFREQ: Move exynos4 devfreq driver into a new sub-directory 2013-01-09 12:06 [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support Abhilash Kesavan 2013-01-09 12:06 ` [PATCH 2/4] ARM: EXYNOS5: Support Exynos5-bus devfreq driver Abhilash Kesavan @ 2013-01-09 12:06 ` Abhilash Kesavan 2013-01-14 14:30 ` MyungJoo Ham 2013-01-18 13:24 ` [PATCH v4 " Abhilash Kesavan 2013-01-09 12:06 ` [PATCH 4/4] PM/Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 Abhilash Kesavan ` (2 subsequent siblings) 4 siblings, 2 replies; 18+ messages in thread From: Abhilash Kesavan @ 2013-01-09 12:06 UTC (permalink / raw) To: myungjoo.ham, linux-kernel, linux-pm, kgene.kim Cc: kyungmin.park, rjw, jhbird.choi, Abhilash Kesavan In anticipation of the new exynos5 devfreq and ppmu driver, create an exynos sub-directory. Move the existing exynos4 devfreq driver into the same. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Jonghwan Choi <jhbird.choi@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> --- drivers/devfreq/Makefile | 2 +- drivers/devfreq/exynos/Makefile | 2 + drivers/devfreq/exynos/exynos4_bus.c | 1113 ++++++++++++++++++++++++++++++++++ drivers/devfreq/exynos4_bus.c | 1113 ---------------------------------- 4 files changed, 1116 insertions(+), 1114 deletions(-) create mode 100644 drivers/devfreq/exynos/Makefile create mode 100644 drivers/devfreq/exynos/exynos4_bus.c delete mode 100644 drivers/devfreq/exynos4_bus.c diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 8c46423..3bc1fef 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -5,4 +5,4 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o # DEVFREQ Drivers -obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o +obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/ diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile new file mode 100644 index 0000000..1498823 --- /dev/null +++ b/drivers/devfreq/exynos/Makefile @@ -0,0 +1,2 @@ +# Exynos DEVFREQ Drivers +obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o diff --git a/drivers/devfreq/exynos/exynos4_bus.c b/drivers/devfreq/exynos/exynos4_bus.c new file mode 100644 index 0000000..7418372 --- /dev/null +++ b/drivers/devfreq/exynos/exynos4_bus.c @@ -0,0 +1,1113 @@ +/* drivers/devfreq/exynos4210_memorybus.c + * + * Copyright (c) 2011 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * MyungJoo Ham <myungjoo.ham@samsung.com> + * + * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework + * This version supports EXYNOS4210 only. This changes bus frequencies + * and vddint voltages. Exynos4412/4212 should be able to be supported + * with minor modifications. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/io.h> +#include <linux/slab.h> +#include <linux/mutex.h> +#include <linux/suspend.h> +#include <linux/opp.h> +#include <linux/devfreq.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/module.h> + +/* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */ +#ifdef CONFIG_EXYNOS_ASV +extern unsigned int exynos_result_of_asv; +#endif + +#include <mach/regs-clock.h> + +#include <plat/map-s5p.h> + +#define MAX_SAFEVOLT 1200000 /* 1.2V */ + +enum exynos4_busf_type { + TYPE_BUSF_EXYNOS4210, + TYPE_BUSF_EXYNOS4x12, +}; + +/* Assume that the bus is saturated if the utilization is 40% */ +#define BUS_SATURATION_RATIO 40 + +enum ppmu_counter { + PPMU_PMNCNT0 = 0, + PPMU_PMCCNT1, + PPMU_PMNCNT2, + PPMU_PMNCNT3, + PPMU_PMNCNT_MAX, +}; +struct exynos4_ppmu { + void __iomem *hw_base; + unsigned int ccnt; + unsigned int event; + unsigned int count[PPMU_PMNCNT_MAX]; + bool ccnt_overflow; + bool count_overflow[PPMU_PMNCNT_MAX]; +}; + +enum busclk_level_idx { + LV_0 = 0, + LV_1, + LV_2, + LV_3, + LV_4, + _LV_END +}; +#define EX4210_LV_MAX LV_2 +#define EX4x12_LV_MAX LV_4 +#define EX4210_LV_NUM (LV_2 + 1) +#define EX4x12_LV_NUM (LV_4 + 1) + +struct busfreq_data { + enum exynos4_busf_type type; + struct device *dev; + struct devfreq *devfreq; + bool disabled; + struct regulator *vdd_int; + struct regulator *vdd_mif; /* Exynos4412/4212 only */ + struct opp *curr_opp; + struct exynos4_ppmu dmc[2]; + + struct notifier_block pm_notifier; + struct mutex lock; + + /* Dividers calculated at boot/probe-time */ + unsigned int dmc_divtable[_LV_END]; /* DMC0 */ + unsigned int top_divtable[_LV_END]; +}; + +struct bus_opp_table { + unsigned int idx; + unsigned long clk; + unsigned long volt; +}; + +/* 4210 controls clock of mif and voltage of int */ +static struct bus_opp_table exynos4210_busclk_table[] = { + {LV_0, 400000, 1150000}, + {LV_1, 267000, 1050000}, + {LV_2, 133000, 1025000}, + {0, 0, 0}, +}; + +/* + * MIF is the main control knob clock for exynox4x12 MIF/INT + * clock and voltage of both mif/int are controlled. + */ +static struct bus_opp_table exynos4x12_mifclk_table[] = { + {LV_0, 400000, 1100000}, + {LV_1, 267000, 1000000}, + {LV_2, 160000, 950000}, + {LV_3, 133000, 950000}, + {LV_4, 100000, 950000}, + {0, 0, 0}, +}; + +/* + * INT is not the control knob of 4x12. LV_x is not meant to represent + * the current performance. (MIF does) + */ +static struct bus_opp_table exynos4x12_intclk_table[] = { + {LV_0, 200000, 1000000}, + {LV_1, 160000, 950000}, + {LV_2, 133000, 925000}, + {LV_3, 100000, 900000}, + {0, 0, 0}, +}; + +/* TODO: asv volt definitions are "__initdata"? */ +/* Some chips have different operating voltages */ +static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = { + {1150000, 1050000, 1050000}, + {1125000, 1025000, 1025000}, + {1100000, 1000000, 1000000}, + {1075000, 975000, 975000}, + {1050000, 950000, 950000}, +}; + +static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = { + /* 400 267 160 133 100 */ + {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */ + {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */ + {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */ + {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */ + {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */ + {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */ + {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */ + {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */ + {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */ +}; + +static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = { + /* 200 160 133 100 */ + {1000000, 950000, 925000, 900000}, /* ASV0 */ + {975000, 925000, 925000, 900000}, /* ASV1 */ + {950000, 925000, 900000, 875000}, /* ASV2 */ + {950000, 900000, 900000, 875000}, /* ASV3 */ + {925000, 875000, 875000, 875000}, /* ASV4 */ + {900000, 850000, 850000, 850000}, /* ASV5 */ + {900000, 850000, 850000, 850000}, /* ASV6 */ + {900000, 850000, 850000, 850000}, /* ASV7 */ + {900000, 850000, 850000, 850000}, /* ASV8 */ +}; + +/*** Clock Divider Data for Exynos4210 ***/ +static unsigned int exynos4210_clkdiv_dmc0[][8] = { + /* + * Clock divider value for following + * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD + * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS } + */ + + /* DMC L0: 400MHz */ + { 3, 1, 1, 1, 1, 1, 3, 1 }, + /* DMC L1: 266.7MHz */ + { 4, 1, 1, 2, 1, 1, 3, 1 }, + /* DMC L2: 133MHz */ + { 5, 1, 1, 5, 1, 1, 3, 1 }, +}; +static unsigned int exynos4210_clkdiv_top[][5] = { + /* + * Clock divider value for following + * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND } + */ + /* ACLK200 L0: 200MHz */ + { 3, 7, 4, 5, 1 }, + /* ACLK200 L1: 160MHz */ + { 4, 7, 5, 6, 1 }, + /* ACLK200 L2: 133MHz */ + { 5, 7, 7, 7, 1 }, +}; +static unsigned int exynos4210_clkdiv_lr_bus[][2] = { + /* + * Clock divider value for following + * { DIVGDL/R, DIVGPL/R } + */ + /* ACLK_GDL/R L1: 200MHz */ + { 3, 1 }, + /* ACLK_GDL/R L2: 160MHz */ + { 4, 1 }, + /* ACLK_GDL/R L3: 133MHz */ + { 5, 1 }, +}; + +/*** Clock Divider Data for Exynos4212/4412 ***/ +static unsigned int exynos4x12_clkdiv_dmc0[][6] = { + /* + * Clock divider value for following + * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD + * DIVDMCP} + */ + + /* DMC L0: 400MHz */ + {3, 1, 1, 1, 1, 1}, + /* DMC L1: 266.7MHz */ + {4, 1, 1, 2, 1, 1}, + /* DMC L2: 160MHz */ + {5, 1, 1, 4, 1, 1}, + /* DMC L3: 133MHz */ + {5, 1, 1, 5, 1, 1}, + /* DMC L4: 100MHz */ + {7, 1, 1, 7, 1, 1}, +}; +static unsigned int exynos4x12_clkdiv_dmc1[][6] = { + /* + * Clock divider value for following + * { G2DACP, DIVC2C, DIVC2C_ACLK } + */ + + /* DMC L0: 400MHz */ + {3, 1, 1}, + /* DMC L1: 266.7MHz */ + {4, 2, 1}, + /* DMC L2: 160MHz */ + {5, 4, 1}, + /* DMC L3: 133MHz */ + {5, 5, 1}, + /* DMC L4: 100MHz */ + {7, 7, 1}, +}; +static unsigned int exynos4x12_clkdiv_top[][5] = { + /* + * Clock divider value for following + * { DIVACLK266_GPS, DIVACLK100, DIVACLK160, + DIVACLK133, DIVONENAND } + */ + + /* ACLK_GDL/R L0: 200MHz */ + {2, 7, 4, 5, 1}, + /* ACLK_GDL/R L1: 200MHz */ + {2, 7, 4, 5, 1}, + /* ACLK_GDL/R L2: 160MHz */ + {4, 7, 5, 7, 1}, + /* ACLK_GDL/R L3: 133MHz */ + {4, 7, 5, 7, 1}, + /* ACLK_GDL/R L4: 100MHz */ + {7, 7, 7, 7, 1}, +}; +static unsigned int exynos4x12_clkdiv_lr_bus[][2] = { + /* + * Clock divider value for following + * { DIVGDL/R, DIVGPL/R } + */ + + /* ACLK_GDL/R L0: 200MHz */ + {3, 1}, + /* ACLK_GDL/R L1: 200MHz */ + {3, 1}, + /* ACLK_GDL/R L2: 160MHz */ + {4, 1}, + /* ACLK_GDL/R L3: 133MHz */ + {5, 1}, + /* ACLK_GDL/R L4: 100MHz */ + {7, 1}, +}; +static unsigned int exynos4x12_clkdiv_sclkip[][3] = { + /* + * Clock divider value for following + * { DIVMFC, DIVJPEG, DIVFIMC0~3} + */ + + /* SCLK_MFC: 200MHz */ + {3, 3, 4}, + /* SCLK_MFC: 200MHz */ + {3, 3, 4}, + /* SCLK_MFC: 160MHz */ + {4, 4, 5}, + /* SCLK_MFC: 133MHz */ + {5, 5, 5}, + /* SCLK_MFC: 100MHz */ + {7, 7, 7}, +}; + + +static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp) +{ + unsigned int index; + unsigned int tmp; + + for (index = LV_0; index < EX4210_LV_NUM; index++) + if (opp_get_freq(opp) == exynos4210_busclk_table[index].clk) + break; + + if (index == EX4210_LV_NUM) + return -EINVAL; + + /* Change Divider - DMC0 */ + tmp = data->dmc_divtable[index]; + + __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); + } while (tmp & 0x11111111); + + /* Change Divider - TOP */ + tmp = data->top_divtable[index]; + + __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); + } while (tmp & 0x11111); + + /* Change Divider - LEFTBUS */ + tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); + + tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); + + tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << + EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | + (exynos4210_clkdiv_lr_bus[index][1] << + EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); + + __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); + } while (tmp & 0x11); + + /* Change Divider - RIGHTBUS */ + tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); + + tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); + + tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << + EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | + (exynos4210_clkdiv_lr_bus[index][1] << + EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); + + __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); + } while (tmp & 0x11); + + return 0; +} + +static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp) +{ + unsigned int index; + unsigned int tmp; + + for (index = LV_0; index < EX4x12_LV_NUM; index++) + if (opp_get_freq(opp) == exynos4x12_mifclk_table[index].clk) + break; + + if (index == EX4x12_LV_NUM) + return -EINVAL; + + /* Change Divider - DMC0 */ + tmp = data->dmc_divtable[index]; + + __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); + } while (tmp & 0x11111111); + + /* Change Divider - DMC1 */ + tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1); + + tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK | + EXYNOS4_CLKDIV_DMC1_C2C_MASK | + EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK); + + tmp |= ((exynos4x12_clkdiv_dmc1[index][0] << + EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) | + (exynos4x12_clkdiv_dmc1[index][1] << + EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) | + (exynos4x12_clkdiv_dmc1[index][2] << + EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)); + + __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1); + } while (tmp & 0x111111); + + /* Change Divider - TOP */ + tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); + + tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK | + EXYNOS4_CLKDIV_TOP_ACLK100_MASK | + EXYNOS4_CLKDIV_TOP_ACLK160_MASK | + EXYNOS4_CLKDIV_TOP_ACLK133_MASK | + EXYNOS4_CLKDIV_TOP_ONENAND_MASK); + + tmp |= ((exynos4x12_clkdiv_top[index][0] << + EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) | + (exynos4x12_clkdiv_top[index][1] << + EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | + (exynos4x12_clkdiv_top[index][2] << + EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | + (exynos4x12_clkdiv_top[index][3] << + EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | + (exynos4x12_clkdiv_top[index][4] << + EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)); + + __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); + } while (tmp & 0x11111); + + /* Change Divider - LEFTBUS */ + tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); + + tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); + + tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << + EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | + (exynos4x12_clkdiv_lr_bus[index][1] << + EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); + + __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); + } while (tmp & 0x11); + + /* Change Divider - RIGHTBUS */ + tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); + + tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); + + tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << + EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | + (exynos4x12_clkdiv_lr_bus[index][1] << + EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); + + __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); + } while (tmp & 0x11); + + /* Change Divider - MFC */ + tmp = __raw_readl(EXYNOS4_CLKDIV_MFC); + + tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK); + + tmp |= ((exynos4x12_clkdiv_sclkip[index][0] << + EXYNOS4_CLKDIV_MFC_SHIFT)); + + __raw_writel(tmp, EXYNOS4_CLKDIV_MFC); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC); + } while (tmp & 0x1); + + /* Change Divider - JPEG */ + tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1); + + tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK); + + tmp |= ((exynos4x12_clkdiv_sclkip[index][1] << + EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)); + + __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); + } while (tmp & 0x1); + + /* Change Divider - FIMC0~3 */ + tmp = __raw_readl(EXYNOS4_CLKDIV_CAM); + + tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK | + EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK); + + tmp |= ((exynos4x12_clkdiv_sclkip[index][2] << + EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) | + (exynos4x12_clkdiv_sclkip[index][2] << + EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) | + (exynos4x12_clkdiv_sclkip[index][2] << + EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) | + (exynos4x12_clkdiv_sclkip[index][2] << + EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)); + + __raw_writel(tmp, EXYNOS4_CLKDIV_CAM); + + do { + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); + } while (tmp & 0x1111); + + return 0; +} + + +static void busfreq_mon_reset(struct busfreq_data *data) +{ + unsigned int i; + + for (i = 0; i < 2; i++) { + void __iomem *ppmu_base = data->dmc[i].hw_base; + + /* Reset PPMU */ + __raw_writel(0x8000000f, ppmu_base + 0xf010); + __raw_writel(0x8000000f, ppmu_base + 0xf050); + __raw_writel(0x6, ppmu_base + 0xf000); + __raw_writel(0x0, ppmu_base + 0xf100); + + /* Set PPMU Event */ + data->dmc[i].event = 0x6; + __raw_writel(((data->dmc[i].event << 12) | 0x1), + ppmu_base + 0xfc); + + /* Start PPMU */ + __raw_writel(0x1, ppmu_base + 0xf000); + } +} + +static void exynos4_read_ppmu(struct busfreq_data *data) +{ + int i, j; + + for (i = 0; i < 2; i++) { + void __iomem *ppmu_base = data->dmc[i].hw_base; + u32 overflow; + + /* Stop PPMU */ + __raw_writel(0x0, ppmu_base + 0xf000); + + /* Update local data from PPMU */ + overflow = __raw_readl(ppmu_base + 0xf050); + + data->dmc[i].ccnt = __raw_readl(ppmu_base + 0xf100); + data->dmc[i].ccnt_overflow = overflow & (1 << 31); + + for (j = 0; j < PPMU_PMNCNT_MAX; j++) { + data->dmc[i].count[j] = __raw_readl( + ppmu_base + (0xf110 + (0x10 * j))); + data->dmc[i].count_overflow[j] = overflow & (1 << j); + } + } + + busfreq_mon_reset(data); +} + +static int exynos4x12_get_intspec(unsigned long mifclk) +{ + int i = 0; + + while (exynos4x12_intclk_table[i].clk) { + if (exynos4x12_intclk_table[i].clk <= mifclk) + return i; + i++; + } + + return -EINVAL; +} + +static int exynos4_bus_setvolt(struct busfreq_data *data, struct opp *opp, + struct opp *oldopp) +{ + int err = 0, tmp; + unsigned long volt = opp_get_voltage(opp); + + switch (data->type) { + case TYPE_BUSF_EXYNOS4210: + /* OPP represents DMC clock + INT voltage */ + err = regulator_set_voltage(data->vdd_int, volt, + MAX_SAFEVOLT); + break; + case TYPE_BUSF_EXYNOS4x12: + /* OPP represents MIF clock + MIF voltage */ + err = regulator_set_voltage(data->vdd_mif, volt, + MAX_SAFEVOLT); + if (err) + break; + + tmp = exynos4x12_get_intspec(opp_get_freq(opp)); + if (tmp < 0) { + err = tmp; + regulator_set_voltage(data->vdd_mif, + opp_get_voltage(oldopp), + MAX_SAFEVOLT); + break; + } + err = regulator_set_voltage(data->vdd_int, + exynos4x12_intclk_table[tmp].volt, + MAX_SAFEVOLT); + /* Try to recover */ + if (err) + regulator_set_voltage(data->vdd_mif, + opp_get_voltage(oldopp), + MAX_SAFEVOLT); + break; + default: + err = -EINVAL; + } + + return err; +} + +static int exynos4_bus_target(struct device *dev, unsigned long *_freq, + u32 flags) +{ + int err = 0; + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data *data = platform_get_drvdata(pdev); + struct opp *opp = devfreq_recommended_opp(dev, _freq, flags); + unsigned long freq = opp_get_freq(opp); + unsigned long old_freq = opp_get_freq(data->curr_opp); + + if (IS_ERR(opp)) + return PTR_ERR(opp); + + if (old_freq == freq) + return 0; + + dev_dbg(dev, "targetting %lukHz %luuV\n", freq, opp_get_voltage(opp)); + + mutex_lock(&data->lock); + + if (data->disabled) + goto out; + + if (old_freq < freq) + err = exynos4_bus_setvolt(data, opp, data->curr_opp); + if (err) + goto out; + + if (old_freq != freq) { + switch (data->type) { + case TYPE_BUSF_EXYNOS4210: + err = exynos4210_set_busclk(data, opp); + break; + case TYPE_BUSF_EXYNOS4x12: + err = exynos4x12_set_busclk(data, opp); + break; + default: + err = -EINVAL; + } + } + if (err) + goto out; + + if (old_freq > freq) + err = exynos4_bus_setvolt(data, opp, data->curr_opp); + if (err) + goto out; + + data->curr_opp = opp; +out: + mutex_unlock(&data->lock); + return err; +} + +static int exynos4_get_busier_dmc(struct busfreq_data *data) +{ + u64 p0 = data->dmc[0].count[0]; + u64 p1 = data->dmc[1].count[0]; + + p0 *= data->dmc[1].ccnt; + p1 *= data->dmc[0].ccnt; + + if (data->dmc[1].ccnt == 0) + return 0; + + if (p0 > p1) + return 0; + return 1; +} + +static int exynos4_bus_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct busfreq_data *data = dev_get_drvdata(dev); + int busier_dmc; + int cycles_x2 = 2; /* 2 x cycles */ + void __iomem *addr; + u32 timing; + u32 memctrl; + + exynos4_read_ppmu(data); + busier_dmc = exynos4_get_busier_dmc(data); + stat->current_frequency = opp_get_freq(data->curr_opp); + + if (busier_dmc) + addr = S5P_VA_DMC1; + else + addr = S5P_VA_DMC0; + + memctrl = __raw_readl(addr + 0x04); /* one of DDR2/3/LPDDR2 */ + timing = __raw_readl(addr + 0x38); /* CL or WL/RL values */ + + switch ((memctrl >> 8) & 0xf) { + case 0x4: /* DDR2 */ + cycles_x2 = ((timing >> 16) & 0xf) * 2; + break; + case 0x5: /* LPDDR2 */ + case 0x6: /* DDR3 */ + cycles_x2 = ((timing >> 8) & 0xf) + ((timing >> 0) & 0xf); + break; + default: + pr_err("%s: Unknown Memory Type(%d).\n", __func__, + (memctrl >> 8) & 0xf); + return -EINVAL; + } + + /* Number of cycles spent on memory access */ + stat->busy_time = data->dmc[busier_dmc].count[0] / 2 * (cycles_x2 + 2); + stat->busy_time *= 100 / BUS_SATURATION_RATIO; + stat->total_time = data->dmc[busier_dmc].ccnt; + + /* If the counters have overflown, retry */ + if (data->dmc[busier_dmc].ccnt_overflow || + data->dmc[busier_dmc].count_overflow[0]) + return -EAGAIN; + + return 0; +} + +static void exynos4_bus_exit(struct device *dev) +{ + struct busfreq_data *data = dev_get_drvdata(dev); + + devfreq_unregister_opp_notifier(dev, data->devfreq); +} + +static struct devfreq_dev_profile exynos4_devfreq_profile = { + .initial_freq = 400000, + .polling_ms = 50, + .target = exynos4_bus_target, + .get_dev_status = exynos4_bus_get_dev_status, + .exit = exynos4_bus_exit, +}; + +static int exynos4210_init_tables(struct busfreq_data *data) +{ + u32 tmp; + int mgrp; + int i, err = 0; + + tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); + for (i = LV_0; i < EX4210_LV_NUM; i++) { + tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | + EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK | + EXYNOS4_CLKDIV_DMC0_DPHY_MASK | + EXYNOS4_CLKDIV_DMC0_DMC_MASK | + EXYNOS4_CLKDIV_DMC0_DMCD_MASK | + EXYNOS4_CLKDIV_DMC0_DMCP_MASK | + EXYNOS4_CLKDIV_DMC0_COPY2_MASK | + EXYNOS4_CLKDIV_DMC0_CORETI_MASK); + + tmp |= ((exynos4210_clkdiv_dmc0[i][0] << + EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | + (exynos4210_clkdiv_dmc0[i][1] << + EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | + (exynos4210_clkdiv_dmc0[i][2] << + EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | + (exynos4210_clkdiv_dmc0[i][3] << + EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | + (exynos4210_clkdiv_dmc0[i][4] << + EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | + (exynos4210_clkdiv_dmc0[i][5] << + EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) | + (exynos4210_clkdiv_dmc0[i][6] << + EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) | + (exynos4210_clkdiv_dmc0[i][7] << + EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)); + + data->dmc_divtable[i] = tmp; + } + + tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); + for (i = LV_0; i < EX4210_LV_NUM; i++) { + tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK | + EXYNOS4_CLKDIV_TOP_ACLK100_MASK | + EXYNOS4_CLKDIV_TOP_ACLK160_MASK | + EXYNOS4_CLKDIV_TOP_ACLK133_MASK | + EXYNOS4_CLKDIV_TOP_ONENAND_MASK); + + tmp |= ((exynos4210_clkdiv_top[i][0] << + EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) | + (exynos4210_clkdiv_top[i][1] << + EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | + (exynos4210_clkdiv_top[i][2] << + EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | + (exynos4210_clkdiv_top[i][3] << + EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | + (exynos4210_clkdiv_top[i][4] << + EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)); + + data->top_divtable[i] = tmp; + } + +#ifdef CONFIG_EXYNOS_ASV + tmp = exynos4_result_of_asv; +#else + tmp = 0; /* Max voltages for the reliability of the unknown */ +#endif + + pr_debug("ASV Group of Exynos4 is %d\n", tmp); + /* Use merged grouping for voltage */ + switch (tmp) { + case 0: + mgrp = 0; + break; + case 1: + case 2: + mgrp = 1; + break; + case 3: + case 4: + mgrp = 2; + break; + case 5: + case 6: + mgrp = 3; + break; + case 7: + mgrp = 4; + break; + default: + pr_warn("Unknown ASV Group. Use max voltage.\n"); + mgrp = 0; + } + + for (i = LV_0; i < EX4210_LV_NUM; i++) + exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i]; + + for (i = LV_0; i < EX4210_LV_NUM; i++) { + err = opp_add(data->dev, exynos4210_busclk_table[i].clk, + exynos4210_busclk_table[i].volt); + if (err) { + dev_err(data->dev, "Cannot add opp entries.\n"); + return err; + } + } + + + return 0; +} + +static int exynos4x12_init_tables(struct busfreq_data *data) +{ + unsigned int i; + unsigned int tmp; + int ret; + + /* Enable pause function for DREX2 DVFS */ + tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL); + tmp |= EXYNOS4_DMC_PAUSE_ENABLE; + __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL); + + tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); + + for (i = 0; i < EX4x12_LV_NUM; i++) { + tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | + EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK | + EXYNOS4_CLKDIV_DMC0_DPHY_MASK | + EXYNOS4_CLKDIV_DMC0_DMC_MASK | + EXYNOS4_CLKDIV_DMC0_DMCD_MASK | + EXYNOS4_CLKDIV_DMC0_DMCP_MASK); + + tmp |= ((exynos4x12_clkdiv_dmc0[i][0] << + EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | + (exynos4x12_clkdiv_dmc0[i][1] << + EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | + (exynos4x12_clkdiv_dmc0[i][2] << + EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | + (exynos4x12_clkdiv_dmc0[i][3] << + EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | + (exynos4x12_clkdiv_dmc0[i][4] << + EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | + (exynos4x12_clkdiv_dmc0[i][5] << + EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)); + + data->dmc_divtable[i] = tmp; + } + +#ifdef CONFIG_EXYNOS_ASV + tmp = exynos4_result_of_asv; +#else + tmp = 0; /* Max voltages for the reliability of the unknown */ +#endif + + if (tmp > 8) + tmp = 0; + pr_debug("ASV Group of Exynos4x12 is %d\n", tmp); + + for (i = 0; i < EX4x12_LV_NUM; i++) { + exynos4x12_mifclk_table[i].volt = + exynos4x12_mif_step_50[tmp][i]; + exynos4x12_intclk_table[i].volt = + exynos4x12_int_volt[tmp][i]; + } + + for (i = 0; i < EX4x12_LV_NUM; i++) { + ret = opp_add(data->dev, exynos4x12_mifclk_table[i].clk, + exynos4x12_mifclk_table[i].volt); + if (ret) { + dev_err(data->dev, "Fail to add opp entries.\n"); + return ret; + } + } + + return 0; +} + +static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct busfreq_data *data = container_of(this, struct busfreq_data, + pm_notifier); + struct opp *opp; + unsigned long maxfreq = ULONG_MAX; + int err = 0; + + switch (event) { + case PM_SUSPEND_PREPARE: + /* Set Fastest and Deactivate DVFS */ + mutex_lock(&data->lock); + + data->disabled = true; + + opp = opp_find_freq_floor(data->dev, &maxfreq); + + err = exynos4_bus_setvolt(data, opp, data->curr_opp); + if (err) + goto unlock; + + switch (data->type) { + case TYPE_BUSF_EXYNOS4210: + err = exynos4210_set_busclk(data, opp); + break; + case TYPE_BUSF_EXYNOS4x12: + err = exynos4x12_set_busclk(data, opp); + break; + default: + err = -EINVAL; + } + if (err) + goto unlock; + + data->curr_opp = opp; +unlock: + mutex_unlock(&data->lock); + if (err) + return err; + return NOTIFY_OK; + case PM_POST_RESTORE: + case PM_POST_SUSPEND: + /* Reactivate */ + mutex_lock(&data->lock); + data->disabled = false; + mutex_unlock(&data->lock); + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +static __devinit int exynos4_busfreq_probe(struct platform_device *pdev) +{ + struct busfreq_data *data; + struct opp *opp; + struct device *dev = &pdev->dev; + int err = 0; + + data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data), GFP_KERNEL); + if (data == NULL) { + dev_err(dev, "Cannot allocate memory.\n"); + return -ENOMEM; + } + + data->type = pdev->id_entry->driver_data; + data->dmc[0].hw_base = S5P_VA_DMC0; + data->dmc[1].hw_base = S5P_VA_DMC1; + data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event; + data->dev = dev; + mutex_init(&data->lock); + + switch (data->type) { + case TYPE_BUSF_EXYNOS4210: + err = exynos4210_init_tables(data); + break; + case TYPE_BUSF_EXYNOS4x12: + err = exynos4x12_init_tables(data); + break; + default: + dev_err(dev, "Cannot determine the device id %d\n", data->type); + err = -EINVAL; + } + if (err) + return err; + + data->vdd_int = devm_regulator_get(dev, "vdd_int"); + if (IS_ERR(data->vdd_int)) { + dev_err(dev, "Cannot get the regulator \"vdd_int\"\n"); + return PTR_ERR(data->vdd_int); + } + if (data->type == TYPE_BUSF_EXYNOS4x12) { + data->vdd_mif = devm_regulator_get(dev, "vdd_mif"); + if (IS_ERR(data->vdd_mif)) { + dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n"); + return PTR_ERR(data->vdd_mif); + } + } + + opp = opp_find_freq_floor(dev, &exynos4_devfreq_profile.initial_freq); + if (IS_ERR(opp)) { + dev_err(dev, "Invalid initial frequency %lu kHz.\n", + exynos4_devfreq_profile.initial_freq); + return PTR_ERR(opp); + } + data->curr_opp = opp; + + platform_set_drvdata(pdev, data); + + busfreq_mon_reset(data); + + data->devfreq = devfreq_add_device(dev, &exynos4_devfreq_profile, + "simple_ondemand", NULL); + if (IS_ERR(data->devfreq)) + return PTR_ERR(data->devfreq); + + devfreq_register_opp_notifier(dev, data->devfreq); + + err = register_pm_notifier(&data->pm_notifier); + if (err) { + dev_err(dev, "Failed to setup pm notifier\n"); + devfreq_remove_device(data->devfreq); + return err; + } + + return 0; +} + +static __devexit int exynos4_busfreq_remove(struct platform_device *pdev) +{ + struct busfreq_data *data = platform_get_drvdata(pdev); + + unregister_pm_notifier(&data->pm_notifier); + devfreq_remove_device(data->devfreq); + + return 0; +} + +static int exynos4_busfreq_resume(struct device *dev) +{ + struct busfreq_data *data = dev_get_drvdata(dev); + + busfreq_mon_reset(data); + return 0; +} + +static const struct dev_pm_ops exynos4_busfreq_pm = { + .resume = exynos4_busfreq_resume, +}; + +static const struct platform_device_id exynos4_busfreq_id[] = { + { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 }, + { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 }, + { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 }, + { }, +}; + +static struct platform_driver exynos4_busfreq_driver = { + .probe = exynos4_busfreq_probe, + .remove = __devexit_p(exynos4_busfreq_remove), + .id_table = exynos4_busfreq_id, + .driver = { + .name = "exynos4-busfreq", + .owner = THIS_MODULE, + .pm = &exynos4_busfreq_pm, + }, +}; + +static int __init exynos4_busfreq_init(void) +{ + return platform_driver_register(&exynos4_busfreq_driver); +} +late_initcall(exynos4_busfreq_init); + +static void __exit exynos4_busfreq_exit(void) +{ + platform_driver_unregister(&exynos4_busfreq_driver); +} +module_exit(exynos4_busfreq_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework"); +MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>"); diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c deleted file mode 100644 index 7418372..0000000 --- a/drivers/devfreq/exynos4_bus.c +++ /dev/null @@ -1,1113 +0,0 @@ -/* drivers/devfreq/exynos4210_memorybus.c - * - * Copyright (c) 2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * MyungJoo Ham <myungjoo.ham@samsung.com> - * - * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework - * This version supports EXYNOS4210 only. This changes bus frequencies - * and vddint voltages. Exynos4412/4212 should be able to be supported - * with minor modifications. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - */ - -#include <linux/io.h> -#include <linux/slab.h> -#include <linux/mutex.h> -#include <linux/suspend.h> -#include <linux/opp.h> -#include <linux/devfreq.h> -#include <linux/platform_device.h> -#include <linux/regulator/consumer.h> -#include <linux/module.h> - -/* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */ -#ifdef CONFIG_EXYNOS_ASV -extern unsigned int exynos_result_of_asv; -#endif - -#include <mach/regs-clock.h> - -#include <plat/map-s5p.h> - -#define MAX_SAFEVOLT 1200000 /* 1.2V */ - -enum exynos4_busf_type { - TYPE_BUSF_EXYNOS4210, - TYPE_BUSF_EXYNOS4x12, -}; - -/* Assume that the bus is saturated if the utilization is 40% */ -#define BUS_SATURATION_RATIO 40 - -enum ppmu_counter { - PPMU_PMNCNT0 = 0, - PPMU_PMCCNT1, - PPMU_PMNCNT2, - PPMU_PMNCNT3, - PPMU_PMNCNT_MAX, -}; -struct exynos4_ppmu { - void __iomem *hw_base; - unsigned int ccnt; - unsigned int event; - unsigned int count[PPMU_PMNCNT_MAX]; - bool ccnt_overflow; - bool count_overflow[PPMU_PMNCNT_MAX]; -}; - -enum busclk_level_idx { - LV_0 = 0, - LV_1, - LV_2, - LV_3, - LV_4, - _LV_END -}; -#define EX4210_LV_MAX LV_2 -#define EX4x12_LV_MAX LV_4 -#define EX4210_LV_NUM (LV_2 + 1) -#define EX4x12_LV_NUM (LV_4 + 1) - -struct busfreq_data { - enum exynos4_busf_type type; - struct device *dev; - struct devfreq *devfreq; - bool disabled; - struct regulator *vdd_int; - struct regulator *vdd_mif; /* Exynos4412/4212 only */ - struct opp *curr_opp; - struct exynos4_ppmu dmc[2]; - - struct notifier_block pm_notifier; - struct mutex lock; - - /* Dividers calculated at boot/probe-time */ - unsigned int dmc_divtable[_LV_END]; /* DMC0 */ - unsigned int top_divtable[_LV_END]; -}; - -struct bus_opp_table { - unsigned int idx; - unsigned long clk; - unsigned long volt; -}; - -/* 4210 controls clock of mif and voltage of int */ -static struct bus_opp_table exynos4210_busclk_table[] = { - {LV_0, 400000, 1150000}, - {LV_1, 267000, 1050000}, - {LV_2, 133000, 1025000}, - {0, 0, 0}, -}; - -/* - * MIF is the main control knob clock for exynox4x12 MIF/INT - * clock and voltage of both mif/int are controlled. - */ -static struct bus_opp_table exynos4x12_mifclk_table[] = { - {LV_0, 400000, 1100000}, - {LV_1, 267000, 1000000}, - {LV_2, 160000, 950000}, - {LV_3, 133000, 950000}, - {LV_4, 100000, 950000}, - {0, 0, 0}, -}; - -/* - * INT is not the control knob of 4x12. LV_x is not meant to represent - * the current performance. (MIF does) - */ -static struct bus_opp_table exynos4x12_intclk_table[] = { - {LV_0, 200000, 1000000}, - {LV_1, 160000, 950000}, - {LV_2, 133000, 925000}, - {LV_3, 100000, 900000}, - {0, 0, 0}, -}; - -/* TODO: asv volt definitions are "__initdata"? */ -/* Some chips have different operating voltages */ -static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = { - {1150000, 1050000, 1050000}, - {1125000, 1025000, 1025000}, - {1100000, 1000000, 1000000}, - {1075000, 975000, 975000}, - {1050000, 950000, 950000}, -}; - -static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = { - /* 400 267 160 133 100 */ - {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */ - {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */ - {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */ - {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */ - {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */ - {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */ - {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */ - {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */ - {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */ -}; - -static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = { - /* 200 160 133 100 */ - {1000000, 950000, 925000, 900000}, /* ASV0 */ - {975000, 925000, 925000, 900000}, /* ASV1 */ - {950000, 925000, 900000, 875000}, /* ASV2 */ - {950000, 900000, 900000, 875000}, /* ASV3 */ - {925000, 875000, 875000, 875000}, /* ASV4 */ - {900000, 850000, 850000, 850000}, /* ASV5 */ - {900000, 850000, 850000, 850000}, /* ASV6 */ - {900000, 850000, 850000, 850000}, /* ASV7 */ - {900000, 850000, 850000, 850000}, /* ASV8 */ -}; - -/*** Clock Divider Data for Exynos4210 ***/ -static unsigned int exynos4210_clkdiv_dmc0[][8] = { - /* - * Clock divider value for following - * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD - * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS } - */ - - /* DMC L0: 400MHz */ - { 3, 1, 1, 1, 1, 1, 3, 1 }, - /* DMC L1: 266.7MHz */ - { 4, 1, 1, 2, 1, 1, 3, 1 }, - /* DMC L2: 133MHz */ - { 5, 1, 1, 5, 1, 1, 3, 1 }, -}; -static unsigned int exynos4210_clkdiv_top[][5] = { - /* - * Clock divider value for following - * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND } - */ - /* ACLK200 L0: 200MHz */ - { 3, 7, 4, 5, 1 }, - /* ACLK200 L1: 160MHz */ - { 4, 7, 5, 6, 1 }, - /* ACLK200 L2: 133MHz */ - { 5, 7, 7, 7, 1 }, -}; -static unsigned int exynos4210_clkdiv_lr_bus[][2] = { - /* - * Clock divider value for following - * { DIVGDL/R, DIVGPL/R } - */ - /* ACLK_GDL/R L1: 200MHz */ - { 3, 1 }, - /* ACLK_GDL/R L2: 160MHz */ - { 4, 1 }, - /* ACLK_GDL/R L3: 133MHz */ - { 5, 1 }, -}; - -/*** Clock Divider Data for Exynos4212/4412 ***/ -static unsigned int exynos4x12_clkdiv_dmc0[][6] = { - /* - * Clock divider value for following - * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD - * DIVDMCP} - */ - - /* DMC L0: 400MHz */ - {3, 1, 1, 1, 1, 1}, - /* DMC L1: 266.7MHz */ - {4, 1, 1, 2, 1, 1}, - /* DMC L2: 160MHz */ - {5, 1, 1, 4, 1, 1}, - /* DMC L3: 133MHz */ - {5, 1, 1, 5, 1, 1}, - /* DMC L4: 100MHz */ - {7, 1, 1, 7, 1, 1}, -}; -static unsigned int exynos4x12_clkdiv_dmc1[][6] = { - /* - * Clock divider value for following - * { G2DACP, DIVC2C, DIVC2C_ACLK } - */ - - /* DMC L0: 400MHz */ - {3, 1, 1}, - /* DMC L1: 266.7MHz */ - {4, 2, 1}, - /* DMC L2: 160MHz */ - {5, 4, 1}, - /* DMC L3: 133MHz */ - {5, 5, 1}, - /* DMC L4: 100MHz */ - {7, 7, 1}, -}; -static unsigned int exynos4x12_clkdiv_top[][5] = { - /* - * Clock divider value for following - * { DIVACLK266_GPS, DIVACLK100, DIVACLK160, - DIVACLK133, DIVONENAND } - */ - - /* ACLK_GDL/R L0: 200MHz */ - {2, 7, 4, 5, 1}, - /* ACLK_GDL/R L1: 200MHz */ - {2, 7, 4, 5, 1}, - /* ACLK_GDL/R L2: 160MHz */ - {4, 7, 5, 7, 1}, - /* ACLK_GDL/R L3: 133MHz */ - {4, 7, 5, 7, 1}, - /* ACLK_GDL/R L4: 100MHz */ - {7, 7, 7, 7, 1}, -}; -static unsigned int exynos4x12_clkdiv_lr_bus[][2] = { - /* - * Clock divider value for following - * { DIVGDL/R, DIVGPL/R } - */ - - /* ACLK_GDL/R L0: 200MHz */ - {3, 1}, - /* ACLK_GDL/R L1: 200MHz */ - {3, 1}, - /* ACLK_GDL/R L2: 160MHz */ - {4, 1}, - /* ACLK_GDL/R L3: 133MHz */ - {5, 1}, - /* ACLK_GDL/R L4: 100MHz */ - {7, 1}, -}; -static unsigned int exynos4x12_clkdiv_sclkip[][3] = { - /* - * Clock divider value for following - * { DIVMFC, DIVJPEG, DIVFIMC0~3} - */ - - /* SCLK_MFC: 200MHz */ - {3, 3, 4}, - /* SCLK_MFC: 200MHz */ - {3, 3, 4}, - /* SCLK_MFC: 160MHz */ - {4, 4, 5}, - /* SCLK_MFC: 133MHz */ - {5, 5, 5}, - /* SCLK_MFC: 100MHz */ - {7, 7, 7}, -}; - - -static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp) -{ - unsigned int index; - unsigned int tmp; - - for (index = LV_0; index < EX4210_LV_NUM; index++) - if (opp_get_freq(opp) == exynos4210_busclk_table[index].clk) - break; - - if (index == EX4210_LV_NUM) - return -EINVAL; - - /* Change Divider - DMC0 */ - tmp = data->dmc_divtable[index]; - - __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); - } while (tmp & 0x11111111); - - /* Change Divider - TOP */ - tmp = data->top_divtable[index]; - - __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); - } while (tmp & 0x11111); - - /* Change Divider - LEFTBUS */ - tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); - - tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); - - tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << - EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | - (exynos4210_clkdiv_lr_bus[index][1] << - EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); - - __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); - } while (tmp & 0x11); - - /* Change Divider - RIGHTBUS */ - tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); - - tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); - - tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << - EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | - (exynos4210_clkdiv_lr_bus[index][1] << - EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); - - __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); - } while (tmp & 0x11); - - return 0; -} - -static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp) -{ - unsigned int index; - unsigned int tmp; - - for (index = LV_0; index < EX4x12_LV_NUM; index++) - if (opp_get_freq(opp) == exynos4x12_mifclk_table[index].clk) - break; - - if (index == EX4x12_LV_NUM) - return -EINVAL; - - /* Change Divider - DMC0 */ - tmp = data->dmc_divtable[index]; - - __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); - } while (tmp & 0x11111111); - - /* Change Divider - DMC1 */ - tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1); - - tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK | - EXYNOS4_CLKDIV_DMC1_C2C_MASK | - EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK); - - tmp |= ((exynos4x12_clkdiv_dmc1[index][0] << - EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) | - (exynos4x12_clkdiv_dmc1[index][1] << - EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) | - (exynos4x12_clkdiv_dmc1[index][2] << - EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)); - - __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1); - } while (tmp & 0x111111); - - /* Change Divider - TOP */ - tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); - - tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK | - EXYNOS4_CLKDIV_TOP_ACLK100_MASK | - EXYNOS4_CLKDIV_TOP_ACLK160_MASK | - EXYNOS4_CLKDIV_TOP_ACLK133_MASK | - EXYNOS4_CLKDIV_TOP_ONENAND_MASK); - - tmp |= ((exynos4x12_clkdiv_top[index][0] << - EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) | - (exynos4x12_clkdiv_top[index][1] << - EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | - (exynos4x12_clkdiv_top[index][2] << - EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | - (exynos4x12_clkdiv_top[index][3] << - EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | - (exynos4x12_clkdiv_top[index][4] << - EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)); - - __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); - } while (tmp & 0x11111); - - /* Change Divider - LEFTBUS */ - tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); - - tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); - - tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << - EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | - (exynos4x12_clkdiv_lr_bus[index][1] << - EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); - - __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); - } while (tmp & 0x11); - - /* Change Divider - RIGHTBUS */ - tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); - - tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); - - tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << - EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | - (exynos4x12_clkdiv_lr_bus[index][1] << - EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); - - __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); - } while (tmp & 0x11); - - /* Change Divider - MFC */ - tmp = __raw_readl(EXYNOS4_CLKDIV_MFC); - - tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK); - - tmp |= ((exynos4x12_clkdiv_sclkip[index][0] << - EXYNOS4_CLKDIV_MFC_SHIFT)); - - __raw_writel(tmp, EXYNOS4_CLKDIV_MFC); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC); - } while (tmp & 0x1); - - /* Change Divider - JPEG */ - tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1); - - tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK); - - tmp |= ((exynos4x12_clkdiv_sclkip[index][1] << - EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)); - - __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); - } while (tmp & 0x1); - - /* Change Divider - FIMC0~3 */ - tmp = __raw_readl(EXYNOS4_CLKDIV_CAM); - - tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK | - EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK); - - tmp |= ((exynos4x12_clkdiv_sclkip[index][2] << - EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) | - (exynos4x12_clkdiv_sclkip[index][2] << - EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) | - (exynos4x12_clkdiv_sclkip[index][2] << - EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) | - (exynos4x12_clkdiv_sclkip[index][2] << - EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)); - - __raw_writel(tmp, EXYNOS4_CLKDIV_CAM); - - do { - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); - } while (tmp & 0x1111); - - return 0; -} - - -static void busfreq_mon_reset(struct busfreq_data *data) -{ - unsigned int i; - - for (i = 0; i < 2; i++) { - void __iomem *ppmu_base = data->dmc[i].hw_base; - - /* Reset PPMU */ - __raw_writel(0x8000000f, ppmu_base + 0xf010); - __raw_writel(0x8000000f, ppmu_base + 0xf050); - __raw_writel(0x6, ppmu_base + 0xf000); - __raw_writel(0x0, ppmu_base + 0xf100); - - /* Set PPMU Event */ - data->dmc[i].event = 0x6; - __raw_writel(((data->dmc[i].event << 12) | 0x1), - ppmu_base + 0xfc); - - /* Start PPMU */ - __raw_writel(0x1, ppmu_base + 0xf000); - } -} - -static void exynos4_read_ppmu(struct busfreq_data *data) -{ - int i, j; - - for (i = 0; i < 2; i++) { - void __iomem *ppmu_base = data->dmc[i].hw_base; - u32 overflow; - - /* Stop PPMU */ - __raw_writel(0x0, ppmu_base + 0xf000); - - /* Update local data from PPMU */ - overflow = __raw_readl(ppmu_base + 0xf050); - - data->dmc[i].ccnt = __raw_readl(ppmu_base + 0xf100); - data->dmc[i].ccnt_overflow = overflow & (1 << 31); - - for (j = 0; j < PPMU_PMNCNT_MAX; j++) { - data->dmc[i].count[j] = __raw_readl( - ppmu_base + (0xf110 + (0x10 * j))); - data->dmc[i].count_overflow[j] = overflow & (1 << j); - } - } - - busfreq_mon_reset(data); -} - -static int exynos4x12_get_intspec(unsigned long mifclk) -{ - int i = 0; - - while (exynos4x12_intclk_table[i].clk) { - if (exynos4x12_intclk_table[i].clk <= mifclk) - return i; - i++; - } - - return -EINVAL; -} - -static int exynos4_bus_setvolt(struct busfreq_data *data, struct opp *opp, - struct opp *oldopp) -{ - int err = 0, tmp; - unsigned long volt = opp_get_voltage(opp); - - switch (data->type) { - case TYPE_BUSF_EXYNOS4210: - /* OPP represents DMC clock + INT voltage */ - err = regulator_set_voltage(data->vdd_int, volt, - MAX_SAFEVOLT); - break; - case TYPE_BUSF_EXYNOS4x12: - /* OPP represents MIF clock + MIF voltage */ - err = regulator_set_voltage(data->vdd_mif, volt, - MAX_SAFEVOLT); - if (err) - break; - - tmp = exynos4x12_get_intspec(opp_get_freq(opp)); - if (tmp < 0) { - err = tmp; - regulator_set_voltage(data->vdd_mif, - opp_get_voltage(oldopp), - MAX_SAFEVOLT); - break; - } - err = regulator_set_voltage(data->vdd_int, - exynos4x12_intclk_table[tmp].volt, - MAX_SAFEVOLT); - /* Try to recover */ - if (err) - regulator_set_voltage(data->vdd_mif, - opp_get_voltage(oldopp), - MAX_SAFEVOLT); - break; - default: - err = -EINVAL; - } - - return err; -} - -static int exynos4_bus_target(struct device *dev, unsigned long *_freq, - u32 flags) -{ - int err = 0; - struct platform_device *pdev = container_of(dev, struct platform_device, - dev); - struct busfreq_data *data = platform_get_drvdata(pdev); - struct opp *opp = devfreq_recommended_opp(dev, _freq, flags); - unsigned long freq = opp_get_freq(opp); - unsigned long old_freq = opp_get_freq(data->curr_opp); - - if (IS_ERR(opp)) - return PTR_ERR(opp); - - if (old_freq == freq) - return 0; - - dev_dbg(dev, "targetting %lukHz %luuV\n", freq, opp_get_voltage(opp)); - - mutex_lock(&data->lock); - - if (data->disabled) - goto out; - - if (old_freq < freq) - err = exynos4_bus_setvolt(data, opp, data->curr_opp); - if (err) - goto out; - - if (old_freq != freq) { - switch (data->type) { - case TYPE_BUSF_EXYNOS4210: - err = exynos4210_set_busclk(data, opp); - break; - case TYPE_BUSF_EXYNOS4x12: - err = exynos4x12_set_busclk(data, opp); - break; - default: - err = -EINVAL; - } - } - if (err) - goto out; - - if (old_freq > freq) - err = exynos4_bus_setvolt(data, opp, data->curr_opp); - if (err) - goto out; - - data->curr_opp = opp; -out: - mutex_unlock(&data->lock); - return err; -} - -static int exynos4_get_busier_dmc(struct busfreq_data *data) -{ - u64 p0 = data->dmc[0].count[0]; - u64 p1 = data->dmc[1].count[0]; - - p0 *= data->dmc[1].ccnt; - p1 *= data->dmc[0].ccnt; - - if (data->dmc[1].ccnt == 0) - return 0; - - if (p0 > p1) - return 0; - return 1; -} - -static int exynos4_bus_get_dev_status(struct device *dev, - struct devfreq_dev_status *stat) -{ - struct busfreq_data *data = dev_get_drvdata(dev); - int busier_dmc; - int cycles_x2 = 2; /* 2 x cycles */ - void __iomem *addr; - u32 timing; - u32 memctrl; - - exynos4_read_ppmu(data); - busier_dmc = exynos4_get_busier_dmc(data); - stat->current_frequency = opp_get_freq(data->curr_opp); - - if (busier_dmc) - addr = S5P_VA_DMC1; - else - addr = S5P_VA_DMC0; - - memctrl = __raw_readl(addr + 0x04); /* one of DDR2/3/LPDDR2 */ - timing = __raw_readl(addr + 0x38); /* CL or WL/RL values */ - - switch ((memctrl >> 8) & 0xf) { - case 0x4: /* DDR2 */ - cycles_x2 = ((timing >> 16) & 0xf) * 2; - break; - case 0x5: /* LPDDR2 */ - case 0x6: /* DDR3 */ - cycles_x2 = ((timing >> 8) & 0xf) + ((timing >> 0) & 0xf); - break; - default: - pr_err("%s: Unknown Memory Type(%d).\n", __func__, - (memctrl >> 8) & 0xf); - return -EINVAL; - } - - /* Number of cycles spent on memory access */ - stat->busy_time = data->dmc[busier_dmc].count[0] / 2 * (cycles_x2 + 2); - stat->busy_time *= 100 / BUS_SATURATION_RATIO; - stat->total_time = data->dmc[busier_dmc].ccnt; - - /* If the counters have overflown, retry */ - if (data->dmc[busier_dmc].ccnt_overflow || - data->dmc[busier_dmc].count_overflow[0]) - return -EAGAIN; - - return 0; -} - -static void exynos4_bus_exit(struct device *dev) -{ - struct busfreq_data *data = dev_get_drvdata(dev); - - devfreq_unregister_opp_notifier(dev, data->devfreq); -} - -static struct devfreq_dev_profile exynos4_devfreq_profile = { - .initial_freq = 400000, - .polling_ms = 50, - .target = exynos4_bus_target, - .get_dev_status = exynos4_bus_get_dev_status, - .exit = exynos4_bus_exit, -}; - -static int exynos4210_init_tables(struct busfreq_data *data) -{ - u32 tmp; - int mgrp; - int i, err = 0; - - tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); - for (i = LV_0; i < EX4210_LV_NUM; i++) { - tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | - EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK | - EXYNOS4_CLKDIV_DMC0_DPHY_MASK | - EXYNOS4_CLKDIV_DMC0_DMC_MASK | - EXYNOS4_CLKDIV_DMC0_DMCD_MASK | - EXYNOS4_CLKDIV_DMC0_DMCP_MASK | - EXYNOS4_CLKDIV_DMC0_COPY2_MASK | - EXYNOS4_CLKDIV_DMC0_CORETI_MASK); - - tmp |= ((exynos4210_clkdiv_dmc0[i][0] << - EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | - (exynos4210_clkdiv_dmc0[i][1] << - EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | - (exynos4210_clkdiv_dmc0[i][2] << - EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | - (exynos4210_clkdiv_dmc0[i][3] << - EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | - (exynos4210_clkdiv_dmc0[i][4] << - EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | - (exynos4210_clkdiv_dmc0[i][5] << - EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) | - (exynos4210_clkdiv_dmc0[i][6] << - EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) | - (exynos4210_clkdiv_dmc0[i][7] << - EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)); - - data->dmc_divtable[i] = tmp; - } - - tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); - for (i = LV_0; i < EX4210_LV_NUM; i++) { - tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK | - EXYNOS4_CLKDIV_TOP_ACLK100_MASK | - EXYNOS4_CLKDIV_TOP_ACLK160_MASK | - EXYNOS4_CLKDIV_TOP_ACLK133_MASK | - EXYNOS4_CLKDIV_TOP_ONENAND_MASK); - - tmp |= ((exynos4210_clkdiv_top[i][0] << - EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) | - (exynos4210_clkdiv_top[i][1] << - EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | - (exynos4210_clkdiv_top[i][2] << - EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | - (exynos4210_clkdiv_top[i][3] << - EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | - (exynos4210_clkdiv_top[i][4] << - EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)); - - data->top_divtable[i] = tmp; - } - -#ifdef CONFIG_EXYNOS_ASV - tmp = exynos4_result_of_asv; -#else - tmp = 0; /* Max voltages for the reliability of the unknown */ -#endif - - pr_debug("ASV Group of Exynos4 is %d\n", tmp); - /* Use merged grouping for voltage */ - switch (tmp) { - case 0: - mgrp = 0; - break; - case 1: - case 2: - mgrp = 1; - break; - case 3: - case 4: - mgrp = 2; - break; - case 5: - case 6: - mgrp = 3; - break; - case 7: - mgrp = 4; - break; - default: - pr_warn("Unknown ASV Group. Use max voltage.\n"); - mgrp = 0; - } - - for (i = LV_0; i < EX4210_LV_NUM; i++) - exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i]; - - for (i = LV_0; i < EX4210_LV_NUM; i++) { - err = opp_add(data->dev, exynos4210_busclk_table[i].clk, - exynos4210_busclk_table[i].volt); - if (err) { - dev_err(data->dev, "Cannot add opp entries.\n"); - return err; - } - } - - - return 0; -} - -static int exynos4x12_init_tables(struct busfreq_data *data) -{ - unsigned int i; - unsigned int tmp; - int ret; - - /* Enable pause function for DREX2 DVFS */ - tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL); - tmp |= EXYNOS4_DMC_PAUSE_ENABLE; - __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL); - - tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); - - for (i = 0; i < EX4x12_LV_NUM; i++) { - tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | - EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK | - EXYNOS4_CLKDIV_DMC0_DPHY_MASK | - EXYNOS4_CLKDIV_DMC0_DMC_MASK | - EXYNOS4_CLKDIV_DMC0_DMCD_MASK | - EXYNOS4_CLKDIV_DMC0_DMCP_MASK); - - tmp |= ((exynos4x12_clkdiv_dmc0[i][0] << - EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | - (exynos4x12_clkdiv_dmc0[i][1] << - EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | - (exynos4x12_clkdiv_dmc0[i][2] << - EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | - (exynos4x12_clkdiv_dmc0[i][3] << - EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | - (exynos4x12_clkdiv_dmc0[i][4] << - EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | - (exynos4x12_clkdiv_dmc0[i][5] << - EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)); - - data->dmc_divtable[i] = tmp; - } - -#ifdef CONFIG_EXYNOS_ASV - tmp = exynos4_result_of_asv; -#else - tmp = 0; /* Max voltages for the reliability of the unknown */ -#endif - - if (tmp > 8) - tmp = 0; - pr_debug("ASV Group of Exynos4x12 is %d\n", tmp); - - for (i = 0; i < EX4x12_LV_NUM; i++) { - exynos4x12_mifclk_table[i].volt = - exynos4x12_mif_step_50[tmp][i]; - exynos4x12_intclk_table[i].volt = - exynos4x12_int_volt[tmp][i]; - } - - for (i = 0; i < EX4x12_LV_NUM; i++) { - ret = opp_add(data->dev, exynos4x12_mifclk_table[i].clk, - exynos4x12_mifclk_table[i].volt); - if (ret) { - dev_err(data->dev, "Fail to add opp entries.\n"); - return ret; - } - } - - return 0; -} - -static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this, - unsigned long event, void *ptr) -{ - struct busfreq_data *data = container_of(this, struct busfreq_data, - pm_notifier); - struct opp *opp; - unsigned long maxfreq = ULONG_MAX; - int err = 0; - - switch (event) { - case PM_SUSPEND_PREPARE: - /* Set Fastest and Deactivate DVFS */ - mutex_lock(&data->lock); - - data->disabled = true; - - opp = opp_find_freq_floor(data->dev, &maxfreq); - - err = exynos4_bus_setvolt(data, opp, data->curr_opp); - if (err) - goto unlock; - - switch (data->type) { - case TYPE_BUSF_EXYNOS4210: - err = exynos4210_set_busclk(data, opp); - break; - case TYPE_BUSF_EXYNOS4x12: - err = exynos4x12_set_busclk(data, opp); - break; - default: - err = -EINVAL; - } - if (err) - goto unlock; - - data->curr_opp = opp; -unlock: - mutex_unlock(&data->lock); - if (err) - return err; - return NOTIFY_OK; - case PM_POST_RESTORE: - case PM_POST_SUSPEND: - /* Reactivate */ - mutex_lock(&data->lock); - data->disabled = false; - mutex_unlock(&data->lock); - return NOTIFY_OK; - } - - return NOTIFY_DONE; -} - -static __devinit int exynos4_busfreq_probe(struct platform_device *pdev) -{ - struct busfreq_data *data; - struct opp *opp; - struct device *dev = &pdev->dev; - int err = 0; - - data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data), GFP_KERNEL); - if (data == NULL) { - dev_err(dev, "Cannot allocate memory.\n"); - return -ENOMEM; - } - - data->type = pdev->id_entry->driver_data; - data->dmc[0].hw_base = S5P_VA_DMC0; - data->dmc[1].hw_base = S5P_VA_DMC1; - data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event; - data->dev = dev; - mutex_init(&data->lock); - - switch (data->type) { - case TYPE_BUSF_EXYNOS4210: - err = exynos4210_init_tables(data); - break; - case TYPE_BUSF_EXYNOS4x12: - err = exynos4x12_init_tables(data); - break; - default: - dev_err(dev, "Cannot determine the device id %d\n", data->type); - err = -EINVAL; - } - if (err) - return err; - - data->vdd_int = devm_regulator_get(dev, "vdd_int"); - if (IS_ERR(data->vdd_int)) { - dev_err(dev, "Cannot get the regulator \"vdd_int\"\n"); - return PTR_ERR(data->vdd_int); - } - if (data->type == TYPE_BUSF_EXYNOS4x12) { - data->vdd_mif = devm_regulator_get(dev, "vdd_mif"); - if (IS_ERR(data->vdd_mif)) { - dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n"); - return PTR_ERR(data->vdd_mif); - } - } - - opp = opp_find_freq_floor(dev, &exynos4_devfreq_profile.initial_freq); - if (IS_ERR(opp)) { - dev_err(dev, "Invalid initial frequency %lu kHz.\n", - exynos4_devfreq_profile.initial_freq); - return PTR_ERR(opp); - } - data->curr_opp = opp; - - platform_set_drvdata(pdev, data); - - busfreq_mon_reset(data); - - data->devfreq = devfreq_add_device(dev, &exynos4_devfreq_profile, - "simple_ondemand", NULL); - if (IS_ERR(data->devfreq)) - return PTR_ERR(data->devfreq); - - devfreq_register_opp_notifier(dev, data->devfreq); - - err = register_pm_notifier(&data->pm_notifier); - if (err) { - dev_err(dev, "Failed to setup pm notifier\n"); - devfreq_remove_device(data->devfreq); - return err; - } - - return 0; -} - -static __devexit int exynos4_busfreq_remove(struct platform_device *pdev) -{ - struct busfreq_data *data = platform_get_drvdata(pdev); - - unregister_pm_notifier(&data->pm_notifier); - devfreq_remove_device(data->devfreq); - - return 0; -} - -static int exynos4_busfreq_resume(struct device *dev) -{ - struct busfreq_data *data = dev_get_drvdata(dev); - - busfreq_mon_reset(data); - return 0; -} - -static const struct dev_pm_ops exynos4_busfreq_pm = { - .resume = exynos4_busfreq_resume, -}; - -static const struct platform_device_id exynos4_busfreq_id[] = { - { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 }, - { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 }, - { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 }, - { }, -}; - -static struct platform_driver exynos4_busfreq_driver = { - .probe = exynos4_busfreq_probe, - .remove = __devexit_p(exynos4_busfreq_remove), - .id_table = exynos4_busfreq_id, - .driver = { - .name = "exynos4-busfreq", - .owner = THIS_MODULE, - .pm = &exynos4_busfreq_pm, - }, -}; - -static int __init exynos4_busfreq_init(void) -{ - return platform_driver_register(&exynos4_busfreq_driver); -} -late_initcall(exynos4_busfreq_init); - -static void __exit exynos4_busfreq_exit(void) -{ - platform_driver_unregister(&exynos4_busfreq_driver); -} -module_exit(exynos4_busfreq_exit); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework"); -MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>"); -- 1.7.8.6 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 3/4] PM: DEVFREQ: Move exynos4 devfreq driver into a new sub-directory 2013-01-09 12:06 ` [PATCH 3/4] PM: DEVFREQ: Move exynos4 devfreq driver into a new sub-directory Abhilash Kesavan @ 2013-01-14 14:30 ` MyungJoo Ham 2013-01-18 13:24 ` [PATCH v4 " Abhilash Kesavan 1 sibling, 0 replies; 18+ messages in thread From: MyungJoo Ham @ 2013-01-14 14:30 UTC (permalink / raw) To: Abhilash Kesavan Cc: linux-kernel, linux-pm, kgene.kim, kyungmin.park, rjw, jhbird.choi On Wed, Jan 9, 2013 at 9:06 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote: > In anticipation of the new exynos5 devfreq and ppmu driver, create > an exynos sub-directory. Move the existing exynos4 devfreq driver > into the same. > > Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> > Cc: Jonghwan Choi <jhbird.choi@samsung.com> > Cc: Kukjin Kim <kgene.kim@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Thanks for organizing this up. > --- > drivers/devfreq/Makefile | 2 +- > drivers/devfreq/exynos/Makefile | 2 + > drivers/devfreq/exynos/exynos4_bus.c | 1113 ++++++++++++++++++++++++++++++++++ > drivers/devfreq/exynos4_bus.c | 1113 ---------------------------------- > 4 files changed, 1116 insertions(+), 1114 deletions(-) > create mode 100644 drivers/devfreq/exynos/Makefile > create mode 100644 drivers/devfreq/exynos/exynos4_bus.c > delete mode 100644 drivers/devfreq/exynos4_bus.c > > diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile > index 8c46423..3bc1fef 100644 > --- a/drivers/devfreq/Makefile > +++ b/drivers/devfreq/Makefile > @@ -5,4 +5,4 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o > obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o > > # DEVFREQ Drivers > -obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o > +obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/ > diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile > new file mode 100644 > index 0000000..1498823 > --- /dev/null > +++ b/drivers/devfreq/exynos/Makefile > @@ -0,0 +1,2 @@ > +# Exynos DEVFREQ Drivers > +obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o > diff --git a/drivers/devfreq/exynos/exynos4_bus.c b/drivers/devfreq/exynos/exynos4_bus.c > new file mode 100644 > index 0000000..7418372 > --- /dev/null > +++ b/drivers/devfreq/exynos/exynos4_bus.c > @@ -0,0 +1,1113 @@ > +/* drivers/devfreq/exynos4210_memorybus.c > + * > + * Copyright (c) 2011 Samsung Electronics Co., Ltd. > + * http://www.samsung.com/ > + * MyungJoo Ham <myungjoo.ham@samsung.com> > + * > + * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework > + * This version supports EXYNOS4210 only. This changes bus frequencies > + * and vddint voltages. Exynos4412/4212 should be able to be supported > + * with minor modifications. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#include <linux/io.h> > +#include <linux/slab.h> > +#include <linux/mutex.h> > +#include <linux/suspend.h> > +#include <linux/opp.h> > +#include <linux/devfreq.h> > +#include <linux/platform_device.h> > +#include <linux/regulator/consumer.h> > +#include <linux/module.h> > + > +/* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */ > +#ifdef CONFIG_EXYNOS_ASV > +extern unsigned int exynos_result_of_asv; > +#endif > + > +#include <mach/regs-clock.h> > + > +#include <plat/map-s5p.h> > + > +#define MAX_SAFEVOLT 1200000 /* 1.2V */ > + > +enum exynos4_busf_type { > + TYPE_BUSF_EXYNOS4210, > + TYPE_BUSF_EXYNOS4x12, > +}; > + > +/* Assume that the bus is saturated if the utilization is 40% */ > +#define BUS_SATURATION_RATIO 40 > + > +enum ppmu_counter { > + PPMU_PMNCNT0 = 0, > + PPMU_PMCCNT1, > + PPMU_PMNCNT2, > + PPMU_PMNCNT3, > + PPMU_PMNCNT_MAX, > +}; > +struct exynos4_ppmu { > + void __iomem *hw_base; > + unsigned int ccnt; > + unsigned int event; > + unsigned int count[PPMU_PMNCNT_MAX]; > + bool ccnt_overflow; > + bool count_overflow[PPMU_PMNCNT_MAX]; > +}; > + > +enum busclk_level_idx { > + LV_0 = 0, > + LV_1, > + LV_2, > + LV_3, > + LV_4, > + _LV_END > +}; > +#define EX4210_LV_MAX LV_2 > +#define EX4x12_LV_MAX LV_4 > +#define EX4210_LV_NUM (LV_2 + 1) > +#define EX4x12_LV_NUM (LV_4 + 1) > + > +struct busfreq_data { > + enum exynos4_busf_type type; > + struct device *dev; > + struct devfreq *devfreq; > + bool disabled; > + struct regulator *vdd_int; > + struct regulator *vdd_mif; /* Exynos4412/4212 only */ > + struct opp *curr_opp; > + struct exynos4_ppmu dmc[2]; > + > + struct notifier_block pm_notifier; > + struct mutex lock; > + > + /* Dividers calculated at boot/probe-time */ > + unsigned int dmc_divtable[_LV_END]; /* DMC0 */ > + unsigned int top_divtable[_LV_END]; > +}; > + > +struct bus_opp_table { > + unsigned int idx; > + unsigned long clk; > + unsigned long volt; > +}; > + > +/* 4210 controls clock of mif and voltage of int */ > +static struct bus_opp_table exynos4210_busclk_table[] = { > + {LV_0, 400000, 1150000}, > + {LV_1, 267000, 1050000}, > + {LV_2, 133000, 1025000}, > + {0, 0, 0}, > +}; > + > +/* > + * MIF is the main control knob clock for exynox4x12 MIF/INT > + * clock and voltage of both mif/int are controlled. > + */ > +static struct bus_opp_table exynos4x12_mifclk_table[] = { > + {LV_0, 400000, 1100000}, > + {LV_1, 267000, 1000000}, > + {LV_2, 160000, 950000}, > + {LV_3, 133000, 950000}, > + {LV_4, 100000, 950000}, > + {0, 0, 0}, > +}; > + > +/* > + * INT is not the control knob of 4x12. LV_x is not meant to represent > + * the current performance. (MIF does) > + */ > +static struct bus_opp_table exynos4x12_intclk_table[] = { > + {LV_0, 200000, 1000000}, > + {LV_1, 160000, 950000}, > + {LV_2, 133000, 925000}, > + {LV_3, 100000, 900000}, > + {0, 0, 0}, > +}; > + > +/* TODO: asv volt definitions are "__initdata"? */ > +/* Some chips have different operating voltages */ > +static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = { > + {1150000, 1050000, 1050000}, > + {1125000, 1025000, 1025000}, > + {1100000, 1000000, 1000000}, > + {1075000, 975000, 975000}, > + {1050000, 950000, 950000}, > +}; > + > +static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = { > + /* 400 267 160 133 100 */ > + {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */ > + {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */ > + {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */ > + {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */ > + {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */ > + {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */ > + {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */ > + {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */ > + {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */ > +}; > + > +static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = { > + /* 200 160 133 100 */ > + {1000000, 950000, 925000, 900000}, /* ASV0 */ > + {975000, 925000, 925000, 900000}, /* ASV1 */ > + {950000, 925000, 900000, 875000}, /* ASV2 */ > + {950000, 900000, 900000, 875000}, /* ASV3 */ > + {925000, 875000, 875000, 875000}, /* ASV4 */ > + {900000, 850000, 850000, 850000}, /* ASV5 */ > + {900000, 850000, 850000, 850000}, /* ASV6 */ > + {900000, 850000, 850000, 850000}, /* ASV7 */ > + {900000, 850000, 850000, 850000}, /* ASV8 */ > +}; > + > +/*** Clock Divider Data for Exynos4210 ***/ > +static unsigned int exynos4210_clkdiv_dmc0[][8] = { > + /* > + * Clock divider value for following > + * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD > + * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS } > + */ > + > + /* DMC L0: 400MHz */ > + { 3, 1, 1, 1, 1, 1, 3, 1 }, > + /* DMC L1: 266.7MHz */ > + { 4, 1, 1, 2, 1, 1, 3, 1 }, > + /* DMC L2: 133MHz */ > + { 5, 1, 1, 5, 1, 1, 3, 1 }, > +}; > +static unsigned int exynos4210_clkdiv_top[][5] = { > + /* > + * Clock divider value for following > + * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND } > + */ > + /* ACLK200 L0: 200MHz */ > + { 3, 7, 4, 5, 1 }, > + /* ACLK200 L1: 160MHz */ > + { 4, 7, 5, 6, 1 }, > + /* ACLK200 L2: 133MHz */ > + { 5, 7, 7, 7, 1 }, > +}; > +static unsigned int exynos4210_clkdiv_lr_bus[][2] = { > + /* > + * Clock divider value for following > + * { DIVGDL/R, DIVGPL/R } > + */ > + /* ACLK_GDL/R L1: 200MHz */ > + { 3, 1 }, > + /* ACLK_GDL/R L2: 160MHz */ > + { 4, 1 }, > + /* ACLK_GDL/R L3: 133MHz */ > + { 5, 1 }, > +}; > + > +/*** Clock Divider Data for Exynos4212/4412 ***/ > +static unsigned int exynos4x12_clkdiv_dmc0[][6] = { > + /* > + * Clock divider value for following > + * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD > + * DIVDMCP} > + */ > + > + /* DMC L0: 400MHz */ > + {3, 1, 1, 1, 1, 1}, > + /* DMC L1: 266.7MHz */ > + {4, 1, 1, 2, 1, 1}, > + /* DMC L2: 160MHz */ > + {5, 1, 1, 4, 1, 1}, > + /* DMC L3: 133MHz */ > + {5, 1, 1, 5, 1, 1}, > + /* DMC L4: 100MHz */ > + {7, 1, 1, 7, 1, 1}, > +}; > +static unsigned int exynos4x12_clkdiv_dmc1[][6] = { > + /* > + * Clock divider value for following > + * { G2DACP, DIVC2C, DIVC2C_ACLK } > + */ > + > + /* DMC L0: 400MHz */ > + {3, 1, 1}, > + /* DMC L1: 266.7MHz */ > + {4, 2, 1}, > + /* DMC L2: 160MHz */ > + {5, 4, 1}, > + /* DMC L3: 133MHz */ > + {5, 5, 1}, > + /* DMC L4: 100MHz */ > + {7, 7, 1}, > +}; > +static unsigned int exynos4x12_clkdiv_top[][5] = { > + /* > + * Clock divider value for following > + * { DIVACLK266_GPS, DIVACLK100, DIVACLK160, > + DIVACLK133, DIVONENAND } > + */ > + > + /* ACLK_GDL/R L0: 200MHz */ > + {2, 7, 4, 5, 1}, > + /* ACLK_GDL/R L1: 200MHz */ > + {2, 7, 4, 5, 1}, > + /* ACLK_GDL/R L2: 160MHz */ > + {4, 7, 5, 7, 1}, > + /* ACLK_GDL/R L3: 133MHz */ > + {4, 7, 5, 7, 1}, > + /* ACLK_GDL/R L4: 100MHz */ > + {7, 7, 7, 7, 1}, > +}; > +static unsigned int exynos4x12_clkdiv_lr_bus[][2] = { > + /* > + * Clock divider value for following > + * { DIVGDL/R, DIVGPL/R } > + */ > + > + /* ACLK_GDL/R L0: 200MHz */ > + {3, 1}, > + /* ACLK_GDL/R L1: 200MHz */ > + {3, 1}, > + /* ACLK_GDL/R L2: 160MHz */ > + {4, 1}, > + /* ACLK_GDL/R L3: 133MHz */ > + {5, 1}, > + /* ACLK_GDL/R L4: 100MHz */ > + {7, 1}, > +}; > +static unsigned int exynos4x12_clkdiv_sclkip[][3] = { > + /* > + * Clock divider value for following > + * { DIVMFC, DIVJPEG, DIVFIMC0~3} > + */ > + > + /* SCLK_MFC: 200MHz */ > + {3, 3, 4}, > + /* SCLK_MFC: 200MHz */ > + {3, 3, 4}, > + /* SCLK_MFC: 160MHz */ > + {4, 4, 5}, > + /* SCLK_MFC: 133MHz */ > + {5, 5, 5}, > + /* SCLK_MFC: 100MHz */ > + {7, 7, 7}, > +}; > + > + > +static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp) > +{ > + unsigned int index; > + unsigned int tmp; > + > + for (index = LV_0; index < EX4210_LV_NUM; index++) > + if (opp_get_freq(opp) == exynos4210_busclk_table[index].clk) > + break; > + > + if (index == EX4210_LV_NUM) > + return -EINVAL; > + > + /* Change Divider - DMC0 */ > + tmp = data->dmc_divtable[index]; > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); > + } while (tmp & 0x11111111); > + > + /* Change Divider - TOP */ > + tmp = data->top_divtable[index]; > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); > + } while (tmp & 0x11111); > + > + /* Change Divider - LEFTBUS */ > + tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); > + > + tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); > + > + tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << > + EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | > + (exynos4210_clkdiv_lr_bus[index][1] << > + EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); > + } while (tmp & 0x11); > + > + /* Change Divider - RIGHTBUS */ > + tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); > + > + tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); > + > + tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << > + EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | > + (exynos4210_clkdiv_lr_bus[index][1] << > + EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); > + } while (tmp & 0x11); > + > + return 0; > +} > + > +static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp) > +{ > + unsigned int index; > + unsigned int tmp; > + > + for (index = LV_0; index < EX4x12_LV_NUM; index++) > + if (opp_get_freq(opp) == exynos4x12_mifclk_table[index].clk) > + break; > + > + if (index == EX4x12_LV_NUM) > + return -EINVAL; > + > + /* Change Divider - DMC0 */ > + tmp = data->dmc_divtable[index]; > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); > + } while (tmp & 0x11111111); > + > + /* Change Divider - DMC1 */ > + tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1); > + > + tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK | > + EXYNOS4_CLKDIV_DMC1_C2C_MASK | > + EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK); > + > + tmp |= ((exynos4x12_clkdiv_dmc1[index][0] << > + EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) | > + (exynos4x12_clkdiv_dmc1[index][1] << > + EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) | > + (exynos4x12_clkdiv_dmc1[index][2] << > + EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)); > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1); > + } while (tmp & 0x111111); > + > + /* Change Divider - TOP */ > + tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); > + > + tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK | > + EXYNOS4_CLKDIV_TOP_ACLK100_MASK | > + EXYNOS4_CLKDIV_TOP_ACLK160_MASK | > + EXYNOS4_CLKDIV_TOP_ACLK133_MASK | > + EXYNOS4_CLKDIV_TOP_ONENAND_MASK); > + > + tmp |= ((exynos4x12_clkdiv_top[index][0] << > + EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) | > + (exynos4x12_clkdiv_top[index][1] << > + EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | > + (exynos4x12_clkdiv_top[index][2] << > + EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | > + (exynos4x12_clkdiv_top[index][3] << > + EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | > + (exynos4x12_clkdiv_top[index][4] << > + EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)); > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); > + } while (tmp & 0x11111); > + > + /* Change Divider - LEFTBUS */ > + tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); > + > + tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); > + > + tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << > + EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | > + (exynos4x12_clkdiv_lr_bus[index][1] << > + EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); > + } while (tmp & 0x11); > + > + /* Change Divider - RIGHTBUS */ > + tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); > + > + tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); > + > + tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << > + EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | > + (exynos4x12_clkdiv_lr_bus[index][1] << > + EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); > + } while (tmp & 0x11); > + > + /* Change Divider - MFC */ > + tmp = __raw_readl(EXYNOS4_CLKDIV_MFC); > + > + tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK); > + > + tmp |= ((exynos4x12_clkdiv_sclkip[index][0] << > + EXYNOS4_CLKDIV_MFC_SHIFT)); > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_MFC); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC); > + } while (tmp & 0x1); > + > + /* Change Divider - JPEG */ > + tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1); > + > + tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK); > + > + tmp |= ((exynos4x12_clkdiv_sclkip[index][1] << > + EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)); > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); > + } while (tmp & 0x1); > + > + /* Change Divider - FIMC0~3 */ > + tmp = __raw_readl(EXYNOS4_CLKDIV_CAM); > + > + tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK | > + EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK); > + > + tmp |= ((exynos4x12_clkdiv_sclkip[index][2] << > + EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) | > + (exynos4x12_clkdiv_sclkip[index][2] << > + EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) | > + (exynos4x12_clkdiv_sclkip[index][2] << > + EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) | > + (exynos4x12_clkdiv_sclkip[index][2] << > + EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)); > + > + __raw_writel(tmp, EXYNOS4_CLKDIV_CAM); > + > + do { > + tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); > + } while (tmp & 0x1111); > + > + return 0; > +} > + > + > +static void busfreq_mon_reset(struct busfreq_data *data) > +{ > + unsigned int i; > + > + for (i = 0; i < 2; i++) { > + void __iomem *ppmu_base = data->dmc[i].hw_base; > + > + /* Reset PPMU */ > + __raw_writel(0x8000000f, ppmu_base + 0xf010); > + __raw_writel(0x8000000f, ppmu_base + 0xf050); > + __raw_writel(0x6, ppmu_base + 0xf000); > + __raw_writel(0x0, ppmu_base + 0xf100); > + > + /* Set PPMU Event */ > + data->dmc[i].event = 0x6; > + __raw_writel(((data->dmc[i].event << 12) | 0x1), > + ppmu_base + 0xfc); > + > + /* Start PPMU */ > + __raw_writel(0x1, ppmu_base + 0xf000); > + } > +} > + > +static void exynos4_read_ppmu(struct busfreq_data *data) > +{ > + int i, j; > + > + for (i = 0; i < 2; i++) { > + void __iomem *ppmu_base = data->dmc[i].hw_base; > + u32 overflow; > + > + /* Stop PPMU */ > + __raw_writel(0x0, ppmu_base + 0xf000); > + > + /* Update local data from PPMU */ > + overflow = __raw_readl(ppmu_base + 0xf050); > + > + data->dmc[i].ccnt = __raw_readl(ppmu_base + 0xf100); > + data->dmc[i].ccnt_overflow = overflow & (1 << 31); > + > + for (j = 0; j < PPMU_PMNCNT_MAX; j++) { > + data->dmc[i].count[j] = __raw_readl( > + ppmu_base + (0xf110 + (0x10 * j))); > + data->dmc[i].count_overflow[j] = overflow & (1 << j); > + } > + } > + > + busfreq_mon_reset(data); > +} > + > +static int exynos4x12_get_intspec(unsigned long mifclk) > +{ > + int i = 0; > + > + while (exynos4x12_intclk_table[i].clk) { > + if (exynos4x12_intclk_table[i].clk <= mifclk) > + return i; > + i++; > + } > + > + return -EINVAL; > +} > + > +static int exynos4_bus_setvolt(struct busfreq_data *data, struct opp *opp, > + struct opp *oldopp) > +{ > + int err = 0, tmp; > + unsigned long volt = opp_get_voltage(opp); > + > + switch (data->type) { > + case TYPE_BUSF_EXYNOS4210: > + /* OPP represents DMC clock + INT voltage */ > + err = regulator_set_voltage(data->vdd_int, volt, > + MAX_SAFEVOLT); > + break; > + case TYPE_BUSF_EXYNOS4x12: > + /* OPP represents MIF clock + MIF voltage */ > + err = regulator_set_voltage(data->vdd_mif, volt, > + MAX_SAFEVOLT); > + if (err) > + break; > + > + tmp = exynos4x12_get_intspec(opp_get_freq(opp)); > + if (tmp < 0) { > + err = tmp; > + regulator_set_voltage(data->vdd_mif, > + opp_get_voltage(oldopp), > + MAX_SAFEVOLT); > + break; > + } > + err = regulator_set_voltage(data->vdd_int, > + exynos4x12_intclk_table[tmp].volt, > + MAX_SAFEVOLT); > + /* Try to recover */ > + if (err) > + regulator_set_voltage(data->vdd_mif, > + opp_get_voltage(oldopp), > + MAX_SAFEVOLT); > + break; > + default: > + err = -EINVAL; > + } > + > + return err; > +} > + > +static int exynos4_bus_target(struct device *dev, unsigned long *_freq, > + u32 flags) > +{ > + int err = 0; > + struct platform_device *pdev = container_of(dev, struct platform_device, > + dev); > + struct busfreq_data *data = platform_get_drvdata(pdev); > + struct opp *opp = devfreq_recommended_opp(dev, _freq, flags); > + unsigned long freq = opp_get_freq(opp); > + unsigned long old_freq = opp_get_freq(data->curr_opp); > + > + if (IS_ERR(opp)) > + return PTR_ERR(opp); > + > + if (old_freq == freq) > + return 0; > + > + dev_dbg(dev, "targetting %lukHz %luuV\n", freq, opp_get_voltage(opp)); > + > + mutex_lock(&data->lock); > + > + if (data->disabled) > + goto out; > + > + if (old_freq < freq) > + err = exynos4_bus_setvolt(data, opp, data->curr_opp); > + if (err) > + goto out; > + > + if (old_freq != freq) { > + switch (data->type) { > + case TYPE_BUSF_EXYNOS4210: > + err = exynos4210_set_busclk(data, opp); > + break; > + case TYPE_BUSF_EXYNOS4x12: > + err = exynos4x12_set_busclk(data, opp); > + break; > + default: > + err = -EINVAL; > + } > + } > + if (err) > + goto out; > + > + if (old_freq > freq) > + err = exynos4_bus_setvolt(data, opp, data->curr_opp); > + if (err) > + goto out; > + > + data->curr_opp = opp; > +out: > + mutex_unlock(&data->lock); > + return err; > +} > + > +static int exynos4_get_busier_dmc(struct busfreq_data *data) > +{ > + u64 p0 = data->dmc[0].count[0]; > + u64 p1 = data->dmc[1].count[0]; > + > + p0 *= data->dmc[1].ccnt; > + p1 *= data->dmc[0].ccnt; > + > + if (data->dmc[1].ccnt == 0) > + return 0; > + > + if (p0 > p1) > + return 0; > + return 1; > +} > + > +static int exynos4_bus_get_dev_status(struct device *dev, > + struct devfreq_dev_status *stat) > +{ > + struct busfreq_data *data = dev_get_drvdata(dev); > + int busier_dmc; > + int cycles_x2 = 2; /* 2 x cycles */ > + void __iomem *addr; > + u32 timing; > + u32 memctrl; > + > + exynos4_read_ppmu(data); > + busier_dmc = exynos4_get_busier_dmc(data); > + stat->current_frequency = opp_get_freq(data->curr_opp); > + > + if (busier_dmc) > + addr = S5P_VA_DMC1; > + else > + addr = S5P_VA_DMC0; > + > + memctrl = __raw_readl(addr + 0x04); /* one of DDR2/3/LPDDR2 */ > + timing = __raw_readl(addr + 0x38); /* CL or WL/RL values */ > + > + switch ((memctrl >> 8) & 0xf) { > + case 0x4: /* DDR2 */ > + cycles_x2 = ((timing >> 16) & 0xf) * 2; > + break; > + case 0x5: /* LPDDR2 */ > + case 0x6: /* DDR3 */ > + cycles_x2 = ((timing >> 8) & 0xf) + ((timing >> 0) & 0xf); > + break; > + default: > + pr_err("%s: Unknown Memory Type(%d).\n", __func__, > + (memctrl >> 8) & 0xf); > + return -EINVAL; > + } > + > + /* Number of cycles spent on memory access */ > + stat->busy_time = data->dmc[busier_dmc].count[0] / 2 * (cycles_x2 + 2); > + stat->busy_time *= 100 / BUS_SATURATION_RATIO; > + stat->total_time = data->dmc[busier_dmc].ccnt; > + > + /* If the counters have overflown, retry */ > + if (data->dmc[busier_dmc].ccnt_overflow || > + data->dmc[busier_dmc].count_overflow[0]) > + return -EAGAIN; > + > + return 0; > +} > + > +static void exynos4_bus_exit(struct device *dev) > +{ > + struct busfreq_data *data = dev_get_drvdata(dev); > + > + devfreq_unregister_opp_notifier(dev, data->devfreq); > +} > + > +static struct devfreq_dev_profile exynos4_devfreq_profile = { > + .initial_freq = 400000, > + .polling_ms = 50, > + .target = exynos4_bus_target, > + .get_dev_status = exynos4_bus_get_dev_status, > + .exit = exynos4_bus_exit, > +}; > + > +static int exynos4210_init_tables(struct busfreq_data *data) > +{ > + u32 tmp; > + int mgrp; > + int i, err = 0; > + > + tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); > + for (i = LV_0; i < EX4210_LV_NUM; i++) { > + tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | > + EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK | > + EXYNOS4_CLKDIV_DMC0_DPHY_MASK | > + EXYNOS4_CLKDIV_DMC0_DMC_MASK | > + EXYNOS4_CLKDIV_DMC0_DMCD_MASK | > + EXYNOS4_CLKDIV_DMC0_DMCP_MASK | > + EXYNOS4_CLKDIV_DMC0_COPY2_MASK | > + EXYNOS4_CLKDIV_DMC0_CORETI_MASK); > + > + tmp |= ((exynos4210_clkdiv_dmc0[i][0] << > + EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | > + (exynos4210_clkdiv_dmc0[i][1] << > + EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | > + (exynos4210_clkdiv_dmc0[i][2] << > + EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | > + (exynos4210_clkdiv_dmc0[i][3] << > + EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | > + (exynos4210_clkdiv_dmc0[i][4] << > + EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | > + (exynos4210_clkdiv_dmc0[i][5] << > + EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) | > + (exynos4210_clkdiv_dmc0[i][6] << > + EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) | > + (exynos4210_clkdiv_dmc0[i][7] << > + EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)); > + > + data->dmc_divtable[i] = tmp; > + } > + > + tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); > + for (i = LV_0; i < EX4210_LV_NUM; i++) { > + tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK | > + EXYNOS4_CLKDIV_TOP_ACLK100_MASK | > + EXYNOS4_CLKDIV_TOP_ACLK160_MASK | > + EXYNOS4_CLKDIV_TOP_ACLK133_MASK | > + EXYNOS4_CLKDIV_TOP_ONENAND_MASK); > + > + tmp |= ((exynos4210_clkdiv_top[i][0] << > + EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) | > + (exynos4210_clkdiv_top[i][1] << > + EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | > + (exynos4210_clkdiv_top[i][2] << > + EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | > + (exynos4210_clkdiv_top[i][3] << > + EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | > + (exynos4210_clkdiv_top[i][4] << > + EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)); > + > + data->top_divtable[i] = tmp; > + } > + > +#ifdef CONFIG_EXYNOS_ASV > + tmp = exynos4_result_of_asv; > +#else > + tmp = 0; /* Max voltages for the reliability of the unknown */ > +#endif > + > + pr_debug("ASV Group of Exynos4 is %d\n", tmp); > + /* Use merged grouping for voltage */ > + switch (tmp) { > + case 0: > + mgrp = 0; > + break; > + case 1: > + case 2: > + mgrp = 1; > + break; > + case 3: > + case 4: > + mgrp = 2; > + break; > + case 5: > + case 6: > + mgrp = 3; > + break; > + case 7: > + mgrp = 4; > + break; > + default: > + pr_warn("Unknown ASV Group. Use max voltage.\n"); > + mgrp = 0; > + } > + > + for (i = LV_0; i < EX4210_LV_NUM; i++) > + exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i]; > + > + for (i = LV_0; i < EX4210_LV_NUM; i++) { > + err = opp_add(data->dev, exynos4210_busclk_table[i].clk, > + exynos4210_busclk_table[i].volt); > + if (err) { > + dev_err(data->dev, "Cannot add opp entries.\n"); > + return err; > + } > + } > + > + > + return 0; > +} > + > +static int exynos4x12_init_tables(struct busfreq_data *data) > +{ > + unsigned int i; > + unsigned int tmp; > + int ret; > + > + /* Enable pause function for DREX2 DVFS */ > + tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL); > + tmp |= EXYNOS4_DMC_PAUSE_ENABLE; > + __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL); > + > + tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); > + > + for (i = 0; i < EX4x12_LV_NUM; i++) { > + tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | > + EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK | > + EXYNOS4_CLKDIV_DMC0_DPHY_MASK | > + EXYNOS4_CLKDIV_DMC0_DMC_MASK | > + EXYNOS4_CLKDIV_DMC0_DMCD_MASK | > + EXYNOS4_CLKDIV_DMC0_DMCP_MASK); > + > + tmp |= ((exynos4x12_clkdiv_dmc0[i][0] << > + EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | > + (exynos4x12_clkdiv_dmc0[i][1] << > + EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | > + (exynos4x12_clkdiv_dmc0[i][2] << > + EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | > + (exynos4x12_clkdiv_dmc0[i][3] << > + EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | > + (exynos4x12_clkdiv_dmc0[i][4] << > + EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | > + (exynos4x12_clkdiv_dmc0[i][5] << > + EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)); > + > + data->dmc_divtable[i] = tmp; > + } > + > +#ifdef CONFIG_EXYNOS_ASV > + tmp = exynos4_result_of_asv; > +#else > + tmp = 0; /* Max voltages for the reliability of the unknown */ > +#endif > + > + if (tmp > 8) > + tmp = 0; > + pr_debug("ASV Group of Exynos4x12 is %d\n", tmp); > + > + for (i = 0; i < EX4x12_LV_NUM; i++) { > + exynos4x12_mifclk_table[i].volt = > + exynos4x12_mif_step_50[tmp][i]; > + exynos4x12_intclk_table[i].volt = > + exynos4x12_int_volt[tmp][i]; > + } > + > + for (i = 0; i < EX4x12_LV_NUM; i++) { > + ret = opp_add(data->dev, exynos4x12_mifclk_table[i].clk, > + exynos4x12_mifclk_table[i].volt); > + if (ret) { > + dev_err(data->dev, "Fail to add opp entries.\n"); > + return ret; > + } > + } > + > + return 0; > +} > + > +static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this, > + unsigned long event, void *ptr) > +{ > + struct busfreq_data *data = container_of(this, struct busfreq_data, > + pm_notifier); > + struct opp *opp; > + unsigned long maxfreq = ULONG_MAX; > + int err = 0; > + > + switch (event) { > + case PM_SUSPEND_PREPARE: > + /* Set Fastest and Deactivate DVFS */ > + mutex_lock(&data->lock); > + > + data->disabled = true; > + > + opp = opp_find_freq_floor(data->dev, &maxfreq); > + > + err = exynos4_bus_setvolt(data, opp, data->curr_opp); > + if (err) > + goto unlock; > + > + switch (data->type) { > + case TYPE_BUSF_EXYNOS4210: > + err = exynos4210_set_busclk(data, opp); > + break; > + case TYPE_BUSF_EXYNOS4x12: > + err = exynos4x12_set_busclk(data, opp); > + break; > + default: > + err = -EINVAL; > + } > + if (err) > + goto unlock; > + > + data->curr_opp = opp; > +unlock: > + mutex_unlock(&data->lock); > + if (err) > + return err; > + return NOTIFY_OK; > + case PM_POST_RESTORE: > + case PM_POST_SUSPEND: > + /* Reactivate */ > + mutex_lock(&data->lock); > + data->disabled = false; > + mutex_unlock(&data->lock); > + return NOTIFY_OK; > + } > + > + return NOTIFY_DONE; > +} > + > +static __devinit int exynos4_busfreq_probe(struct platform_device *pdev) > +{ > + struct busfreq_data *data; > + struct opp *opp; > + struct device *dev = &pdev->dev; > + int err = 0; > + > + data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data), GFP_KERNEL); > + if (data == NULL) { > + dev_err(dev, "Cannot allocate memory.\n"); > + return -ENOMEM; > + } > + > + data->type = pdev->id_entry->driver_data; > + data->dmc[0].hw_base = S5P_VA_DMC0; > + data->dmc[1].hw_base = S5P_VA_DMC1; > + data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event; > + data->dev = dev; > + mutex_init(&data->lock); > + > + switch (data->type) { > + case TYPE_BUSF_EXYNOS4210: > + err = exynos4210_init_tables(data); > + break; > + case TYPE_BUSF_EXYNOS4x12: > + err = exynos4x12_init_tables(data); > + break; > + default: > + dev_err(dev, "Cannot determine the device id %d\n", data->type); > + err = -EINVAL; > + } > + if (err) > + return err; > + > + data->vdd_int = devm_regulator_get(dev, "vdd_int"); > + if (IS_ERR(data->vdd_int)) { > + dev_err(dev, "Cannot get the regulator \"vdd_int\"\n"); > + return PTR_ERR(data->vdd_int); > + } > + if (data->type == TYPE_BUSF_EXYNOS4x12) { > + data->vdd_mif = devm_regulator_get(dev, "vdd_mif"); > + if (IS_ERR(data->vdd_mif)) { > + dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n"); > + return PTR_ERR(data->vdd_mif); > + } > + } > + > + opp = opp_find_freq_floor(dev, &exynos4_devfreq_profile.initial_freq); > + if (IS_ERR(opp)) { > + dev_err(dev, "Invalid initial frequency %lu kHz.\n", > + exynos4_devfreq_profile.initial_freq); > + return PTR_ERR(opp); > + } > + data->curr_opp = opp; > + > + platform_set_drvdata(pdev, data); > + > + busfreq_mon_reset(data); > + > + data->devfreq = devfreq_add_device(dev, &exynos4_devfreq_profile, > + "simple_ondemand", NULL); > + if (IS_ERR(data->devfreq)) > + return PTR_ERR(data->devfreq); > + > + devfreq_register_opp_notifier(dev, data->devfreq); > + > + err = register_pm_notifier(&data->pm_notifier); > + if (err) { > + dev_err(dev, "Failed to setup pm notifier\n"); > + devfreq_remove_device(data->devfreq); > + return err; > + } > + > + return 0; > +} > + > +static __devexit int exynos4_busfreq_remove(struct platform_device *pdev) > +{ > + struct busfreq_data *data = platform_get_drvdata(pdev); > + > + unregister_pm_notifier(&data->pm_notifier); > + devfreq_remove_device(data->devfreq); > + > + return 0; > +} > + > +static int exynos4_busfreq_resume(struct device *dev) > +{ > + struct busfreq_data *data = dev_get_drvdata(dev); > + > + busfreq_mon_reset(data); > + return 0; > +} > + > +static const struct dev_pm_ops exynos4_busfreq_pm = { > + .resume = exynos4_busfreq_resume, > +}; > + > +static const struct platform_device_id exynos4_busfreq_id[] = { > + { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 }, > + { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 }, > + { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 }, > + { }, > +}; > + > +static struct platform_driver exynos4_busfreq_driver = { > + .probe = exynos4_busfreq_probe, > + .remove = __devexit_p(exynos4_busfreq_remove), > + .id_table = exynos4_busfreq_id, > + .driver = { > + .name = "exynos4-busfreq", > + .owner = THIS_MODULE, > + .pm = &exynos4_busfreq_pm, > + }, > +}; > + > +static int __init exynos4_busfreq_init(void) > +{ > + return platform_driver_register(&exynos4_busfreq_driver); > +} > +late_initcall(exynos4_busfreq_init); > + > +static void __exit exynos4_busfreq_exit(void) > +{ > + platform_driver_unregister(&exynos4_busfreq_driver); > +} > +module_exit(exynos4_busfreq_exit); > + > +MODULE_LICENSE("GPL"); > +MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework"); > +MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>"); > diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos4_bus.c > deleted file mode 100644 > index 7418372..0000000 > --- a/drivers/devfreq/exynos4_bus.c > +++ /dev/null > @@ -1,1113 +0,0 @@ > -/* drivers/devfreq/exynos4210_memorybus.c > - * > - * Copyright (c) 2011 Samsung Electronics Co., Ltd. > - * http://www.samsung.com/ > - * MyungJoo Ham <myungjoo.ham@samsung.com> > - * > - * EXYNOS4 - Memory/Bus clock frequency scaling support in DEVFREQ framework > - * This version supports EXYNOS4210 only. This changes bus frequencies > - * and vddint voltages. Exynos4412/4212 should be able to be supported > - * with minor modifications. > - * > - * This program is free software; you can redistribute it and/or modify > - * it under the terms of the GNU General Public License version 2 as > - * published by the Free Software Foundation. > - * > - */ > - > -#include <linux/io.h> > -#include <linux/slab.h> > -#include <linux/mutex.h> > -#include <linux/suspend.h> > -#include <linux/opp.h> > -#include <linux/devfreq.h> > -#include <linux/platform_device.h> > -#include <linux/regulator/consumer.h> > -#include <linux/module.h> > - > -/* Exynos4 ASV has been in the mailing list, but not upstreamed, yet. */ > -#ifdef CONFIG_EXYNOS_ASV > -extern unsigned int exynos_result_of_asv; > -#endif > - > -#include <mach/regs-clock.h> > - > -#include <plat/map-s5p.h> > - > -#define MAX_SAFEVOLT 1200000 /* 1.2V */ > - > -enum exynos4_busf_type { > - TYPE_BUSF_EXYNOS4210, > - TYPE_BUSF_EXYNOS4x12, > -}; > - > -/* Assume that the bus is saturated if the utilization is 40% */ > -#define BUS_SATURATION_RATIO 40 > - > -enum ppmu_counter { > - PPMU_PMNCNT0 = 0, > - PPMU_PMCCNT1, > - PPMU_PMNCNT2, > - PPMU_PMNCNT3, > - PPMU_PMNCNT_MAX, > -}; > -struct exynos4_ppmu { > - void __iomem *hw_base; > - unsigned int ccnt; > - unsigned int event; > - unsigned int count[PPMU_PMNCNT_MAX]; > - bool ccnt_overflow; > - bool count_overflow[PPMU_PMNCNT_MAX]; > -}; > - > -enum busclk_level_idx { > - LV_0 = 0, > - LV_1, > - LV_2, > - LV_3, > - LV_4, > - _LV_END > -}; > -#define EX4210_LV_MAX LV_2 > -#define EX4x12_LV_MAX LV_4 > -#define EX4210_LV_NUM (LV_2 + 1) > -#define EX4x12_LV_NUM (LV_4 + 1) > - > -struct busfreq_data { > - enum exynos4_busf_type type; > - struct device *dev; > - struct devfreq *devfreq; > - bool disabled; > - struct regulator *vdd_int; > - struct regulator *vdd_mif; /* Exynos4412/4212 only */ > - struct opp *curr_opp; > - struct exynos4_ppmu dmc[2]; > - > - struct notifier_block pm_notifier; > - struct mutex lock; > - > - /* Dividers calculated at boot/probe-time */ > - unsigned int dmc_divtable[_LV_END]; /* DMC0 */ > - unsigned int top_divtable[_LV_END]; > -}; > - > -struct bus_opp_table { > - unsigned int idx; > - unsigned long clk; > - unsigned long volt; > -}; > - > -/* 4210 controls clock of mif and voltage of int */ > -static struct bus_opp_table exynos4210_busclk_table[] = { > - {LV_0, 400000, 1150000}, > - {LV_1, 267000, 1050000}, > - {LV_2, 133000, 1025000}, > - {0, 0, 0}, > -}; > - > -/* > - * MIF is the main control knob clock for exynox4x12 MIF/INT > - * clock and voltage of both mif/int are controlled. > - */ > -static struct bus_opp_table exynos4x12_mifclk_table[] = { > - {LV_0, 400000, 1100000}, > - {LV_1, 267000, 1000000}, > - {LV_2, 160000, 950000}, > - {LV_3, 133000, 950000}, > - {LV_4, 100000, 950000}, > - {0, 0, 0}, > -}; > - > -/* > - * INT is not the control knob of 4x12. LV_x is not meant to represent > - * the current performance. (MIF does) > - */ > -static struct bus_opp_table exynos4x12_intclk_table[] = { > - {LV_0, 200000, 1000000}, > - {LV_1, 160000, 950000}, > - {LV_2, 133000, 925000}, > - {LV_3, 100000, 900000}, > - {0, 0, 0}, > -}; > - > -/* TODO: asv volt definitions are "__initdata"? */ > -/* Some chips have different operating voltages */ > -static unsigned int exynos4210_asv_volt[][EX4210_LV_NUM] = { > - {1150000, 1050000, 1050000}, > - {1125000, 1025000, 1025000}, > - {1100000, 1000000, 1000000}, > - {1075000, 975000, 975000}, > - {1050000, 950000, 950000}, > -}; > - > -static unsigned int exynos4x12_mif_step_50[][EX4x12_LV_NUM] = { > - /* 400 267 160 133 100 */ > - {1050000, 950000, 900000, 900000, 900000}, /* ASV0 */ > - {1050000, 950000, 900000, 900000, 900000}, /* ASV1 */ > - {1050000, 950000, 900000, 900000, 900000}, /* ASV2 */ > - {1050000, 900000, 900000, 900000, 900000}, /* ASV3 */ > - {1050000, 900000, 900000, 900000, 850000}, /* ASV4 */ > - {1050000, 900000, 900000, 850000, 850000}, /* ASV5 */ > - {1050000, 900000, 850000, 850000, 850000}, /* ASV6 */ > - {1050000, 900000, 850000, 850000, 850000}, /* ASV7 */ > - {1050000, 900000, 850000, 850000, 850000}, /* ASV8 */ > -}; > - > -static unsigned int exynos4x12_int_volt[][EX4x12_LV_NUM] = { > - /* 200 160 133 100 */ > - {1000000, 950000, 925000, 900000}, /* ASV0 */ > - {975000, 925000, 925000, 900000}, /* ASV1 */ > - {950000, 925000, 900000, 875000}, /* ASV2 */ > - {950000, 900000, 900000, 875000}, /* ASV3 */ > - {925000, 875000, 875000, 875000}, /* ASV4 */ > - {900000, 850000, 850000, 850000}, /* ASV5 */ > - {900000, 850000, 850000, 850000}, /* ASV6 */ > - {900000, 850000, 850000, 850000}, /* ASV7 */ > - {900000, 850000, 850000, 850000}, /* ASV8 */ > -}; > - > -/*** Clock Divider Data for Exynos4210 ***/ > -static unsigned int exynos4210_clkdiv_dmc0[][8] = { > - /* > - * Clock divider value for following > - * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD > - * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS } > - */ > - > - /* DMC L0: 400MHz */ > - { 3, 1, 1, 1, 1, 1, 3, 1 }, > - /* DMC L1: 266.7MHz */ > - { 4, 1, 1, 2, 1, 1, 3, 1 }, > - /* DMC L2: 133MHz */ > - { 5, 1, 1, 5, 1, 1, 3, 1 }, > -}; > -static unsigned int exynos4210_clkdiv_top[][5] = { > - /* > - * Clock divider value for following > - * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND } > - */ > - /* ACLK200 L0: 200MHz */ > - { 3, 7, 4, 5, 1 }, > - /* ACLK200 L1: 160MHz */ > - { 4, 7, 5, 6, 1 }, > - /* ACLK200 L2: 133MHz */ > - { 5, 7, 7, 7, 1 }, > -}; > -static unsigned int exynos4210_clkdiv_lr_bus[][2] = { > - /* > - * Clock divider value for following > - * { DIVGDL/R, DIVGPL/R } > - */ > - /* ACLK_GDL/R L1: 200MHz */ > - { 3, 1 }, > - /* ACLK_GDL/R L2: 160MHz */ > - { 4, 1 }, > - /* ACLK_GDL/R L3: 133MHz */ > - { 5, 1 }, > -}; > - > -/*** Clock Divider Data for Exynos4212/4412 ***/ > -static unsigned int exynos4x12_clkdiv_dmc0[][6] = { > - /* > - * Clock divider value for following > - * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD > - * DIVDMCP} > - */ > - > - /* DMC L0: 400MHz */ > - {3, 1, 1, 1, 1, 1}, > - /* DMC L1: 266.7MHz */ > - {4, 1, 1, 2, 1, 1}, > - /* DMC L2: 160MHz */ > - {5, 1, 1, 4, 1, 1}, > - /* DMC L3: 133MHz */ > - {5, 1, 1, 5, 1, 1}, > - /* DMC L4: 100MHz */ > - {7, 1, 1, 7, 1, 1}, > -}; > -static unsigned int exynos4x12_clkdiv_dmc1[][6] = { > - /* > - * Clock divider value for following > - * { G2DACP, DIVC2C, DIVC2C_ACLK } > - */ > - > - /* DMC L0: 400MHz */ > - {3, 1, 1}, > - /* DMC L1: 266.7MHz */ > - {4, 2, 1}, > - /* DMC L2: 160MHz */ > - {5, 4, 1}, > - /* DMC L3: 133MHz */ > - {5, 5, 1}, > - /* DMC L4: 100MHz */ > - {7, 7, 1}, > -}; > -static unsigned int exynos4x12_clkdiv_top[][5] = { > - /* > - * Clock divider value for following > - * { DIVACLK266_GPS, DIVACLK100, DIVACLK160, > - DIVACLK133, DIVONENAND } > - */ > - > - /* ACLK_GDL/R L0: 200MHz */ > - {2, 7, 4, 5, 1}, > - /* ACLK_GDL/R L1: 200MHz */ > - {2, 7, 4, 5, 1}, > - /* ACLK_GDL/R L2: 160MHz */ > - {4, 7, 5, 7, 1}, > - /* ACLK_GDL/R L3: 133MHz */ > - {4, 7, 5, 7, 1}, > - /* ACLK_GDL/R L4: 100MHz */ > - {7, 7, 7, 7, 1}, > -}; > -static unsigned int exynos4x12_clkdiv_lr_bus[][2] = { > - /* > - * Clock divider value for following > - * { DIVGDL/R, DIVGPL/R } > - */ > - > - /* ACLK_GDL/R L0: 200MHz */ > - {3, 1}, > - /* ACLK_GDL/R L1: 200MHz */ > - {3, 1}, > - /* ACLK_GDL/R L2: 160MHz */ > - {4, 1}, > - /* ACLK_GDL/R L3: 133MHz */ > - {5, 1}, > - /* ACLK_GDL/R L4: 100MHz */ > - {7, 1}, > -}; > -static unsigned int exynos4x12_clkdiv_sclkip[][3] = { > - /* > - * Clock divider value for following > - * { DIVMFC, DIVJPEG, DIVFIMC0~3} > - */ > - > - /* SCLK_MFC: 200MHz */ > - {3, 3, 4}, > - /* SCLK_MFC: 200MHz */ > - {3, 3, 4}, > - /* SCLK_MFC: 160MHz */ > - {4, 4, 5}, > - /* SCLK_MFC: 133MHz */ > - {5, 5, 5}, > - /* SCLK_MFC: 100MHz */ > - {7, 7, 7}, > -}; > - > - > -static int exynos4210_set_busclk(struct busfreq_data *data, struct opp *opp) > -{ > - unsigned int index; > - unsigned int tmp; > - > - for (index = LV_0; index < EX4210_LV_NUM; index++) > - if (opp_get_freq(opp) == exynos4210_busclk_table[index].clk) > - break; > - > - if (index == EX4210_LV_NUM) > - return -EINVAL; > - > - /* Change Divider - DMC0 */ > - tmp = data->dmc_divtable[index]; > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); > - } while (tmp & 0x11111111); > - > - /* Change Divider - TOP */ > - tmp = data->top_divtable[index]; > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); > - } while (tmp & 0x11111); > - > - /* Change Divider - LEFTBUS */ > - tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); > - > - tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); > - > - tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << > - EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | > - (exynos4210_clkdiv_lr_bus[index][1] << > - EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); > - } while (tmp & 0x11); > - > - /* Change Divider - RIGHTBUS */ > - tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); > - > - tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); > - > - tmp |= ((exynos4210_clkdiv_lr_bus[index][0] << > - EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | > - (exynos4210_clkdiv_lr_bus[index][1] << > - EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); > - } while (tmp & 0x11); > - > - return 0; > -} > - > -static int exynos4x12_set_busclk(struct busfreq_data *data, struct opp *opp) > -{ > - unsigned int index; > - unsigned int tmp; > - > - for (index = LV_0; index < EX4x12_LV_NUM; index++) > - if (opp_get_freq(opp) == exynos4x12_mifclk_table[index].clk) > - break; > - > - if (index == EX4x12_LV_NUM) > - return -EINVAL; > - > - /* Change Divider - DMC0 */ > - tmp = data->dmc_divtable[index]; > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_DMC0); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC0); > - } while (tmp & 0x11111111); > - > - /* Change Divider - DMC1 */ > - tmp = __raw_readl(EXYNOS4_CLKDIV_DMC1); > - > - tmp &= ~(EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK | > - EXYNOS4_CLKDIV_DMC1_C2C_MASK | > - EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK); > - > - tmp |= ((exynos4x12_clkdiv_dmc1[index][0] << > - EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) | > - (exynos4x12_clkdiv_dmc1[index][1] << > - EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) | > - (exynos4x12_clkdiv_dmc1[index][2] << > - EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT)); > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_DMC1); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_DMC1); > - } while (tmp & 0x111111); > - > - /* Change Divider - TOP */ > - tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); > - > - tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK | > - EXYNOS4_CLKDIV_TOP_ACLK100_MASK | > - EXYNOS4_CLKDIV_TOP_ACLK160_MASK | > - EXYNOS4_CLKDIV_TOP_ACLK133_MASK | > - EXYNOS4_CLKDIV_TOP_ONENAND_MASK); > - > - tmp |= ((exynos4x12_clkdiv_top[index][0] << > - EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) | > - (exynos4x12_clkdiv_top[index][1] << > - EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | > - (exynos4x12_clkdiv_top[index][2] << > - EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | > - (exynos4x12_clkdiv_top[index][3] << > - EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | > - (exynos4x12_clkdiv_top[index][4] << > - EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)); > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_TOP); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_TOP); > - } while (tmp & 0x11111); > - > - /* Change Divider - LEFTBUS */ > - tmp = __raw_readl(EXYNOS4_CLKDIV_LEFTBUS); > - > - tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); > - > - tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << > - EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | > - (exynos4x12_clkdiv_lr_bus[index][1] << > - EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_LEFTBUS); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_LEFTBUS); > - } while (tmp & 0x11); > - > - /* Change Divider - RIGHTBUS */ > - tmp = __raw_readl(EXYNOS4_CLKDIV_RIGHTBUS); > - > - tmp &= ~(EXYNOS4_CLKDIV_BUS_GDLR_MASK | EXYNOS4_CLKDIV_BUS_GPLR_MASK); > - > - tmp |= ((exynos4x12_clkdiv_lr_bus[index][0] << > - EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | > - (exynos4x12_clkdiv_lr_bus[index][1] << > - EXYNOS4_CLKDIV_BUS_GPLR_SHIFT)); > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_RIGHTBUS); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_RIGHTBUS); > - } while (tmp & 0x11); > - > - /* Change Divider - MFC */ > - tmp = __raw_readl(EXYNOS4_CLKDIV_MFC); > - > - tmp &= ~(EXYNOS4_CLKDIV_MFC_MASK); > - > - tmp |= ((exynos4x12_clkdiv_sclkip[index][0] << > - EXYNOS4_CLKDIV_MFC_SHIFT)); > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_MFC); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_MFC); > - } while (tmp & 0x1); > - > - /* Change Divider - JPEG */ > - tmp = __raw_readl(EXYNOS4_CLKDIV_CAM1); > - > - tmp &= ~(EXYNOS4_CLKDIV_CAM1_JPEG_MASK); > - > - tmp |= ((exynos4x12_clkdiv_sclkip[index][1] << > - EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)); > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_CAM1); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); > - } while (tmp & 0x1); > - > - /* Change Divider - FIMC0~3 */ > - tmp = __raw_readl(EXYNOS4_CLKDIV_CAM); > - > - tmp &= ~(EXYNOS4_CLKDIV_CAM_FIMC0_MASK | EXYNOS4_CLKDIV_CAM_FIMC1_MASK | > - EXYNOS4_CLKDIV_CAM_FIMC2_MASK | EXYNOS4_CLKDIV_CAM_FIMC3_MASK); > - > - tmp |= ((exynos4x12_clkdiv_sclkip[index][2] << > - EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) | > - (exynos4x12_clkdiv_sclkip[index][2] << > - EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) | > - (exynos4x12_clkdiv_sclkip[index][2] << > - EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) | > - (exynos4x12_clkdiv_sclkip[index][2] << > - EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT)); > - > - __raw_writel(tmp, EXYNOS4_CLKDIV_CAM); > - > - do { > - tmp = __raw_readl(EXYNOS4_CLKDIV_STAT_CAM1); > - } while (tmp & 0x1111); > - > - return 0; > -} > - > - > -static void busfreq_mon_reset(struct busfreq_data *data) > -{ > - unsigned int i; > - > - for (i = 0; i < 2; i++) { > - void __iomem *ppmu_base = data->dmc[i].hw_base; > - > - /* Reset PPMU */ > - __raw_writel(0x8000000f, ppmu_base + 0xf010); > - __raw_writel(0x8000000f, ppmu_base + 0xf050); > - __raw_writel(0x6, ppmu_base + 0xf000); > - __raw_writel(0x0, ppmu_base + 0xf100); > - > - /* Set PPMU Event */ > - data->dmc[i].event = 0x6; > - __raw_writel(((data->dmc[i].event << 12) | 0x1), > - ppmu_base + 0xfc); > - > - /* Start PPMU */ > - __raw_writel(0x1, ppmu_base + 0xf000); > - } > -} > - > -static void exynos4_read_ppmu(struct busfreq_data *data) > -{ > - int i, j; > - > - for (i = 0; i < 2; i++) { > - void __iomem *ppmu_base = data->dmc[i].hw_base; > - u32 overflow; > - > - /* Stop PPMU */ > - __raw_writel(0x0, ppmu_base + 0xf000); > - > - /* Update local data from PPMU */ > - overflow = __raw_readl(ppmu_base + 0xf050); > - > - data->dmc[i].ccnt = __raw_readl(ppmu_base + 0xf100); > - data->dmc[i].ccnt_overflow = overflow & (1 << 31); > - > - for (j = 0; j < PPMU_PMNCNT_MAX; j++) { > - data->dmc[i].count[j] = __raw_readl( > - ppmu_base + (0xf110 + (0x10 * j))); > - data->dmc[i].count_overflow[j] = overflow & (1 << j); > - } > - } > - > - busfreq_mon_reset(data); > -} > - > -static int exynos4x12_get_intspec(unsigned long mifclk) > -{ > - int i = 0; > - > - while (exynos4x12_intclk_table[i].clk) { > - if (exynos4x12_intclk_table[i].clk <= mifclk) > - return i; > - i++; > - } > - > - return -EINVAL; > -} > - > -static int exynos4_bus_setvolt(struct busfreq_data *data, struct opp *opp, > - struct opp *oldopp) > -{ > - int err = 0, tmp; > - unsigned long volt = opp_get_voltage(opp); > - > - switch (data->type) { > - case TYPE_BUSF_EXYNOS4210: > - /* OPP represents DMC clock + INT voltage */ > - err = regulator_set_voltage(data->vdd_int, volt, > - MAX_SAFEVOLT); > - break; > - case TYPE_BUSF_EXYNOS4x12: > - /* OPP represents MIF clock + MIF voltage */ > - err = regulator_set_voltage(data->vdd_mif, volt, > - MAX_SAFEVOLT); > - if (err) > - break; > - > - tmp = exynos4x12_get_intspec(opp_get_freq(opp)); > - if (tmp < 0) { > - err = tmp; > - regulator_set_voltage(data->vdd_mif, > - opp_get_voltage(oldopp), > - MAX_SAFEVOLT); > - break; > - } > - err = regulator_set_voltage(data->vdd_int, > - exynos4x12_intclk_table[tmp].volt, > - MAX_SAFEVOLT); > - /* Try to recover */ > - if (err) > - regulator_set_voltage(data->vdd_mif, > - opp_get_voltage(oldopp), > - MAX_SAFEVOLT); > - break; > - default: > - err = -EINVAL; > - } > - > - return err; > -} > - > -static int exynos4_bus_target(struct device *dev, unsigned long *_freq, > - u32 flags) > -{ > - int err = 0; > - struct platform_device *pdev = container_of(dev, struct platform_device, > - dev); > - struct busfreq_data *data = platform_get_drvdata(pdev); > - struct opp *opp = devfreq_recommended_opp(dev, _freq, flags); > - unsigned long freq = opp_get_freq(opp); > - unsigned long old_freq = opp_get_freq(data->curr_opp); > - > - if (IS_ERR(opp)) > - return PTR_ERR(opp); > - > - if (old_freq == freq) > - return 0; > - > - dev_dbg(dev, "targetting %lukHz %luuV\n", freq, opp_get_voltage(opp)); > - > - mutex_lock(&data->lock); > - > - if (data->disabled) > - goto out; > - > - if (old_freq < freq) > - err = exynos4_bus_setvolt(data, opp, data->curr_opp); > - if (err) > - goto out; > - > - if (old_freq != freq) { > - switch (data->type) { > - case TYPE_BUSF_EXYNOS4210: > - err = exynos4210_set_busclk(data, opp); > - break; > - case TYPE_BUSF_EXYNOS4x12: > - err = exynos4x12_set_busclk(data, opp); > - break; > - default: > - err = -EINVAL; > - } > - } > - if (err) > - goto out; > - > - if (old_freq > freq) > - err = exynos4_bus_setvolt(data, opp, data->curr_opp); > - if (err) > - goto out; > - > - data->curr_opp = opp; > -out: > - mutex_unlock(&data->lock); > - return err; > -} > - > -static int exynos4_get_busier_dmc(struct busfreq_data *data) > -{ > - u64 p0 = data->dmc[0].count[0]; > - u64 p1 = data->dmc[1].count[0]; > - > - p0 *= data->dmc[1].ccnt; > - p1 *= data->dmc[0].ccnt; > - > - if (data->dmc[1].ccnt == 0) > - return 0; > - > - if (p0 > p1) > - return 0; > - return 1; > -} > - > -static int exynos4_bus_get_dev_status(struct device *dev, > - struct devfreq_dev_status *stat) > -{ > - struct busfreq_data *data = dev_get_drvdata(dev); > - int busier_dmc; > - int cycles_x2 = 2; /* 2 x cycles */ > - void __iomem *addr; > - u32 timing; > - u32 memctrl; > - > - exynos4_read_ppmu(data); > - busier_dmc = exynos4_get_busier_dmc(data); > - stat->current_frequency = opp_get_freq(data->curr_opp); > - > - if (busier_dmc) > - addr = S5P_VA_DMC1; > - else > - addr = S5P_VA_DMC0; > - > - memctrl = __raw_readl(addr + 0x04); /* one of DDR2/3/LPDDR2 */ > - timing = __raw_readl(addr + 0x38); /* CL or WL/RL values */ > - > - switch ((memctrl >> 8) & 0xf) { > - case 0x4: /* DDR2 */ > - cycles_x2 = ((timing >> 16) & 0xf) * 2; > - break; > - case 0x5: /* LPDDR2 */ > - case 0x6: /* DDR3 */ > - cycles_x2 = ((timing >> 8) & 0xf) + ((timing >> 0) & 0xf); > - break; > - default: > - pr_err("%s: Unknown Memory Type(%d).\n", __func__, > - (memctrl >> 8) & 0xf); > - return -EINVAL; > - } > - > - /* Number of cycles spent on memory access */ > - stat->busy_time = data->dmc[busier_dmc].count[0] / 2 * (cycles_x2 + 2); > - stat->busy_time *= 100 / BUS_SATURATION_RATIO; > - stat->total_time = data->dmc[busier_dmc].ccnt; > - > - /* If the counters have overflown, retry */ > - if (data->dmc[busier_dmc].ccnt_overflow || > - data->dmc[busier_dmc].count_overflow[0]) > - return -EAGAIN; > - > - return 0; > -} > - > -static void exynos4_bus_exit(struct device *dev) > -{ > - struct busfreq_data *data = dev_get_drvdata(dev); > - > - devfreq_unregister_opp_notifier(dev, data->devfreq); > -} > - > -static struct devfreq_dev_profile exynos4_devfreq_profile = { > - .initial_freq = 400000, > - .polling_ms = 50, > - .target = exynos4_bus_target, > - .get_dev_status = exynos4_bus_get_dev_status, > - .exit = exynos4_bus_exit, > -}; > - > -static int exynos4210_init_tables(struct busfreq_data *data) > -{ > - u32 tmp; > - int mgrp; > - int i, err = 0; > - > - tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); > - for (i = LV_0; i < EX4210_LV_NUM; i++) { > - tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | > - EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK | > - EXYNOS4_CLKDIV_DMC0_DPHY_MASK | > - EXYNOS4_CLKDIV_DMC0_DMC_MASK | > - EXYNOS4_CLKDIV_DMC0_DMCD_MASK | > - EXYNOS4_CLKDIV_DMC0_DMCP_MASK | > - EXYNOS4_CLKDIV_DMC0_COPY2_MASK | > - EXYNOS4_CLKDIV_DMC0_CORETI_MASK); > - > - tmp |= ((exynos4210_clkdiv_dmc0[i][0] << > - EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | > - (exynos4210_clkdiv_dmc0[i][1] << > - EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | > - (exynos4210_clkdiv_dmc0[i][2] << > - EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | > - (exynos4210_clkdiv_dmc0[i][3] << > - EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | > - (exynos4210_clkdiv_dmc0[i][4] << > - EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | > - (exynos4210_clkdiv_dmc0[i][5] << > - EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) | > - (exynos4210_clkdiv_dmc0[i][6] << > - EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) | > - (exynos4210_clkdiv_dmc0[i][7] << > - EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT)); > - > - data->dmc_divtable[i] = tmp; > - } > - > - tmp = __raw_readl(EXYNOS4_CLKDIV_TOP); > - for (i = LV_0; i < EX4210_LV_NUM; i++) { > - tmp &= ~(EXYNOS4_CLKDIV_TOP_ACLK200_MASK | > - EXYNOS4_CLKDIV_TOP_ACLK100_MASK | > - EXYNOS4_CLKDIV_TOP_ACLK160_MASK | > - EXYNOS4_CLKDIV_TOP_ACLK133_MASK | > - EXYNOS4_CLKDIV_TOP_ONENAND_MASK); > - > - tmp |= ((exynos4210_clkdiv_top[i][0] << > - EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) | > - (exynos4210_clkdiv_top[i][1] << > - EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | > - (exynos4210_clkdiv_top[i][2] << > - EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | > - (exynos4210_clkdiv_top[i][3] << > - EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | > - (exynos4210_clkdiv_top[i][4] << > - EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT)); > - > - data->top_divtable[i] = tmp; > - } > - > -#ifdef CONFIG_EXYNOS_ASV > - tmp = exynos4_result_of_asv; > -#else > - tmp = 0; /* Max voltages for the reliability of the unknown */ > -#endif > - > - pr_debug("ASV Group of Exynos4 is %d\n", tmp); > - /* Use merged grouping for voltage */ > - switch (tmp) { > - case 0: > - mgrp = 0; > - break; > - case 1: > - case 2: > - mgrp = 1; > - break; > - case 3: > - case 4: > - mgrp = 2; > - break; > - case 5: > - case 6: > - mgrp = 3; > - break; > - case 7: > - mgrp = 4; > - break; > - default: > - pr_warn("Unknown ASV Group. Use max voltage.\n"); > - mgrp = 0; > - } > - > - for (i = LV_0; i < EX4210_LV_NUM; i++) > - exynos4210_busclk_table[i].volt = exynos4210_asv_volt[mgrp][i]; > - > - for (i = LV_0; i < EX4210_LV_NUM; i++) { > - err = opp_add(data->dev, exynos4210_busclk_table[i].clk, > - exynos4210_busclk_table[i].volt); > - if (err) { > - dev_err(data->dev, "Cannot add opp entries.\n"); > - return err; > - } > - } > - > - > - return 0; > -} > - > -static int exynos4x12_init_tables(struct busfreq_data *data) > -{ > - unsigned int i; > - unsigned int tmp; > - int ret; > - > - /* Enable pause function for DREX2 DVFS */ > - tmp = __raw_readl(EXYNOS4_DMC_PAUSE_CTRL); > - tmp |= EXYNOS4_DMC_PAUSE_ENABLE; > - __raw_writel(tmp, EXYNOS4_DMC_PAUSE_CTRL); > - > - tmp = __raw_readl(EXYNOS4_CLKDIV_DMC0); > - > - for (i = 0; i < EX4x12_LV_NUM; i++) { > - tmp &= ~(EXYNOS4_CLKDIV_DMC0_ACP_MASK | > - EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK | > - EXYNOS4_CLKDIV_DMC0_DPHY_MASK | > - EXYNOS4_CLKDIV_DMC0_DMC_MASK | > - EXYNOS4_CLKDIV_DMC0_DMCD_MASK | > - EXYNOS4_CLKDIV_DMC0_DMCP_MASK); > - > - tmp |= ((exynos4x12_clkdiv_dmc0[i][0] << > - EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | > - (exynos4x12_clkdiv_dmc0[i][1] << > - EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | > - (exynos4x12_clkdiv_dmc0[i][2] << > - EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | > - (exynos4x12_clkdiv_dmc0[i][3] << > - EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | > - (exynos4x12_clkdiv_dmc0[i][4] << > - EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | > - (exynos4x12_clkdiv_dmc0[i][5] << > - EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT)); > - > - data->dmc_divtable[i] = tmp; > - } > - > -#ifdef CONFIG_EXYNOS_ASV > - tmp = exynos4_result_of_asv; > -#else > - tmp = 0; /* Max voltages for the reliability of the unknown */ > -#endif > - > - if (tmp > 8) > - tmp = 0; > - pr_debug("ASV Group of Exynos4x12 is %d\n", tmp); > - > - for (i = 0; i < EX4x12_LV_NUM; i++) { > - exynos4x12_mifclk_table[i].volt = > - exynos4x12_mif_step_50[tmp][i]; > - exynos4x12_intclk_table[i].volt = > - exynos4x12_int_volt[tmp][i]; > - } > - > - for (i = 0; i < EX4x12_LV_NUM; i++) { > - ret = opp_add(data->dev, exynos4x12_mifclk_table[i].clk, > - exynos4x12_mifclk_table[i].volt); > - if (ret) { > - dev_err(data->dev, "Fail to add opp entries.\n"); > - return ret; > - } > - } > - > - return 0; > -} > - > -static int exynos4_busfreq_pm_notifier_event(struct notifier_block *this, > - unsigned long event, void *ptr) > -{ > - struct busfreq_data *data = container_of(this, struct busfreq_data, > - pm_notifier); > - struct opp *opp; > - unsigned long maxfreq = ULONG_MAX; > - int err = 0; > - > - switch (event) { > - case PM_SUSPEND_PREPARE: > - /* Set Fastest and Deactivate DVFS */ > - mutex_lock(&data->lock); > - > - data->disabled = true; > - > - opp = opp_find_freq_floor(data->dev, &maxfreq); > - > - err = exynos4_bus_setvolt(data, opp, data->curr_opp); > - if (err) > - goto unlock; > - > - switch (data->type) { > - case TYPE_BUSF_EXYNOS4210: > - err = exynos4210_set_busclk(data, opp); > - break; > - case TYPE_BUSF_EXYNOS4x12: > - err = exynos4x12_set_busclk(data, opp); > - break; > - default: > - err = -EINVAL; > - } > - if (err) > - goto unlock; > - > - data->curr_opp = opp; > -unlock: > - mutex_unlock(&data->lock); > - if (err) > - return err; > - return NOTIFY_OK; > - case PM_POST_RESTORE: > - case PM_POST_SUSPEND: > - /* Reactivate */ > - mutex_lock(&data->lock); > - data->disabled = false; > - mutex_unlock(&data->lock); > - return NOTIFY_OK; > - } > - > - return NOTIFY_DONE; > -} > - > -static __devinit int exynos4_busfreq_probe(struct platform_device *pdev) > -{ > - struct busfreq_data *data; > - struct opp *opp; > - struct device *dev = &pdev->dev; > - int err = 0; > - > - data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data), GFP_KERNEL); > - if (data == NULL) { > - dev_err(dev, "Cannot allocate memory.\n"); > - return -ENOMEM; > - } > - > - data->type = pdev->id_entry->driver_data; > - data->dmc[0].hw_base = S5P_VA_DMC0; > - data->dmc[1].hw_base = S5P_VA_DMC1; > - data->pm_notifier.notifier_call = exynos4_busfreq_pm_notifier_event; > - data->dev = dev; > - mutex_init(&data->lock); > - > - switch (data->type) { > - case TYPE_BUSF_EXYNOS4210: > - err = exynos4210_init_tables(data); > - break; > - case TYPE_BUSF_EXYNOS4x12: > - err = exynos4x12_init_tables(data); > - break; > - default: > - dev_err(dev, "Cannot determine the device id %d\n", data->type); > - err = -EINVAL; > - } > - if (err) > - return err; > - > - data->vdd_int = devm_regulator_get(dev, "vdd_int"); > - if (IS_ERR(data->vdd_int)) { > - dev_err(dev, "Cannot get the regulator \"vdd_int\"\n"); > - return PTR_ERR(data->vdd_int); > - } > - if (data->type == TYPE_BUSF_EXYNOS4x12) { > - data->vdd_mif = devm_regulator_get(dev, "vdd_mif"); > - if (IS_ERR(data->vdd_mif)) { > - dev_err(dev, "Cannot get the regulator \"vdd_mif\"\n"); > - return PTR_ERR(data->vdd_mif); > - } > - } > - > - opp = opp_find_freq_floor(dev, &exynos4_devfreq_profile.initial_freq); > - if (IS_ERR(opp)) { > - dev_err(dev, "Invalid initial frequency %lu kHz.\n", > - exynos4_devfreq_profile.initial_freq); > - return PTR_ERR(opp); > - } > - data->curr_opp = opp; > - > - platform_set_drvdata(pdev, data); > - > - busfreq_mon_reset(data); > - > - data->devfreq = devfreq_add_device(dev, &exynos4_devfreq_profile, > - "simple_ondemand", NULL); > - if (IS_ERR(data->devfreq)) > - return PTR_ERR(data->devfreq); > - > - devfreq_register_opp_notifier(dev, data->devfreq); > - > - err = register_pm_notifier(&data->pm_notifier); > - if (err) { > - dev_err(dev, "Failed to setup pm notifier\n"); > - devfreq_remove_device(data->devfreq); > - return err; > - } > - > - return 0; > -} > - > -static __devexit int exynos4_busfreq_remove(struct platform_device *pdev) > -{ > - struct busfreq_data *data = platform_get_drvdata(pdev); > - > - unregister_pm_notifier(&data->pm_notifier); > - devfreq_remove_device(data->devfreq); > - > - return 0; > -} > - > -static int exynos4_busfreq_resume(struct device *dev) > -{ > - struct busfreq_data *data = dev_get_drvdata(dev); > - > - busfreq_mon_reset(data); > - return 0; > -} > - > -static const struct dev_pm_ops exynos4_busfreq_pm = { > - .resume = exynos4_busfreq_resume, > -}; > - > -static const struct platform_device_id exynos4_busfreq_id[] = { > - { "exynos4210-busfreq", TYPE_BUSF_EXYNOS4210 }, > - { "exynos4412-busfreq", TYPE_BUSF_EXYNOS4x12 }, > - { "exynos4212-busfreq", TYPE_BUSF_EXYNOS4x12 }, > - { }, > -}; > - > -static struct platform_driver exynos4_busfreq_driver = { > - .probe = exynos4_busfreq_probe, > - .remove = __devexit_p(exynos4_busfreq_remove), > - .id_table = exynos4_busfreq_id, > - .driver = { > - .name = "exynos4-busfreq", > - .owner = THIS_MODULE, > - .pm = &exynos4_busfreq_pm, > - }, > -}; > - > -static int __init exynos4_busfreq_init(void) > -{ > - return platform_driver_register(&exynos4_busfreq_driver); > -} > -late_initcall(exynos4_busfreq_init); > - > -static void __exit exynos4_busfreq_exit(void) > -{ > - platform_driver_unregister(&exynos4_busfreq_driver); > -} > -module_exit(exynos4_busfreq_exit); > - > -MODULE_LICENSE("GPL"); > -MODULE_DESCRIPTION("EXYNOS4 busfreq driver with devfreq framework"); > -MODULE_AUTHOR("MyungJoo Ham <myungjoo.ham@samsung.com>"); > -- > 1.7.8.6 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- MyungJoo Ham, Ph.D. Mobile Software Platform Lab, DMC Business, Samsung Electronics ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 3/4] PM: DEVFREQ: Move exynos4 devfreq driver into a new sub-directory 2013-01-09 12:06 ` [PATCH 3/4] PM: DEVFREQ: Move exynos4 devfreq driver into a new sub-directory Abhilash Kesavan 2013-01-14 14:30 ` MyungJoo Ham @ 2013-01-18 13:24 ` Abhilash Kesavan 1 sibling, 0 replies; 18+ messages in thread From: Abhilash Kesavan @ 2013-01-18 13:24 UTC (permalink / raw) To: myungjoo.ham, linux-kernel, linux-pm, kgene.kim Cc: kyungmin.park, rjw, jhbird.choi In anticipation of the new exynos5 devfreq and ppmu driver, create an exynos sub-directory. Move the existing exynos4 devfreq driver into the same. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Jonghwan Choi <jhbird.choi@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> --- Note: No changes, rebased against latest tree. Only compile tested for Exynos4. drivers/devfreq/Makefile | 2 +- drivers/devfreq/exynos/Makefile | 2 ++ drivers/devfreq/{ => exynos}/exynos4_bus.c | 0 3 files changed, 3 insertions(+), 1 deletions(-) create mode 100644 drivers/devfreq/exynos/Makefile rename drivers/devfreq/{ => exynos}/exynos4_bus.c (100%) diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 8c46423..3bc1fef 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -5,4 +5,4 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o # DEVFREQ Drivers -obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o +obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/ diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile new file mode 100644 index 0000000..1498823 --- /dev/null +++ b/drivers/devfreq/exynos/Makefile @@ -0,0 +1,2 @@ +# Exynos DEVFREQ Drivers +obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o diff --git a/drivers/devfreq/exynos4_bus.c b/drivers/devfreq/exynos/exynos4_bus.c similarity index 100% rename from drivers/devfreq/exynos4_bus.c rename to drivers/devfreq/exynos/exynos4_bus.c -- 1.7.8.6 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/4] PM/Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 2013-01-09 12:06 [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support Abhilash Kesavan 2013-01-09 12:06 ` [PATCH 2/4] ARM: EXYNOS5: Support Exynos5-bus devfreq driver Abhilash Kesavan 2013-01-09 12:06 ` [PATCH 3/4] PM: DEVFREQ: Move exynos4 devfreq driver into a new sub-directory Abhilash Kesavan @ 2013-01-09 12:06 ` Abhilash Kesavan 2013-01-09 14:14 ` Rajagopal Venkat 2013-01-18 13:24 ` [PATCH v4 4/4] PM: Devfreq: " Abhilash Kesavan 2013-01-14 14:26 ` [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support MyungJoo Ham 2013-01-18 13:23 ` [PATCH v4 " Abhilash Kesavan 4 siblings, 2 replies; 18+ messages in thread From: Abhilash Kesavan @ 2013-01-09 12:06 UTC (permalink / raw) To: myungjoo.ham, linux-kernel, linux-pm, kgene.kim Cc: kyungmin.park, rjw, jhbird.choi, Abhilash Kesavan Exynos5-bus device devfreq driver monitors PPMU counters and adjusts operating frequencies and voltages with OPP. ASV should be used to provide appropriate voltages as per the speed group of the SoC rather than using a constant 1.025V. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Jonghwan Choi <jhbird.choi@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> --- drivers/devfreq/Kconfig | 10 + drivers/devfreq/Makefile | 1 + drivers/devfreq/exynos/Makefile | 1 + drivers/devfreq/exynos/exynos5_bus.c | 469 +++++++++++++++++++++++++++++++++ drivers/devfreq/exynos/exynos5_ppmu.c | 412 +++++++++++++++++++++++++++++ drivers/devfreq/exynos/exynos_ppmu.c | 56 ++++ include/linux/exynos5_ppmu.h | 26 ++ include/linux/exynos_ppmu.h | 79 ++++++ 8 files changed, 1054 insertions(+), 0 deletions(-) create mode 100644 drivers/devfreq/exynos/exynos5_bus.c create mode 100644 drivers/devfreq/exynos/exynos5_ppmu.c create mode 100644 drivers/devfreq/exynos/exynos_ppmu.c create mode 100644 include/linux/exynos5_ppmu.h create mode 100644 include/linux/exynos_ppmu.h diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 0f079be..1560d0d 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -78,4 +78,14 @@ config ARM_EXYNOS4_BUS_DEVFREQ To operate with optimal voltages, ASV support is required (CONFIG_EXYNOS_ASV). +config ARM_EXYNOS5_BUS_DEVFREQ + bool "ARM Exynos5250 Bus DEVFREQ Driver" + depends on SOC_EXYNOS5250 + select ARCH_HAS_OPP + select DEVFREQ_GOV_SIMPLE_ONDEMAND + help + This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int). + It reads PPMU counters of memory controllers and adjusts the + operating frequencies and voltages with OPP support. + endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 3bc1fef..16138c9 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o # DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/ +obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/ diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile index 1498823..69713a8 100644 --- a/drivers/devfreq/exynos/Makefile +++ b/drivers/devfreq/exynos/Makefile @@ -1,2 +1,3 @@ # Exynos DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o +obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_ppmu.o exynos5_bus.o diff --git a/drivers/devfreq/exynos/exynos5_bus.c b/drivers/devfreq/exynos/exynos5_bus.c new file mode 100644 index 0000000..1d4a4b1 --- /dev/null +++ b/drivers/devfreq/exynos/exynos5_bus.c @@ -0,0 +1,469 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS5 INT clock frequency scaling support using DEVFREQ framework + * Based on work done by Jonghwan Choi <jhbird.choi@samsung.com> + * Support for only EXYNOS5250 is present. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/slab.h> +#include <linux/suspend.h> +#include <linux/opp.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/pm_qos.h> +#include <linux/regulator/consumer.h> +#include <linux/exynos_ppmu.h> +#include <linux/exynos5_ppmu.h> + +#include "../governor.h" + +#define MAX_SAFEVOLT 1100000 /* 1.10V */ +/* Assume that the bus is saturated if the utilization is 25% */ +#define INT_BUS_SATURATION_RATIO 25 +#define EXYNOS5_BUS_INT_POLL_TIME msecs_to_jiffies(100) + +enum int_level_idx { + LV_0, + LV_1, + LV_2, + LV_3, + LV_4, + _LV_END +}; + +struct busfreq_data_int { + struct device *dev; + struct devfreq *devfreq; + bool disabled; + struct regulator *vdd_int; + unsigned long curr_freq; + struct notifier_block pm_notifier; + struct mutex lock; + struct pm_qos_request int_req; + struct clk *int_clk; + struct exynos5_ppmu_handle *ppmu; + struct delayed_work work; + int busy; +}; + +struct int_bus_opp_table { + unsigned int idx; + unsigned long clk; + unsigned long volt; +}; + +static struct int_bus_opp_table exynos5_int_opp_table[] = { + {LV_0, 266000, 1025000}, + {LV_1, 200000, 1025000}, + {LV_2, 160000, 1025000}, + {LV_3, 133000, 1025000}, + {LV_4, 100000, 1025000}, + {0, 0, 0}, +}; + +static int exynos5_int_setvolt(struct busfreq_data_int *data, + unsigned long volt) +{ + return regulator_set_voltage(data->vdd_int, volt, MAX_SAFEVOLT); +} + +static int exynos5_busfreq_int_target(struct device *dev, unsigned long *_freq, + u32 flags) +{ + int err = 0; + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + struct opp *opp; + unsigned long old_freq, freq; + unsigned long volt; + + rcu_read_lock(); + opp = devfreq_recommended_opp(dev, _freq, flags); + if (IS_ERR(opp)) { + rcu_read_unlock(); + dev_err(dev, "%s: Invalid OPP.\n", __func__); + return PTR_ERR(opp); + } + + freq = opp_get_freq(opp); + volt = opp_get_voltage(opp); + rcu_read_unlock(); + + old_freq = data->curr_freq; + + if (old_freq == freq) + return 0; + + dev_dbg(dev, "targetting %lukHz %luuV\n", freq, volt); + + mutex_lock(&data->lock); + + if (data->disabled) + goto out; + + if (freq > exynos5_int_opp_table[_LV_END - 1].clk) + pm_qos_update_request(&data->int_req, + data->busy * old_freq * 16 / 100000); + else + pm_qos_update_request(&data->int_req, -1); + + if (old_freq < freq) + err = exynos5_int_setvolt(data, volt); + if (err) + goto out; + + err = clk_set_rate(data->int_clk, freq * 1000); + + if (err) + goto out; + + if (old_freq > freq) + err = exynos5_int_setvolt(data, volt); + if (err) + goto out; + + data->curr_freq = freq; +out: + mutex_unlock(&data->lock); + return err; +} + +static int exynos5_int_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + stat->current_frequency = data->curr_freq; + stat->busy_time = data->busy; + stat->total_time = 100; + + return 0; +} + +static void exynos5_int_poll_start(struct busfreq_data_int *data) +{ + schedule_delayed_work(&data->work, EXYNOS5_BUS_INT_POLL_TIME); +} + +static void exynos5_int_poll_stop(struct busfreq_data_int *data) +{ + cancel_delayed_work_sync(&data->work); +} + +static void exynos5_int_poll(struct work_struct *work) +{ + struct delayed_work *dwork; + struct busfreq_data_int *data; + int ret; + + dwork = to_delayed_work(work); + data = container_of(dwork, struct busfreq_data_int, work); + + ret = exynos5_ppmu_get_busy(data->ppmu, PPMU_SET_RIGHT); + + if (ret >= 0) { + data->busy = ret; + mutex_lock(&data->devfreq->lock); + update_devfreq(data->devfreq); + mutex_unlock(&data->devfreq->lock); + } + + schedule_delayed_work(&data->work, EXYNOS5_BUS_INT_POLL_TIME); +} + +static void exynos5_int_exit(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + devfreq_unregister_opp_notifier(dev, data->devfreq); +} + +static struct devfreq_dev_profile exynos5_devfreq_int_profile = { + .initial_freq = 160000, + .polling_ms = 0, + .target = exynos5_busfreq_int_target, + .get_dev_status = exynos5_int_get_dev_status, + .exit = exynos5_int_exit, +}; + +static int exynos5250_init_int_tables(struct busfreq_data_int *data) +{ + int i, err = 0; + + for (i = LV_0; i < _LV_END; i++) { + err = opp_add(data->dev, exynos5_int_opp_table[i].clk, + exynos5_int_opp_table[i].volt); + if (err) { + dev_err(data->dev, "Cannot add opp entries.\n"); + return err; + } + } + + return 0; +} +static struct devfreq_simple_ondemand_data exynos5_int_ondemand_data = { + .downdifferential = 2, + .upthreshold = INT_BUS_SATURATION_RATIO, +}; + +static int exynos5_busfreq_int_pm_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct busfreq_data_int *data = container_of(this, + struct busfreq_data_int, pm_notifier); + struct opp *opp; + unsigned long maxfreq = ULONG_MAX; + unsigned long freq; + unsigned long volt; + int err = 0; + + switch (event) { + case PM_SUSPEND_PREPARE: + /* Set Fastest and Deactivate DVFS */ + mutex_lock(&data->lock); + + data->disabled = true; + + rcu_read_lock(); + opp = opp_find_freq_floor(data->dev, &maxfreq); + if (IS_ERR(opp)) { + rcu_read_unlock(); + err = PTR_ERR(opp); + goto unlock; + } + freq = opp_get_freq(opp); + volt = opp_get_voltage(opp); + rcu_read_unlock(); + + err = exynos5_int_setvolt(data, volt); + if (err) + goto unlock; + + err = clk_set_rate(data->int_clk, freq * 1000); + + if (err) + goto unlock; + + data->curr_freq = freq; +unlock: + mutex_unlock(&data->lock); + if (err) + return NOTIFY_BAD; + return NOTIFY_OK; + case PM_POST_RESTORE: + case PM_POST_SUSPEND: + /* Reactivate */ + mutex_lock(&data->lock); + data->disabled = false; + mutex_unlock(&data->lock); + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +static __devinit int exynos5_busfreq_int_probe(struct platform_device *pdev) +{ + struct busfreq_data_int *data; + struct opp *opp; + struct device *dev = &pdev->dev; + unsigned long initial_freq; + unsigned long initial_volt; + int err = 0; + + data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data_int), + GFP_KERNEL); + if (data == NULL) { + dev_err(dev, "Cannot allocate memory.\n"); + return -ENOMEM; + } + + data->pm_notifier.notifier_call = exynos5_busfreq_int_pm_notifier_event; + data->dev = dev; + mutex_init(&data->lock); + + err = exynos5250_init_int_tables(data); + if (err) + goto err_regulator; + + data->vdd_int = regulator_get(dev, "vdd_int"); + if (IS_ERR(data->vdd_int)) { + dev_err(dev, "Cannot get the regulator \"vdd_int\"\n"); + err = PTR_ERR(data->vdd_int); + goto err_regulator; + } + + data->int_clk = clk_get(dev, "int_clk"); + if (IS_ERR(data->int_clk)) { + dev_err(dev, "Cannot get clock \"int_clk\"\n"); + err = PTR_ERR(data->int_clk); + goto err_clock; + } + + rcu_read_lock(); + opp = opp_find_freq_floor(dev, + &exynos5_devfreq_int_profile.initial_freq); + if (IS_ERR(opp)) { + rcu_read_unlock(); + dev_err(dev, "Invalid initial frequency %lu kHz.\n", + exynos5_devfreq_int_profile.initial_freq); + err = PTR_ERR(opp); + goto err_opp_add; + } + initial_freq = opp_get_freq(opp); + initial_volt = opp_get_voltage(opp); + rcu_read_unlock(); + data->curr_freq = initial_freq; + + err = clk_set_rate(data->int_clk, initial_freq * 1000); + if (err) { + dev_err(dev, "Failed to set initial frequency\n"); + goto err_opp_add; + } + + err = exynos5_int_setvolt(data, initial_volt); + if (err) + goto err_opp_add; + + platform_set_drvdata(pdev, data); + + data->ppmu = exynos5_ppmu_get(); + if (!data->ppmu) + goto err_ppmu_get; + + INIT_DELAYED_WORK(&data->work, exynos5_int_poll); + exynos5_int_poll_start(data); + + data->devfreq = devfreq_add_device(dev, &exynos5_devfreq_int_profile, + "simple_ondemand", + &exynos5_int_ondemand_data); + + if (IS_ERR(data->devfreq)) { + err = PTR_ERR(data->devfreq); + goto err_devfreq_add; + } + + devfreq_register_opp_notifier(dev, data->devfreq); + + err = register_pm_notifier(&data->pm_notifier); + if (err) { + dev_err(dev, "Failed to setup pm notifier\n"); + goto err_devfreq_add; + } + + /* TODO: Add a new QOS class for int/mif bus */ + pm_qos_add_request(&data->int_req, PM_QOS_NETWORK_THROUGHPUT, -1); + + return 0; + +err_devfreq_add: + devfreq_remove_device(data->devfreq); + exynos5_int_poll_stop(data); +err_ppmu_get: + platform_set_drvdata(pdev, NULL); +err_opp_add: + clk_put(data->int_clk); +err_clock: + regulator_put(data->vdd_int); +err_regulator: + return err; +} + +static __devexit int exynos5_busfreq_int_remove(struct platform_device *pdev) +{ + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + pm_qos_remove_request(&data->int_req); + unregister_pm_notifier(&data->pm_notifier); + devfreq_remove_device(data->devfreq); + regulator_put(data->vdd_int); + clk_put(data->int_clk); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +#ifdef CONFIG_PM_SLEEP +static int exynos5_busfreq_int_suspend(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + exynos5_int_poll_stop(data); + return 0; +} + +static int exynos5_busfreq_int_resume(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + exynos5_int_poll_start(data); + return 0; +} +#endif + +static SIMPLE_DEV_PM_OPS(exynos5_busfreq_int_pm, exynos5_busfreq_int_suspend, + exynos5_busfreq_int_resume); + +/* platform device pointer for exynos5 devfreq device. */ +static struct platform_device *exynos5_devfreq_pdev; + +static struct platform_driver exynos5_busfreq_int_driver = { + .probe = exynos5_busfreq_int_probe, + .remove = __devexit_p(exynos5_busfreq_int_remove), + .driver = { + .name = "exynos5-bus-int", + .owner = THIS_MODULE, + .pm = &exynos5_busfreq_int_pm, + }, +}; + +static int __init exynos5_busfreq_int_init(void) +{ + int ret; + + ret = platform_driver_register(&exynos5_busfreq_int_driver); + if (ret < 0) + goto out; + + exynos5_devfreq_pdev = + platform_device_register_simple("exynos5-bus-int", -1, NULL, 0); + if (IS_ERR_OR_NULL(exynos5_devfreq_pdev)) { + ret = PTR_ERR(exynos5_devfreq_pdev); + goto out1; + } + + return 0; +out1: + platform_driver_unregister(&exynos5_busfreq_int_driver); +out: + return ret; +} +late_initcall(exynos5_busfreq_int_init); + +static void __exit exynos5_busfreq_int_exit(void) +{ + platform_device_unregister(exynos5_devfreq_pdev); + platform_driver_unregister(&exynos5_busfreq_int_driver); +} +module_exit(exynos5_busfreq_int_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("EXYNOS5 busfreq driver with devfreq framework"); diff --git a/drivers/devfreq/exynos/exynos5_ppmu.c b/drivers/devfreq/exynos/exynos5_ppmu.c new file mode 100644 index 0000000..0620f24 --- /dev/null +++ b/drivers/devfreq/exynos/exynos5_ppmu.c @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS5 PPMU support + * Support for only EXYNOS5250 is present. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/kernel.h> +#include <linux/debugfs.h> +#include <linux/delay.h> +#include <linux/hrtimer.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/slab.h> +#include <linux/exynos_ppmu.h> +#include <linux/exynos5_ppmu.h> + +#include <mach/map.h> + +#define FIXED_POINT_OFFSET (0x8) +#define FIXED_POINT_MASK (0xff) + +enum exynos5_ppmu_list { + PPMU_DDR_C, + PPMU_DDR_R1, + PPMU_DDR_L, + PPMU_RIGHT, + PPMU_CPU, + PPMU_END, +}; + +struct exynos5_ppmu_handle { + struct list_head node; + struct exynos_ppmu ppmu[PPMU_END]; +}; + +static DEFINE_SPINLOCK(exynos5_ppmu_lock); +static LIST_HEAD(exynos5_ppmu_handle_list); +static struct exynos_ppmu ppmu[PPMU_END]; + +static const char *exynos5_ppmu_name[PPMU_END] = { + [PPMU_DDR_C] = "DDR_C", + [PPMU_DDR_R1] = "DDR_R1", + [PPMU_DDR_L] = "DDR_L", + [PPMU_RIGHT] = "RIGHT", + [PPMU_CPU] = "CPU", +}; + +static void exynos5_ppmu_reset(struct exynos_ppmu *ppmu) +{ + unsigned long flags; + void __iomem *ppmu_base = ppmu->hw_base; + + /* Reset the performance and cycle counters */ + exynos_ppmu_reset(ppmu_base); + + /* Setup count registers for monitoring read/write transactions */ + ppmu->event[PPMU_PMNCNT0] = RD_DATA_COUNT; + exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT0, + ppmu->event[PPMU_PMNCNT0]); + ppmu->event[PPMU_PMCCNT1] = WR_DATA_COUNT; + exynos_ppmu_setevent(ppmu_base, PPMU_PMCCNT1, + ppmu->event[PPMU_PMCCNT1]); + ppmu->event[PPMU_PMNCNT3] = RDWR_DATA_COUNT; + exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3, + ppmu->event[PPMU_PMNCNT3]); + + local_irq_save(flags); + ppmu->reset_time = ktime_get(); + exynos_ppmu_start(ppmu_base); + local_irq_restore(flags); +} + +static void exynos5_ppmu_read(struct exynos_ppmu *ppmu) +{ + unsigned long flags; + ktime_t read_time; + ktime_t t; + int reg, j; + void __iomem *ppmu_base = ppmu->hw_base; + + local_irq_save(flags); + read_time = ktime_get(); + exynos_ppmu_stop(ppmu_base); + local_irq_restore(flags); + + /* Update local data from PPMU */ + ppmu->ccnt = __raw_readl(ppmu_base + PPMU_CCNT); + reg = __raw_readl(ppmu_base + PPMU_FLAG); + ppmu->ccnt_overflow = reg & PPMU_CCNT_OVERFLOW; + + for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) { + if (ppmu->event[j] == 0) + ppmu->count[j] = 0; + else + ppmu->count[j] = exynos_ppmu_read(ppmu_base, j); + } + t = ktime_sub(read_time, ppmu->reset_time); + ppmu->ns = ktime_to_ns(t); +} + +static void exynos5_ppmu_add(struct exynos_ppmu *to, struct exynos_ppmu *from) +{ + int i, j; + + for (i = 0; i < PPMU_END; i++) { + for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) + to[i].count[j] += from[i].count[j]; + + to[i].ccnt += from[i].ccnt; + if (to[i].ccnt < from[i].ccnt) + to[i].ccnt_overflow = true; + + to[i].ns += from[i].ns; + + if (from[i].ccnt_overflow) + to[i].ccnt_overflow = true; + } +} + +static void exynos5_ppmu_handle_clear(struct exynos5_ppmu_handle *handle) +{ + memset(&handle->ppmu, 0, sizeof(struct exynos_ppmu) * PPMU_END); +} + +static void exynos5_ppmu_update(void) +{ + int i; + struct exynos5_ppmu_handle *handle; + + for (i = 0; i < PPMU_END; i++) { + exynos5_ppmu_read(&ppmu[i]); + exynos5_ppmu_reset(&ppmu[i]); + } + + list_for_each_entry(handle, &exynos5_ppmu_handle_list, node) + exynos5_ppmu_add(handle->ppmu, ppmu); +} + +static int exynos5_ppmu_get_filter(enum exynos5_ppmu_sets filter, + enum exynos5_ppmu_list *start, enum exynos5_ppmu_list *end) +{ + switch (filter) { + case PPMU_SET_DDR: + *start = PPMU_DDR_C; + *end = PPMU_DDR_L; + break; + case PPMU_SET_RIGHT: + *start = PPMU_RIGHT; + *end = PPMU_RIGHT; + break; + case PPMU_SET_CPU: + *start = PPMU_CPU; + *end = PPMU_CPU; + break; + default: + return -EINVAL; + } + + return 0; +} + +int exynos5_ppmu_get_busy(struct exynos5_ppmu_handle *handle, + enum exynos5_ppmu_sets filter) +{ + unsigned long flags; + int i, temp, ret, busy = 0; + enum exynos5_ppmu_list start; + enum exynos5_ppmu_list end; + + ret = exynos5_ppmu_get_filter(filter, &start, &end); + if (ret < 0) + return ret; + + spin_lock_irqsave(&exynos5_ppmu_lock, flags); + + exynos5_ppmu_update(); + + for (i = start; i <= end; i++) { + if (handle->ppmu[i].ccnt_overflow) { + busy = -EOVERFLOW; + break; + } + temp = handle->ppmu[i].count[PPMU_PMNCNT3] * 100; + if (handle->ppmu[i].ccnt > 0) + temp /= handle->ppmu[i].ccnt; + if (temp > busy) + busy = temp; + } + + exynos5_ppmu_handle_clear(handle); + + spin_unlock_irqrestore(&exynos5_ppmu_lock, flags); + + return busy; +} + +static void exynos5_ppmu_put(struct exynos5_ppmu_handle *handle) +{ + unsigned long flags; + + spin_lock_irqsave(&exynos5_ppmu_lock, flags); + + list_del(&handle->node); + + spin_unlock_irqrestore(&exynos5_ppmu_lock, flags); + + kfree(handle); +} + +struct exynos5_ppmu_handle *exynos5_ppmu_get(void) +{ + struct exynos5_ppmu_handle *handle; + unsigned long flags; + + handle = kzalloc(sizeof(struct exynos5_ppmu_handle), GFP_KERNEL); + if (!handle) + return NULL; + + spin_lock_irqsave(&exynos5_ppmu_lock, flags); + + exynos5_ppmu_update(); + list_add_tail(&handle->node, &exynos5_ppmu_handle_list); + + spin_unlock_irqrestore(&exynos5_ppmu_lock, flags); + + return handle; +} + +static void exynos5_ppmu_debug_compute(struct exynos_ppmu *ppmu, + enum ppmu_counter i, u32 *sat, u32 *freq, u32 *bw) +{ + u64 ns = ppmu->ns; + u32 busy = ppmu->count[i]; + u32 total = ppmu->ccnt; + + u64 s; + u64 f; + u64 b; + + s = (u64)busy * 100 * (1 << FIXED_POINT_OFFSET); + s += total / 2; + do_div(s, total); + + f = (u64)total * 1000 * (1 << FIXED_POINT_OFFSET); + f += ns / 2; + f = div64_u64(f, ns); + + b = (u64)busy * (128 / 8) * 1000 * (1 << FIXED_POINT_OFFSET); + b += ns / 2; + b = div64_u64(b, ns); + + *sat = s; + *freq = f; + *bw = b; +} + +static void exynos5_ppmu_debug_show_one_counter(struct seq_file *s, + const char *name, const char *type, struct exynos_ppmu *ppmu, + enum ppmu_counter i, u32 *bw_total) +{ + u32 sat; + u32 freq; + u32 bw; + + exynos5_ppmu_debug_compute(ppmu, i, &sat, &freq, &bw); + + seq_printf(s, "%-10s %-10s %4u.%02u MBps %3u.%02u MHz %2u.%02u%%\n", + name, type, + bw >> FIXED_POINT_OFFSET, + (bw & FIXED_POINT_MASK) * 100 / (1 << FIXED_POINT_OFFSET), + freq >> FIXED_POINT_OFFSET, + (freq & FIXED_POINT_MASK) * 100 / (1 << FIXED_POINT_OFFSET), + sat >> FIXED_POINT_OFFSET, + (sat & FIXED_POINT_MASK) * 100 / (1 << FIXED_POINT_OFFSET)); + + *bw_total += bw; +} + +static void exynos5_ppmu_debug_show_one(struct seq_file *s, + const char *name, struct exynos_ppmu *ppmu, + u32 *bw_total) +{ + exynos5_ppmu_debug_show_one_counter(s, name, "read+write", + ppmu, PPMU_PMNCNT3, &bw_total[PPMU_PMNCNT3]); + exynos5_ppmu_debug_show_one_counter(s, "", "read", + ppmu, PPMU_PMNCNT0, &bw_total[PPMU_PMNCNT0]); + exynos5_ppmu_debug_show_one_counter(s, "", "write", + ppmu, PPMU_PMCCNT1, &bw_total[PPMU_PMCCNT1]); + +} + +static int exynos5_ppmu_debug_show(struct seq_file *s, void *d) +{ + int i; + u32 bw_total[PPMU_PMNCNT_MAX]; + struct exynos5_ppmu_handle *handle; + unsigned long flags; + + memset(bw_total, 0, sizeof(bw_total)); + + handle = exynos5_ppmu_get(); + msleep(100); + + spin_lock_irqsave(&exynos5_ppmu_lock, flags); + + exynos5_ppmu_update(); + + for (i = 0; i < PPMU_CPU; i++) + exynos5_ppmu_debug_show_one(s, exynos5_ppmu_name[i], + &handle->ppmu[i], bw_total); + + seq_printf(s, "%-10s %-10s %4u.%02u MBps\n", "total", "read+write", + bw_total[PPMU_PMNCNT3] >> FIXED_POINT_OFFSET, + (bw_total[PPMU_PMNCNT3] & FIXED_POINT_MASK) * + 100 / (1 << FIXED_POINT_OFFSET)); + seq_printf(s, "%-10s %-10s %4u.%02u MBps\n", "", "read", + bw_total[PPMU_PMNCNT0] >> FIXED_POINT_OFFSET, + (bw_total[PPMU_PMNCNT0] & FIXED_POINT_MASK) * + 100 / (1 << FIXED_POINT_OFFSET)); + seq_printf(s, "%-10s %-10s %4u.%02u MBps\n", "", "write", + bw_total[PPMU_PMCCNT1] >> FIXED_POINT_OFFSET, + (bw_total[PPMU_PMCCNT1] & FIXED_POINT_MASK) * + 100 / (1 << FIXED_POINT_OFFSET)); + + seq_printf(s, "\n"); + + exynos5_ppmu_debug_show_one(s, exynos5_ppmu_name[PPMU_CPU], + &ppmu[PPMU_CPU], bw_total); + + spin_unlock_irqrestore(&exynos5_ppmu_lock, flags); + + exynos5_ppmu_put(handle); + + return 0; +} + +static int exynos5_ppmu_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, exynos5_ppmu_debug_show, inode->i_private); +} + +static const struct file_operations exynos5_ppmu_debug_fops = { + .open = exynos5_ppmu_debug_open, + .read = seq_read, + .llseek = seq_lseek, + .release = single_release, +}; + +static int __init exynos5_ppmu_debug_init(void) +{ + debugfs_create_file("exynos5_bus", S_IRUGO, NULL, NULL, + &exynos5_ppmu_debug_fops); + return 0; +} +late_initcall(exynos5_ppmu_debug_init); + +static int exynos5_ppmu_probe(struct platform_device *pdev) +{ + struct resource *res; + int i; + + for (i = 0; i < PPMU_END; i++) { + /* get the memory region */ + res = platform_get_resource(pdev, IORESOURCE_MEM, i); + if (res == NULL) { + dev_err(&pdev->dev, "failed to get memory region resource\n"); + return -ENOENT; + } + + ppmu[i].hw_base = devm_request_and_ioremap(&pdev->dev, res); + if (ppmu->hw_base == NULL) { + dev_err(&pdev->dev, "failed to ioremap memory region\n"); + return -EINVAL; + } + } + + return 0; +} + +static int __devexit exynos5_ppmu_remove(struct platform_device *pdev) +{ + dev_dbg(&pdev->dev, "%s driver unloaded\n", pdev->name); + + return 0; +} + +static const struct of_device_id exynos5_ppmu_match[] = { + { + .compatible = "samsung,exynos5250-ppmu", + }, + {}, +}; + +static struct platform_driver exynos5_ppmu_driver = { + .probe = exynos5_ppmu_probe, + .remove = __devexit_p(exynos5_ppmu_remove), + .driver = { + .name = "exynos5-ppmu", + .owner = THIS_MODULE, + .of_match_table = of_match_ptr(exynos5_ppmu_match), + }, +}; +module_platform_driver(exynos5_ppmu_driver); diff --git a/drivers/devfreq/exynos/exynos_ppmu.c b/drivers/devfreq/exynos/exynos_ppmu.c new file mode 100644 index 0000000..da373be --- /dev/null +++ b/drivers/devfreq/exynos/exynos_ppmu.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS - PPMU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/io.h> + +#include <linux/exynos_ppmu.h> + +void exynos_ppmu_reset(void __iomem *ppmu_base) +{ + __raw_writel(PPMU_CYCLE_RESET | PPMU_COUNTER_RESET, ppmu_base); + __raw_writel(PPMU_ENABLE_CYCLE | + PPMU_ENABLE_COUNT0 | + PPMU_ENABLE_COUNT1 | + PPMU_ENABLE_COUNT2 | + PPMU_ENABLE_COUNT3, + ppmu_base + PPMU_CNTENS); +} + +void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch, + unsigned int evt) +{ + __raw_writel(evt, ppmu_base + PPMU_BEVTSEL(ch)); +} + +void exynos_ppmu_start(void __iomem *ppmu_base) +{ + __raw_writel(PPMU_ENABLE, ppmu_base); +} + +void exynos_ppmu_stop(void __iomem *ppmu_base) +{ + __raw_writel(PPMU_DISABLE, ppmu_base); +} + +unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch) +{ + unsigned int total; + + if (ch == PPMU_PMNCNT3) + total = ((__raw_readl(ppmu_base + PMCNT_OFFSET(ch)) << 8) | + __raw_readl(ppmu_base + PMCNT_OFFSET(ch + 1))); + else + total = __raw_readl(ppmu_base + PMCNT_OFFSET(ch)); + + return total; +} diff --git a/include/linux/exynos5_ppmu.h b/include/linux/exynos5_ppmu.h new file mode 100644 index 0000000..9f492c1 --- /dev/null +++ b/include/linux/exynos5_ppmu.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS5 PPMU header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __DEVFREQ_EXYNOS5_PPMU_H +#define __DEVFREQ_EXYNOS5_PPMU_H __FILE__ + +enum exynos5_ppmu_sets { + PPMU_SET_DDR, + PPMU_SET_RIGHT, + PPMU_SET_CPU, +}; + +struct exynos5_ppmu_handle *exynos5_ppmu_get(void); +extern int exynos5_ppmu_get_busy(struct exynos5_ppmu_handle *handle, + enum exynos5_ppmu_sets filter); + +#endif /* __DEVFREQ_EXYNOS5_PPMU_H */ + diff --git a/include/linux/exynos_ppmu.h b/include/linux/exynos_ppmu.h new file mode 100644 index 0000000..b46d31b --- /dev/null +++ b/include/linux/exynos_ppmu.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS PPMU header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __DEVFREQ_EXYNOS_PPMU_H +#define __DEVFREQ_EXYNOS_PPMU_H __FILE__ + +#include <linux/ktime.h> + +/* For PPMU Control */ +#define PPMU_ENABLE BIT(0) +#define PPMU_DISABLE 0x0 +#define PPMU_CYCLE_RESET BIT(1) +#define PPMU_COUNTER_RESET BIT(2) + +#define PPMU_ENABLE_COUNT0 BIT(0) +#define PPMU_ENABLE_COUNT1 BIT(1) +#define PPMU_ENABLE_COUNT2 BIT(2) +#define PPMU_ENABLE_COUNT3 BIT(3) +#define PPMU_ENABLE_CYCLE BIT(31) + +#define PPMU_CNTENS 0x10 +#define PPMU_FLAG 0x50 +#define PPMU_CCNT_OVERFLOW BIT(31) +#define PPMU_CCNT 0x100 + +#define PPMU_PMCNT0 0x110 +#define PPMU_PMCNT_OFFSET 0x10 +#define PMCNT_OFFSET(x) (PPMU_PMCNT0 + (PPMU_PMCNT_OFFSET * x)) + +#define PPMU_BEVT0SEL 0x1000 +#define PPMU_BEVTSEL_OFFSET 0x100 +#define PPMU_BEVTSEL(x) (PPMU_BEVT0SEL + (ch * PPMU_BEVTSEL_OFFSET)) + +/* For Event Selection */ +#define RD_DATA_COUNT 0x5 +#define WR_DATA_COUNT 0x6 +#define RDWR_DATA_COUNT 0x7 + +enum ppmu_counter { + PPMU_PMNCNT0, + PPMU_PMCCNT1, + PPMU_PMNCNT2, + PPMU_PMNCNT3, + PPMU_PMNCNT_MAX, +}; + +struct bus_opp_table { + unsigned int idx; + unsigned long clk; + unsigned long volt; +}; + +struct exynos_ppmu { + void __iomem *hw_base; + unsigned int ccnt; + unsigned int event[PPMU_PMNCNT_MAX]; + unsigned int count[PPMU_PMNCNT_MAX]; + unsigned long long ns; + ktime_t reset_time; + bool ccnt_overflow; + bool count_overflow[PPMU_PMNCNT_MAX]; +}; + +void exynos_ppmu_reset(void __iomem *ppmu_base); +void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch, + unsigned int evt); +void exynos_ppmu_start(void __iomem *ppmu_base); +void exynos_ppmu_stop(void __iomem *ppmu_base); +unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch); +#endif /* __DEVFREQ_EXYNOS_PPMU_H */ + -- 1.7.8.6 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 4/4] PM/Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 2013-01-09 12:06 ` [PATCH 4/4] PM/Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 Abhilash Kesavan @ 2013-01-09 14:14 ` Rajagopal Venkat 2013-01-18 13:22 ` Abhilash Kesavan 2013-01-18 13:24 ` [PATCH v4 4/4] PM: Devfreq: " Abhilash Kesavan 1 sibling, 1 reply; 18+ messages in thread From: Rajagopal Venkat @ 2013-01-09 14:14 UTC (permalink / raw) To: Abhilash Kesavan Cc: myungjoo.ham, linux-kernel, linux-pm, kgene.kim, kyungmin.park, rjw, jhbird.choi On 9 January 2013 17:36, Abhilash Kesavan <a.kesavan@samsung.com> wrote: > Exynos5-bus device devfreq driver monitors PPMU counters and > adjusts operating frequencies and voltages with OPP. ASV should > be used to provide appropriate voltages as per the speed group > of the SoC rather than using a constant 1.025V. > > Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> > Cc: Jonghwan Choi <jhbird.choi@samsung.com> > Cc: Kukjin Kim <kgene.kim@samsung.com> > --- > drivers/devfreq/Kconfig | 10 + > drivers/devfreq/Makefile | 1 + > drivers/devfreq/exynos/Makefile | 1 + > drivers/devfreq/exynos/exynos5_bus.c | 469 +++++++++++++++++++++++++++++++++ > drivers/devfreq/exynos/exynos5_ppmu.c | 412 +++++++++++++++++++++++++++++ > drivers/devfreq/exynos/exynos_ppmu.c | 56 ++++ > include/linux/exynos5_ppmu.h | 26 ++ > include/linux/exynos_ppmu.h | 79 ++++++ > 8 files changed, 1054 insertions(+), 0 deletions(-) > create mode 100644 drivers/devfreq/exynos/exynos5_bus.c > create mode 100644 drivers/devfreq/exynos/exynos5_ppmu.c > create mode 100644 drivers/devfreq/exynos/exynos_ppmu.c > create mode 100644 include/linux/exynos5_ppmu.h > create mode 100644 include/linux/exynos_ppmu.h > > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig > index 0f079be..1560d0d 100644 > --- a/drivers/devfreq/Kconfig > +++ b/drivers/devfreq/Kconfig > @@ -78,4 +78,14 @@ config ARM_EXYNOS4_BUS_DEVFREQ > To operate with optimal voltages, ASV support is required > (CONFIG_EXYNOS_ASV). > > +config ARM_EXYNOS5_BUS_DEVFREQ > + bool "ARM Exynos5250 Bus DEVFREQ Driver" > + depends on SOC_EXYNOS5250 > + select ARCH_HAS_OPP > + select DEVFREQ_GOV_SIMPLE_ONDEMAND > + help > + This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int). > + It reads PPMU counters of memory controllers and adjusts the > + operating frequencies and voltages with OPP support. > + > endif # PM_DEVFREQ > diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile > index 3bc1fef..16138c9 100644 > --- a/drivers/devfreq/Makefile > +++ b/drivers/devfreq/Makefile > @@ -6,3 +6,4 @@ obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o > > # DEVFREQ Drivers > obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/ > +obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/ > diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile > index 1498823..69713a8 100644 > --- a/drivers/devfreq/exynos/Makefile > +++ b/drivers/devfreq/exynos/Makefile > @@ -1,2 +1,3 @@ > # Exynos DEVFREQ Drivers > obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o > +obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_ppmu.o exynos5_bus.o > diff --git a/drivers/devfreq/exynos/exynos5_bus.c b/drivers/devfreq/exynos/exynos5_bus.c > new file mode 100644 > index 0000000..1d4a4b1 > --- /dev/null > +++ b/drivers/devfreq/exynos/exynos5_bus.c > @@ -0,0 +1,469 @@ > +/* > + * Copyright (c) 2012 Samsung Electronics Co., Ltd. > + * http://www.samsung.com/ > + * > + * EXYNOS5 INT clock frequency scaling support using DEVFREQ framework > + * Based on work done by Jonghwan Choi <jhbird.choi@samsung.com> > + * Support for only EXYNOS5250 is present. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#include <linux/module.h> > +#include <linux/slab.h> > +#include <linux/suspend.h> > +#include <linux/opp.h> > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/platform_device.h> > +#include <linux/pm_qos.h> > +#include <linux/regulator/consumer.h> > +#include <linux/exynos_ppmu.h> > +#include <linux/exynos5_ppmu.h> > + > +#include "../governor.h" This header file is meant for governors use. What's the need of it here? > + > +#define MAX_SAFEVOLT 1100000 /* 1.10V */ > +/* Assume that the bus is saturated if the utilization is 25% */ > +#define INT_BUS_SATURATION_RATIO 25 > +#define EXYNOS5_BUS_INT_POLL_TIME msecs_to_jiffies(100) > + > +enum int_level_idx { > + LV_0, > + LV_1, > + LV_2, > + LV_3, > + LV_4, > + _LV_END > +}; > + > +struct busfreq_data_int { > + struct device *dev; > + struct devfreq *devfreq; > + bool disabled; > + struct regulator *vdd_int; > + unsigned long curr_freq; > + struct notifier_block pm_notifier; > + struct mutex lock; > + struct pm_qos_request int_req; > + struct clk *int_clk; > + struct exynos5_ppmu_handle *ppmu; > + struct delayed_work work; > + int busy; > +}; > + > +struct int_bus_opp_table { > + unsigned int idx; > + unsigned long clk; > + unsigned long volt; > +}; > + > +static struct int_bus_opp_table exynos5_int_opp_table[] = { > + {LV_0, 266000, 1025000}, > + {LV_1, 200000, 1025000}, > + {LV_2, 160000, 1025000}, > + {LV_3, 133000, 1025000}, > + {LV_4, 100000, 1025000}, > + {0, 0, 0}, > +}; > + > +static int exynos5_int_setvolt(struct busfreq_data_int *data, > + unsigned long volt) > +{ > + return regulator_set_voltage(data->vdd_int, volt, MAX_SAFEVOLT); > +} > + > +static int exynos5_busfreq_int_target(struct device *dev, unsigned long *_freq, > + u32 flags) > +{ > + int err = 0; > + struct platform_device *pdev = container_of(dev, struct platform_device, > + dev); > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + struct opp *opp; > + unsigned long old_freq, freq; > + unsigned long volt; > + > + rcu_read_lock(); > + opp = devfreq_recommended_opp(dev, _freq, flags); > + if (IS_ERR(opp)) { > + rcu_read_unlock(); > + dev_err(dev, "%s: Invalid OPP.\n", __func__); > + return PTR_ERR(opp); > + } > + > + freq = opp_get_freq(opp); > + volt = opp_get_voltage(opp); > + rcu_read_unlock(); > + > + old_freq = data->curr_freq; > + > + if (old_freq == freq) > + return 0; > + > + dev_dbg(dev, "targetting %lukHz %luuV\n", freq, volt); > + > + mutex_lock(&data->lock); > + > + if (data->disabled) > + goto out; > + > + if (freq > exynos5_int_opp_table[_LV_END - 1].clk) > + pm_qos_update_request(&data->int_req, > + data->busy * old_freq * 16 / 100000); > + else > + pm_qos_update_request(&data->int_req, -1); > + > + if (old_freq < freq) > + err = exynos5_int_setvolt(data, volt); > + if (err) > + goto out; > + > + err = clk_set_rate(data->int_clk, freq * 1000); > + > + if (err) > + goto out; > + > + if (old_freq > freq) > + err = exynos5_int_setvolt(data, volt); > + if (err) > + goto out; > + > + data->curr_freq = freq; > +out: > + mutex_unlock(&data->lock); > + return err; > +} > + > +static int exynos5_int_get_dev_status(struct device *dev, > + struct devfreq_dev_status *stat) > +{ > + struct platform_device *pdev = container_of(dev, struct platform_device, > + dev); > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + > + stat->current_frequency = data->curr_freq; > + stat->busy_time = data->busy; > + stat->total_time = 100; How is busy_time is relative to total_time here? busy_time <= total_time is guaranteed? > + > + return 0; > +} > + > +static void exynos5_int_poll_start(struct busfreq_data_int *data) > +{ > + schedule_delayed_work(&data->work, EXYNOS5_BUS_INT_POLL_TIME); > +} > + > +static void exynos5_int_poll_stop(struct busfreq_data_int *data) > +{ > + cancel_delayed_work_sync(&data->work); > +} > + > +static void exynos5_int_poll(struct work_struct *work) > +{ > + struct delayed_work *dwork; > + struct busfreq_data_int *data; > + int ret; > + > + dwork = to_delayed_work(work); > + data = container_of(dwork, struct busfreq_data_int, work); > + > + ret = exynos5_ppmu_get_busy(data->ppmu, PPMU_SET_RIGHT); > + > + if (ret >= 0) { > + data->busy = ret; > + mutex_lock(&data->devfreq->lock); > + update_devfreq(data->devfreq); Again, update_devfreq() is meant for devfreq governors use. Why is the devfreq driver is doing devfreq governor job? any specific reason? The devfreq device load monitoring is done by governors. > + mutex_unlock(&data->devfreq->lock); > + } > + > + schedule_delayed_work(&data->work, EXYNOS5_BUS_INT_POLL_TIME); > +} > + > +static void exynos5_int_exit(struct device *dev) > +{ > + struct platform_device *pdev = container_of(dev, struct platform_device, > + dev); > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + > + devfreq_unregister_opp_notifier(dev, data->devfreq); > +} > + > +static struct devfreq_dev_profile exynos5_devfreq_int_profile = { > + .initial_freq = 160000, > + .polling_ms = 0, why is polling_ms is set to zero? It defeats the purpose of devfreq driver. > + .target = exynos5_busfreq_int_target, > + .get_dev_status = exynos5_int_get_dev_status, > + .exit = exynos5_int_exit, > +}; > + > +static int exynos5250_init_int_tables(struct busfreq_data_int *data) > +{ > + int i, err = 0; > + > + for (i = LV_0; i < _LV_END; i++) { > + err = opp_add(data->dev, exynos5_int_opp_table[i].clk, > + exynos5_int_opp_table[i].volt); > + if (err) { > + dev_err(data->dev, "Cannot add opp entries.\n"); > + return err; > + } > + } > + > + return 0; > +} > +static struct devfreq_simple_ondemand_data exynos5_int_ondemand_data = { > + .downdifferential = 2, > + .upthreshold = INT_BUS_SATURATION_RATIO, > +}; > + > +static int exynos5_busfreq_int_pm_notifier_event(struct notifier_block *this, > + unsigned long event, void *ptr) > +{ > + struct busfreq_data_int *data = container_of(this, > + struct busfreq_data_int, pm_notifier); > + struct opp *opp; > + unsigned long maxfreq = ULONG_MAX; > + unsigned long freq; > + unsigned long volt; > + int err = 0; > + > + switch (event) { > + case PM_SUSPEND_PREPARE: > + /* Set Fastest and Deactivate DVFS */ > + mutex_lock(&data->lock); > + > + data->disabled = true; > + > + rcu_read_lock(); > + opp = opp_find_freq_floor(data->dev, &maxfreq); > + if (IS_ERR(opp)) { > + rcu_read_unlock(); > + err = PTR_ERR(opp); > + goto unlock; > + } > + freq = opp_get_freq(opp); > + volt = opp_get_voltage(opp); > + rcu_read_unlock(); > + > + err = exynos5_int_setvolt(data, volt); > + if (err) > + goto unlock; > + > + err = clk_set_rate(data->int_clk, freq * 1000); > + > + if (err) > + goto unlock; > + > + data->curr_freq = freq; > +unlock: > + mutex_unlock(&data->lock); > + if (err) > + return NOTIFY_BAD; > + return NOTIFY_OK; > + case PM_POST_RESTORE: > + case PM_POST_SUSPEND: > + /* Reactivate */ > + mutex_lock(&data->lock); > + data->disabled = false; > + mutex_unlock(&data->lock); > + return NOTIFY_OK; > + } > + > + return NOTIFY_DONE; > +} > + > +static __devinit int exynos5_busfreq_int_probe(struct platform_device *pdev) > +{ > + struct busfreq_data_int *data; > + struct opp *opp; > + struct device *dev = &pdev->dev; > + unsigned long initial_freq; > + unsigned long initial_volt; > + int err = 0; > + > + data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data_int), > + GFP_KERNEL); > + if (data == NULL) { > + dev_err(dev, "Cannot allocate memory.\n"); > + return -ENOMEM; > + } > + > + data->pm_notifier.notifier_call = exynos5_busfreq_int_pm_notifier_event; > + data->dev = dev; > + mutex_init(&data->lock); > + > + err = exynos5250_init_int_tables(data); > + if (err) > + goto err_regulator; > + > + data->vdd_int = regulator_get(dev, "vdd_int"); > + if (IS_ERR(data->vdd_int)) { > + dev_err(dev, "Cannot get the regulator \"vdd_int\"\n"); > + err = PTR_ERR(data->vdd_int); > + goto err_regulator; > + } > + > + data->int_clk = clk_get(dev, "int_clk"); > + if (IS_ERR(data->int_clk)) { > + dev_err(dev, "Cannot get clock \"int_clk\"\n"); > + err = PTR_ERR(data->int_clk); > + goto err_clock; > + } > + > + rcu_read_lock(); > + opp = opp_find_freq_floor(dev, > + &exynos5_devfreq_int_profile.initial_freq); > + if (IS_ERR(opp)) { > + rcu_read_unlock(); > + dev_err(dev, "Invalid initial frequency %lu kHz.\n", > + exynos5_devfreq_int_profile.initial_freq); > + err = PTR_ERR(opp); > + goto err_opp_add; > + } > + initial_freq = opp_get_freq(opp); > + initial_volt = opp_get_voltage(opp); > + rcu_read_unlock(); > + data->curr_freq = initial_freq; > + > + err = clk_set_rate(data->int_clk, initial_freq * 1000); > + if (err) { > + dev_err(dev, "Failed to set initial frequency\n"); > + goto err_opp_add; > + } > + > + err = exynos5_int_setvolt(data, initial_volt); > + if (err) > + goto err_opp_add; > + > + platform_set_drvdata(pdev, data); > + > + data->ppmu = exynos5_ppmu_get(); > + if (!data->ppmu) > + goto err_ppmu_get; > + > + INIT_DELAYED_WORK(&data->work, exynos5_int_poll); > + exynos5_int_poll_start(data); > + > + data->devfreq = devfreq_add_device(dev, &exynos5_devfreq_int_profile, > + "simple_ondemand", > + &exynos5_int_ondemand_data); > + > + if (IS_ERR(data->devfreq)) { > + err = PTR_ERR(data->devfreq); > + goto err_devfreq_add; > + } > + > + devfreq_register_opp_notifier(dev, data->devfreq); > + > + err = register_pm_notifier(&data->pm_notifier); > + if (err) { > + dev_err(dev, "Failed to setup pm notifier\n"); > + goto err_devfreq_add; > + } > + > + /* TODO: Add a new QOS class for int/mif bus */ > + pm_qos_add_request(&data->int_req, PM_QOS_NETWORK_THROUGHPUT, -1); > + > + return 0; > + > +err_devfreq_add: > + devfreq_remove_device(data->devfreq); > + exynos5_int_poll_stop(data); > +err_ppmu_get: > + platform_set_drvdata(pdev, NULL); > +err_opp_add: > + clk_put(data->int_clk); > +err_clock: > + regulator_put(data->vdd_int); > +err_regulator: > + return err; > +} > + > +static __devexit int exynos5_busfreq_int_remove(struct platform_device *pdev) > +{ > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + > + pm_qos_remove_request(&data->int_req); > + unregister_pm_notifier(&data->pm_notifier); > + devfreq_remove_device(data->devfreq); > + regulator_put(data->vdd_int); > + clk_put(data->int_clk); > + platform_set_drvdata(pdev, NULL); > + > + return 0; > +} > + > +#ifdef CONFIG_PM_SLEEP > +static int exynos5_busfreq_int_suspend(struct device *dev) > +{ > + struct platform_device *pdev = container_of(dev, struct platform_device, > + dev); > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + > + exynos5_int_poll_stop(data); > + return 0; > +} > + > +static int exynos5_busfreq_int_resume(struct device *dev) > +{ > + struct platform_device *pdev = container_of(dev, struct platform_device, > + dev); > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + > + exynos5_int_poll_start(data); > + return 0; > +} > +#endif > + > +static SIMPLE_DEV_PM_OPS(exynos5_busfreq_int_pm, exynos5_busfreq_int_suspend, > + exynos5_busfreq_int_resume); > + > +/* platform device pointer for exynos5 devfreq device. */ > +static struct platform_device *exynos5_devfreq_pdev; > + > +static struct platform_driver exynos5_busfreq_int_driver = { > + .probe = exynos5_busfreq_int_probe, > + .remove = __devexit_p(exynos5_busfreq_int_remove), > + .driver = { > + .name = "exynos5-bus-int", > + .owner = THIS_MODULE, > + .pm = &exynos5_busfreq_int_pm, > + }, > +}; > + > +static int __init exynos5_busfreq_int_init(void) > +{ > + int ret; > + > + ret = platform_driver_register(&exynos5_busfreq_int_driver); > + if (ret < 0) > + goto out; > + > + exynos5_devfreq_pdev = > + platform_device_register_simple("exynos5-bus-int", -1, NULL, 0); > + if (IS_ERR_OR_NULL(exynos5_devfreq_pdev)) { > + ret = PTR_ERR(exynos5_devfreq_pdev); > + goto out1; > + } > + > + return 0; > +out1: > + platform_driver_unregister(&exynos5_busfreq_int_driver); > +out: > + return ret; > +} > +late_initcall(exynos5_busfreq_int_init); > + > +static void __exit exynos5_busfreq_int_exit(void) > +{ > + platform_device_unregister(exynos5_devfreq_pdev); > + platform_driver_unregister(&exynos5_busfreq_int_driver); > +} > +module_exit(exynos5_busfreq_int_exit); > + > +MODULE_LICENSE("GPL"); > +MODULE_DESCRIPTION("EXYNOS5 busfreq driver with devfreq framework"); > diff --git a/drivers/devfreq/exynos/exynos5_ppmu.c b/drivers/devfreq/exynos/exynos5_ppmu.c > new file mode 100644 > index 0000000..0620f24 > --- /dev/null > +++ b/drivers/devfreq/exynos/exynos5_ppmu.c > @@ -0,0 +1,412 @@ > +/* > + * Copyright (c) 2012 Samsung Electronics Co., Ltd. > + * http://www.samsung.com/ > + * > + * EXYNOS5 PPMU support > + * Support for only EXYNOS5250 is present. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/kernel.h> > +#include <linux/debugfs.h> > +#include <linux/delay.h> > +#include <linux/hrtimer.h> > +#include <linux/io.h> > +#include <linux/of.h> > +#include <linux/slab.h> > +#include <linux/exynos_ppmu.h> > +#include <linux/exynos5_ppmu.h> > + > +#include <mach/map.h> > + > +#define FIXED_POINT_OFFSET (0x8) > +#define FIXED_POINT_MASK (0xff) > + > +enum exynos5_ppmu_list { > + PPMU_DDR_C, > + PPMU_DDR_R1, > + PPMU_DDR_L, > + PPMU_RIGHT, > + PPMU_CPU, > + PPMU_END, > +}; > + > +struct exynos5_ppmu_handle { > + struct list_head node; > + struct exynos_ppmu ppmu[PPMU_END]; > +}; > + > +static DEFINE_SPINLOCK(exynos5_ppmu_lock); > +static LIST_HEAD(exynos5_ppmu_handle_list); > +static struct exynos_ppmu ppmu[PPMU_END]; > + > +static const char *exynos5_ppmu_name[PPMU_END] = { > + [PPMU_DDR_C] = "DDR_C", > + [PPMU_DDR_R1] = "DDR_R1", > + [PPMU_DDR_L] = "DDR_L", > + [PPMU_RIGHT] = "RIGHT", > + [PPMU_CPU] = "CPU", > +}; > + > +static void exynos5_ppmu_reset(struct exynos_ppmu *ppmu) > +{ > + unsigned long flags; > + void __iomem *ppmu_base = ppmu->hw_base; > + > + /* Reset the performance and cycle counters */ > + exynos_ppmu_reset(ppmu_base); > + > + /* Setup count registers for monitoring read/write transactions */ > + ppmu->event[PPMU_PMNCNT0] = RD_DATA_COUNT; > + exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT0, > + ppmu->event[PPMU_PMNCNT0]); > + ppmu->event[PPMU_PMCCNT1] = WR_DATA_COUNT; > + exynos_ppmu_setevent(ppmu_base, PPMU_PMCCNT1, > + ppmu->event[PPMU_PMCCNT1]); > + ppmu->event[PPMU_PMNCNT3] = RDWR_DATA_COUNT; > + exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3, > + ppmu->event[PPMU_PMNCNT3]); > + > + local_irq_save(flags); > + ppmu->reset_time = ktime_get(); > + exynos_ppmu_start(ppmu_base); > + local_irq_restore(flags); > +} > + > +static void exynos5_ppmu_read(struct exynos_ppmu *ppmu) > +{ > + unsigned long flags; > + ktime_t read_time; > + ktime_t t; > + int reg, j; > + void __iomem *ppmu_base = ppmu->hw_base; > + > + local_irq_save(flags); > + read_time = ktime_get(); > + exynos_ppmu_stop(ppmu_base); > + local_irq_restore(flags); > + > + /* Update local data from PPMU */ > + ppmu->ccnt = __raw_readl(ppmu_base + PPMU_CCNT); > + reg = __raw_readl(ppmu_base + PPMU_FLAG); > + ppmu->ccnt_overflow = reg & PPMU_CCNT_OVERFLOW; > + > + for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) { > + if (ppmu->event[j] == 0) > + ppmu->count[j] = 0; > + else > + ppmu->count[j] = exynos_ppmu_read(ppmu_base, j); > + } > + t = ktime_sub(read_time, ppmu->reset_time); > + ppmu->ns = ktime_to_ns(t); > +} > + > +static void exynos5_ppmu_add(struct exynos_ppmu *to, struct exynos_ppmu *from) > +{ > + int i, j; > + > + for (i = 0; i < PPMU_END; i++) { > + for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) > + to[i].count[j] += from[i].count[j]; > + > + to[i].ccnt += from[i].ccnt; > + if (to[i].ccnt < from[i].ccnt) > + to[i].ccnt_overflow = true; > + > + to[i].ns += from[i].ns; > + > + if (from[i].ccnt_overflow) > + to[i].ccnt_overflow = true; > + } > +} > + > +static void exynos5_ppmu_handle_clear(struct exynos5_ppmu_handle *handle) > +{ > + memset(&handle->ppmu, 0, sizeof(struct exynos_ppmu) * PPMU_END); > +} > + > +static void exynos5_ppmu_update(void) > +{ > + int i; > + struct exynos5_ppmu_handle *handle; > + > + for (i = 0; i < PPMU_END; i++) { > + exynos5_ppmu_read(&ppmu[i]); > + exynos5_ppmu_reset(&ppmu[i]); > + } > + > + list_for_each_entry(handle, &exynos5_ppmu_handle_list, node) > + exynos5_ppmu_add(handle->ppmu, ppmu); > +} > + > +static int exynos5_ppmu_get_filter(enum exynos5_ppmu_sets filter, > + enum exynos5_ppmu_list *start, enum exynos5_ppmu_list *end) > +{ > + switch (filter) { > + case PPMU_SET_DDR: > + *start = PPMU_DDR_C; > + *end = PPMU_DDR_L; > + break; > + case PPMU_SET_RIGHT: > + *start = PPMU_RIGHT; > + *end = PPMU_RIGHT; > + break; > + case PPMU_SET_CPU: > + *start = PPMU_CPU; > + *end = PPMU_CPU; > + break; > + default: > + return -EINVAL; > + } > + > + return 0; > +} > + > +int exynos5_ppmu_get_busy(struct exynos5_ppmu_handle *handle, > + enum exynos5_ppmu_sets filter) > +{ > + unsigned long flags; > + int i, temp, ret, busy = 0; > + enum exynos5_ppmu_list start; > + enum exynos5_ppmu_list end; > + > + ret = exynos5_ppmu_get_filter(filter, &start, &end); > + if (ret < 0) > + return ret; > + > + spin_lock_irqsave(&exynos5_ppmu_lock, flags); > + > + exynos5_ppmu_update(); > + > + for (i = start; i <= end; i++) { > + if (handle->ppmu[i].ccnt_overflow) { > + busy = -EOVERFLOW; > + break; > + } > + temp = handle->ppmu[i].count[PPMU_PMNCNT3] * 100; > + if (handle->ppmu[i].ccnt > 0) > + temp /= handle->ppmu[i].ccnt; > + if (temp > busy) > + busy = temp; > + } > + > + exynos5_ppmu_handle_clear(handle); > + > + spin_unlock_irqrestore(&exynos5_ppmu_lock, flags); > + > + return busy; > +} > + > +static void exynos5_ppmu_put(struct exynos5_ppmu_handle *handle) > +{ > + unsigned long flags; > + > + spin_lock_irqsave(&exynos5_ppmu_lock, flags); > + > + list_del(&handle->node); > + > + spin_unlock_irqrestore(&exynos5_ppmu_lock, flags); > + > + kfree(handle); > +} > + > +struct exynos5_ppmu_handle *exynos5_ppmu_get(void) > +{ > + struct exynos5_ppmu_handle *handle; > + unsigned long flags; > + > + handle = kzalloc(sizeof(struct exynos5_ppmu_handle), GFP_KERNEL); > + if (!handle) > + return NULL; > + > + spin_lock_irqsave(&exynos5_ppmu_lock, flags); > + > + exynos5_ppmu_update(); > + list_add_tail(&handle->node, &exynos5_ppmu_handle_list); > + > + spin_unlock_irqrestore(&exynos5_ppmu_lock, flags); > + > + return handle; > +} > + > +static void exynos5_ppmu_debug_compute(struct exynos_ppmu *ppmu, > + enum ppmu_counter i, u32 *sat, u32 *freq, u32 *bw) > +{ > + u64 ns = ppmu->ns; > + u32 busy = ppmu->count[i]; > + u32 total = ppmu->ccnt; > + > + u64 s; > + u64 f; > + u64 b; > + > + s = (u64)busy * 100 * (1 << FIXED_POINT_OFFSET); > + s += total / 2; > + do_div(s, total); > + > + f = (u64)total * 1000 * (1 << FIXED_POINT_OFFSET); > + f += ns / 2; > + f = div64_u64(f, ns); > + > + b = (u64)busy * (128 / 8) * 1000 * (1 << FIXED_POINT_OFFSET); > + b += ns / 2; > + b = div64_u64(b, ns); > + > + *sat = s; > + *freq = f; > + *bw = b; > +} > + > +static void exynos5_ppmu_debug_show_one_counter(struct seq_file *s, > + const char *name, const char *type, struct exynos_ppmu *ppmu, > + enum ppmu_counter i, u32 *bw_total) > +{ > + u32 sat; > + u32 freq; > + u32 bw; > + > + exynos5_ppmu_debug_compute(ppmu, i, &sat, &freq, &bw); > + > + seq_printf(s, "%-10s %-10s %4u.%02u MBps %3u.%02u MHz %2u.%02u%%\n", > + name, type, > + bw >> FIXED_POINT_OFFSET, > + (bw & FIXED_POINT_MASK) * 100 / (1 << FIXED_POINT_OFFSET), > + freq >> FIXED_POINT_OFFSET, > + (freq & FIXED_POINT_MASK) * 100 / (1 << FIXED_POINT_OFFSET), > + sat >> FIXED_POINT_OFFSET, > + (sat & FIXED_POINT_MASK) * 100 / (1 << FIXED_POINT_OFFSET)); > + > + *bw_total += bw; > +} > + > +static void exynos5_ppmu_debug_show_one(struct seq_file *s, > + const char *name, struct exynos_ppmu *ppmu, > + u32 *bw_total) > +{ > + exynos5_ppmu_debug_show_one_counter(s, name, "read+write", > + ppmu, PPMU_PMNCNT3, &bw_total[PPMU_PMNCNT3]); > + exynos5_ppmu_debug_show_one_counter(s, "", "read", > + ppmu, PPMU_PMNCNT0, &bw_total[PPMU_PMNCNT0]); > + exynos5_ppmu_debug_show_one_counter(s, "", "write", > + ppmu, PPMU_PMCCNT1, &bw_total[PPMU_PMCCNT1]); > + > +} > + > +static int exynos5_ppmu_debug_show(struct seq_file *s, void *d) > +{ > + int i; > + u32 bw_total[PPMU_PMNCNT_MAX]; > + struct exynos5_ppmu_handle *handle; > + unsigned long flags; > + > + memset(bw_total, 0, sizeof(bw_total)); > + > + handle = exynos5_ppmu_get(); > + msleep(100); > + > + spin_lock_irqsave(&exynos5_ppmu_lock, flags); > + > + exynos5_ppmu_update(); > + > + for (i = 0; i < PPMU_CPU; i++) > + exynos5_ppmu_debug_show_one(s, exynos5_ppmu_name[i], > + &handle->ppmu[i], bw_total); > + > + seq_printf(s, "%-10s %-10s %4u.%02u MBps\n", "total", "read+write", > + bw_total[PPMU_PMNCNT3] >> FIXED_POINT_OFFSET, > + (bw_total[PPMU_PMNCNT3] & FIXED_POINT_MASK) * > + 100 / (1 << FIXED_POINT_OFFSET)); > + seq_printf(s, "%-10s %-10s %4u.%02u MBps\n", "", "read", > + bw_total[PPMU_PMNCNT0] >> FIXED_POINT_OFFSET, > + (bw_total[PPMU_PMNCNT0] & FIXED_POINT_MASK) * > + 100 / (1 << FIXED_POINT_OFFSET)); > + seq_printf(s, "%-10s %-10s %4u.%02u MBps\n", "", "write", > + bw_total[PPMU_PMCCNT1] >> FIXED_POINT_OFFSET, > + (bw_total[PPMU_PMCCNT1] & FIXED_POINT_MASK) * > + 100 / (1 << FIXED_POINT_OFFSET)); > + > + seq_printf(s, "\n"); > + > + exynos5_ppmu_debug_show_one(s, exynos5_ppmu_name[PPMU_CPU], > + &ppmu[PPMU_CPU], bw_total); > + > + spin_unlock_irqrestore(&exynos5_ppmu_lock, flags); > + > + exynos5_ppmu_put(handle); > + > + return 0; > +} > + > +static int exynos5_ppmu_debug_open(struct inode *inode, struct file *file) > +{ > + return single_open(file, exynos5_ppmu_debug_show, inode->i_private); > +} > + > +static const struct file_operations exynos5_ppmu_debug_fops = { > + .open = exynos5_ppmu_debug_open, > + .read = seq_read, > + .llseek = seq_lseek, > + .release = single_release, > +}; > + > +static int __init exynos5_ppmu_debug_init(void) > +{ > + debugfs_create_file("exynos5_bus", S_IRUGO, NULL, NULL, > + &exynos5_ppmu_debug_fops); > + return 0; > +} > +late_initcall(exynos5_ppmu_debug_init); > + > +static int exynos5_ppmu_probe(struct platform_device *pdev) > +{ > + struct resource *res; > + int i; > + > + for (i = 0; i < PPMU_END; i++) { > + /* get the memory region */ > + res = platform_get_resource(pdev, IORESOURCE_MEM, i); > + if (res == NULL) { > + dev_err(&pdev->dev, "failed to get memory region resource\n"); > + return -ENOENT; > + } > + > + ppmu[i].hw_base = devm_request_and_ioremap(&pdev->dev, res); > + if (ppmu->hw_base == NULL) { > + dev_err(&pdev->dev, "failed to ioremap memory region\n"); > + return -EINVAL; > + } > + } > + > + return 0; > +} > + > +static int __devexit exynos5_ppmu_remove(struct platform_device *pdev) > +{ > + dev_dbg(&pdev->dev, "%s driver unloaded\n", pdev->name); > + > + return 0; > +} > + > +static const struct of_device_id exynos5_ppmu_match[] = { > + { > + .compatible = "samsung,exynos5250-ppmu", > + }, > + {}, > +}; > + > +static struct platform_driver exynos5_ppmu_driver = { > + .probe = exynos5_ppmu_probe, > + .remove = __devexit_p(exynos5_ppmu_remove), > + .driver = { > + .name = "exynos5-ppmu", > + .owner = THIS_MODULE, > + .of_match_table = of_match_ptr(exynos5_ppmu_match), > + }, > +}; > +module_platform_driver(exynos5_ppmu_driver); > diff --git a/drivers/devfreq/exynos/exynos_ppmu.c b/drivers/devfreq/exynos/exynos_ppmu.c > new file mode 100644 > index 0000000..da373be > --- /dev/null > +++ b/drivers/devfreq/exynos/exynos_ppmu.c > @@ -0,0 +1,56 @@ > +/* > + * Copyright (c) 2012 Samsung Electronics Co., Ltd. > + * http://www.samsung.com/ > + * > + * EXYNOS - PPMU support > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/kernel.h> > +#include <linux/types.h> > +#include <linux/io.h> > + > +#include <linux/exynos_ppmu.h> > + > +void exynos_ppmu_reset(void __iomem *ppmu_base) > +{ > + __raw_writel(PPMU_CYCLE_RESET | PPMU_COUNTER_RESET, ppmu_base); > + __raw_writel(PPMU_ENABLE_CYCLE | > + PPMU_ENABLE_COUNT0 | > + PPMU_ENABLE_COUNT1 | > + PPMU_ENABLE_COUNT2 | > + PPMU_ENABLE_COUNT3, > + ppmu_base + PPMU_CNTENS); > +} > + > +void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch, > + unsigned int evt) > +{ > + __raw_writel(evt, ppmu_base + PPMU_BEVTSEL(ch)); > +} > + > +void exynos_ppmu_start(void __iomem *ppmu_base) > +{ > + __raw_writel(PPMU_ENABLE, ppmu_base); > +} > + > +void exynos_ppmu_stop(void __iomem *ppmu_base) > +{ > + __raw_writel(PPMU_DISABLE, ppmu_base); > +} > + > +unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch) > +{ > + unsigned int total; > + > + if (ch == PPMU_PMNCNT3) > + total = ((__raw_readl(ppmu_base + PMCNT_OFFSET(ch)) << 8) | > + __raw_readl(ppmu_base + PMCNT_OFFSET(ch + 1))); > + else > + total = __raw_readl(ppmu_base + PMCNT_OFFSET(ch)); > + > + return total; > +} > diff --git a/include/linux/exynos5_ppmu.h b/include/linux/exynos5_ppmu.h > new file mode 100644 > index 0000000..9f492c1 > --- /dev/null > +++ b/include/linux/exynos5_ppmu.h > @@ -0,0 +1,26 @@ > +/* > + * Copyright (c) 2012 Samsung Electronics Co., Ltd. > + * http://www.samsung.com/ > + * > + * EXYNOS5 PPMU header > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > +*/ > + > +#ifndef __DEVFREQ_EXYNOS5_PPMU_H > +#define __DEVFREQ_EXYNOS5_PPMU_H __FILE__ > + > +enum exynos5_ppmu_sets { > + PPMU_SET_DDR, > + PPMU_SET_RIGHT, > + PPMU_SET_CPU, > +}; > + > +struct exynos5_ppmu_handle *exynos5_ppmu_get(void); > +extern int exynos5_ppmu_get_busy(struct exynos5_ppmu_handle *handle, > + enum exynos5_ppmu_sets filter); > + > +#endif /* __DEVFREQ_EXYNOS5_PPMU_H */ > + > diff --git a/include/linux/exynos_ppmu.h b/include/linux/exynos_ppmu.h > new file mode 100644 > index 0000000..b46d31b > --- /dev/null > +++ b/include/linux/exynos_ppmu.h > @@ -0,0 +1,79 @@ > +/* > + * Copyright (c) 2012 Samsung Electronics Co., Ltd. > + * http://www.samsung.com/ > + * > + * EXYNOS PPMU header > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > +*/ > + > +#ifndef __DEVFREQ_EXYNOS_PPMU_H > +#define __DEVFREQ_EXYNOS_PPMU_H __FILE__ > + > +#include <linux/ktime.h> > + > +/* For PPMU Control */ > +#define PPMU_ENABLE BIT(0) > +#define PPMU_DISABLE 0x0 > +#define PPMU_CYCLE_RESET BIT(1) > +#define PPMU_COUNTER_RESET BIT(2) > + > +#define PPMU_ENABLE_COUNT0 BIT(0) > +#define PPMU_ENABLE_COUNT1 BIT(1) > +#define PPMU_ENABLE_COUNT2 BIT(2) > +#define PPMU_ENABLE_COUNT3 BIT(3) > +#define PPMU_ENABLE_CYCLE BIT(31) > + > +#define PPMU_CNTENS 0x10 > +#define PPMU_FLAG 0x50 > +#define PPMU_CCNT_OVERFLOW BIT(31) > +#define PPMU_CCNT 0x100 > + > +#define PPMU_PMCNT0 0x110 > +#define PPMU_PMCNT_OFFSET 0x10 > +#define PMCNT_OFFSET(x) (PPMU_PMCNT0 + (PPMU_PMCNT_OFFSET * x)) > + > +#define PPMU_BEVT0SEL 0x1000 > +#define PPMU_BEVTSEL_OFFSET 0x100 > +#define PPMU_BEVTSEL(x) (PPMU_BEVT0SEL + (ch * PPMU_BEVTSEL_OFFSET)) > + > +/* For Event Selection */ > +#define RD_DATA_COUNT 0x5 > +#define WR_DATA_COUNT 0x6 > +#define RDWR_DATA_COUNT 0x7 > + > +enum ppmu_counter { > + PPMU_PMNCNT0, > + PPMU_PMCCNT1, > + PPMU_PMNCNT2, > + PPMU_PMNCNT3, > + PPMU_PMNCNT_MAX, > +}; > + > +struct bus_opp_table { > + unsigned int idx; > + unsigned long clk; > + unsigned long volt; > +}; > + > +struct exynos_ppmu { > + void __iomem *hw_base; > + unsigned int ccnt; > + unsigned int event[PPMU_PMNCNT_MAX]; > + unsigned int count[PPMU_PMNCNT_MAX]; > + unsigned long long ns; > + ktime_t reset_time; > + bool ccnt_overflow; > + bool count_overflow[PPMU_PMNCNT_MAX]; > +}; > + > +void exynos_ppmu_reset(void __iomem *ppmu_base); > +void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch, > + unsigned int evt); > +void exynos_ppmu_start(void __iomem *ppmu_base); > +void exynos_ppmu_stop(void __iomem *ppmu_base); > +unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch); > +#endif /* __DEVFREQ_EXYNOS_PPMU_H */ > + > -- > 1.7.8.6 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Regards, Rajagopal ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 4/4] PM/Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 2013-01-09 14:14 ` Rajagopal Venkat @ 2013-01-18 13:22 ` Abhilash Kesavan 0 siblings, 0 replies; 18+ messages in thread From: Abhilash Kesavan @ 2013-01-18 13:22 UTC (permalink / raw) To: Rajagopal Venkat Cc: myungjoo.ham, linux-kernel, linux-pm, kgene.kim, kyungmin.park, rjw, jhbird.choi Hi Rajagopal, Thanks for the review. Sorry for the late response, have been a little busy with other things, [...] >> +#include "../governor.h" > > This header file is meant for governors use. What's the need of it here? I was using a custom monitor function and needed update_devfreq for it. Will change this in the next version. [...] >> + stat->current_frequency = data->curr_freq; >> + stat->busy_time = data->busy; >> + stat->total_time = 100; > > How is busy_time is relative to total_time here? busy_time <= > total_time is guaranteed? Will modify the get_dev_status function to do PPMU reads and populate the device status structure. > [...] > Again, update_devfreq() is meant for devfreq governors use. Why is the devfreq > driver is doing devfreq governor job? any specific reason? The devfreq device > load monitoring is done by governors. > Same as above. [...] >> + .polling_ms = 0, > > why is polling_ms is set to zero? It defeats the purpose of devfreq driver. I bypassed the devfreq_monitor with the new custom function created. Am fixing this. I have now done this on the lines of the exynos4 driver. Will re-post in a bit. Regards, Abhilash ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 4/4] PM: Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 2013-01-09 12:06 ` [PATCH 4/4] PM/Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 Abhilash Kesavan 2013-01-09 14:14 ` Rajagopal Venkat @ 2013-01-18 13:24 ` Abhilash Kesavan 2013-02-03 15:47 ` Abhilash Kesavan 2013-02-04 12:14 ` [PATCH v5 " Abhilash Kesavan 1 sibling, 2 replies; 18+ messages in thread From: Abhilash Kesavan @ 2013-01-18 13:24 UTC (permalink / raw) To: myungjoo.ham, linux-kernel, linux-pm, kgene.kim Cc: kyungmin.park, rjw, jhbird.choi Exynos5-bus device devfreq driver monitors PPMU counters and adjusts operating frequencies and voltages with OPP. ASV should be used to provide appropriate voltages as per the speed group of the SoC rather than using a constant 1.025V. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Jonghwan Choi <jhbird.choi@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> --- Changes since RFC v1: * Moved the Exynos5 PPMU driver to machine specific directory * Migrated to the PM QOS framework Changes since v2: * Moved the PPMU driver to drivers/devfreq/exynos * Fixed whitespace, commenting, empty lines in PPMU driver Changes since v3: * Removed the custom devfreq monitor and PPMU polling function * Moved exynos5 PPMU access functions to the devfreq driver drivers/devfreq/Kconfig | 10 + drivers/devfreq/Makefile | 1 + drivers/devfreq/exynos/Makefile | 1 + drivers/devfreq/exynos/exynos5_bus.c | 502 ++++++++++++++++++++++++++++++++++ drivers/devfreq/exynos/exynos_ppmu.c | 55 ++++ include/linux/exynos_ppmu.h | 79 ++++++ 6 files changed, 648 insertions(+), 0 deletions(-) create mode 100644 drivers/devfreq/exynos/exynos5_bus.c create mode 100644 drivers/devfreq/exynos/exynos_ppmu.c create mode 100644 include/linux/exynos_ppmu.h diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 0f079be..1560d0d 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -78,4 +78,14 @@ config ARM_EXYNOS4_BUS_DEVFREQ To operate with optimal voltages, ASV support is required (CONFIG_EXYNOS_ASV). +config ARM_EXYNOS5_BUS_DEVFREQ + bool "ARM Exynos5250 Bus DEVFREQ Driver" + depends on SOC_EXYNOS5250 + select ARCH_HAS_OPP + select DEVFREQ_GOV_SIMPLE_ONDEMAND + help + This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int). + It reads PPMU counters of memory controllers and adjusts the + operating frequencies and voltages with OPP support. + endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 3bc1fef..16138c9 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o # DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/ +obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/ diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile index 1498823..bfaaf5b 100644 --- a/drivers/devfreq/exynos/Makefile +++ b/drivers/devfreq/exynos/Makefile @@ -1,2 +1,3 @@ # Exynos DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o +obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_bus.o diff --git a/drivers/devfreq/exynos/exynos5_bus.c b/drivers/devfreq/exynos/exynos5_bus.c new file mode 100644 index 0000000..fbdcbaf --- /dev/null +++ b/drivers/devfreq/exynos/exynos5_bus.c @@ -0,0 +1,502 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS5 INT clock frequency scaling support using DEVFREQ framework + * Based on work done by Jonghwan Choi <jhbird.choi@samsung.com> + * Support for only EXYNOS5250 is present. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/devfreq.h> +#include <linux/io.h> +#include <linux/opp.h> +#include <linux/slab.h> +#include <linux/suspend.h> +#include <linux/opp.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/pm_qos.h> +#include <linux/regulator/consumer.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> +#include <linux/exynos_ppmu.h> + +#define MAX_SAFEVOLT 1100000 /* 1.10V */ +/* Assume that the bus is saturated if the utilization is 25% */ +#define INT_BUS_SATURATION_RATIO 25 + +enum int_level_idx { + LV_0, + LV_1, + LV_2, + LV_3, + LV_4, + _LV_END +}; + +enum exynos_ppmu_list { + PPMU_RIGHT, + PPMU_END, +}; + +struct busfreq_data_int { + struct device *dev; + struct devfreq *devfreq; + struct regulator *vdd_int; + struct exynos_ppmu ppmu[PPMU_END]; + unsigned long curr_freq; + bool disabled; + + struct notifier_block pm_notifier; + struct mutex lock; + struct pm_qos_request int_req; + struct clk *int_clk; +}; + +struct int_bus_opp_table { + unsigned int idx; + unsigned long clk; + unsigned long volt; +}; + +static struct int_bus_opp_table exynos5_int_opp_table[] = { + {LV_0, 266000, 1025000}, + {LV_1, 200000, 1025000}, + {LV_2, 160000, 1025000}, + {LV_3, 133000, 1025000}, + {LV_4, 100000, 1025000}, + {0, 0, 0}, +}; + +static void busfreq_mon_reset(struct busfreq_data_int *data) +{ + unsigned int i; + + for (i = PPMU_RIGHT; i < PPMU_END; i++) { + void __iomem *ppmu_base = data->ppmu[i].hw_base; + + /* Reset the performance and cycle counters */ + exynos_ppmu_reset(ppmu_base); + + /* Setup count registers to monitor read/write transactions */ + data->ppmu[i].event[PPMU_PMNCNT3] = RDWR_DATA_COUNT; + exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3, + data->ppmu[i].event[PPMU_PMNCNT3]); + + exynos_ppmu_start(ppmu_base); + } +} + +static void exynos5_read_ppmu(struct busfreq_data_int *data) +{ + int i, j; + + for (i = PPMU_RIGHT; i < PPMU_END; i++) { + void __iomem *ppmu_base = data->ppmu[i].hw_base; + + exynos_ppmu_stop(ppmu_base); + + /* Update local data from PPMU */ + data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT); + + for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) { + if (data->ppmu[i].event[j] == 0) + data->ppmu[i].count[j] = 0; + else + data->ppmu[i].count[j] = + exynos_ppmu_read(ppmu_base, j); + } + } + + busfreq_mon_reset(data); +} + +static int exynos5_int_setvolt(struct busfreq_data_int *data, + unsigned long volt) +{ + return regulator_set_voltage(data->vdd_int, volt, MAX_SAFEVOLT); +} + +static int exynos5_busfreq_int_target(struct device *dev, unsigned long *_freq, + u32 flags) +{ + int err = 0; + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + struct opp *opp; + unsigned long old_freq, freq; + unsigned long volt; + + rcu_read_lock(); + opp = devfreq_recommended_opp(dev, _freq, flags); + if (IS_ERR(opp)) { + rcu_read_unlock(); + dev_err(dev, "%s: Invalid OPP.\n", __func__); + return PTR_ERR(opp); + } + + freq = opp_get_freq(opp); + volt = opp_get_voltage(opp); + rcu_read_unlock(); + + old_freq = data->curr_freq; + + if (old_freq == freq) + return 0; + + dev_dbg(dev, "targetting %lukHz %luuV\n", freq, volt); + + mutex_lock(&data->lock); + + if (data->disabled) + goto out; + + if (freq > exynos5_int_opp_table[0].clk) + pm_qos_update_request(&data->int_req, freq * 16 / 1000); + else + pm_qos_update_request(&data->int_req, -1); + + if (old_freq < freq) + err = exynos5_int_setvolt(data, volt); + if (err) + goto out; + + err = clk_set_rate(data->int_clk, freq * 1000); + + if (err) + goto out; + + if (old_freq > freq) + err = exynos5_int_setvolt(data, volt); + if (err) + goto out; + + data->curr_freq = freq; +out: + mutex_unlock(&data->lock); + return err; +} + +static int exynos5_get_busier_dmc(struct busfreq_data_int *data) +{ + int i, j; + int busy = 0; + unsigned int temp = 0; + + for (i = PPMU_RIGHT; i < PPMU_END; i++) { + for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) { + if (data->ppmu[i].count[j] > temp) { + temp = data->ppmu[i].count[j]; + busy = i; + } + } + } + + return busy; +} + +static int exynos5_int_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + int busier_dmc; + + exynos5_read_ppmu(data); + busier_dmc = exynos5_get_busier_dmc(data); + + stat->current_frequency = data->curr_freq; + + /* Number of cycles spent on memory access */ + stat->busy_time = data->ppmu[busier_dmc].count[PPMU_PMNCNT3]; + stat->busy_time *= 100 / INT_BUS_SATURATION_RATIO; + stat->total_time = data->ppmu[busier_dmc].ccnt; + + return 0; +} +static void exynos5_int_exit(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + devfreq_unregister_opp_notifier(dev, data->devfreq); +} + +static struct devfreq_dev_profile exynos5_devfreq_int_profile = { + .initial_freq = 160000, + .polling_ms = 100, + .target = exynos5_busfreq_int_target, + .get_dev_status = exynos5_int_get_dev_status, + .exit = exynos5_int_exit, +}; + +static int exynos5250_init_int_tables(struct busfreq_data_int *data) +{ + int i, err = 0; + + for (i = LV_0; i < _LV_END; i++) { + err = opp_add(data->dev, exynos5_int_opp_table[i].clk, + exynos5_int_opp_table[i].volt); + if (err) { + dev_err(data->dev, "Cannot add opp entries.\n"); + return err; + } + } + + return 0; +} + +static int exynos5_busfreq_int_pm_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct busfreq_data_int *data = container_of(this, + struct busfreq_data_int, pm_notifier); + struct opp *opp; + unsigned long maxfreq = ULONG_MAX; + unsigned long freq; + unsigned long volt; + int err = 0; + + switch (event) { + case PM_SUSPEND_PREPARE: + /* Set Fastest and Deactivate DVFS */ + mutex_lock(&data->lock); + + data->disabled = true; + + rcu_read_lock(); + opp = opp_find_freq_floor(data->dev, &maxfreq); + if (IS_ERR(opp)) { + rcu_read_unlock(); + err = PTR_ERR(opp); + goto unlock; + } + freq = opp_get_freq(opp); + volt = opp_get_voltage(opp); + rcu_read_unlock(); + + err = exynos5_int_setvolt(data, volt); + if (err) + goto unlock; + + err = clk_set_rate(data->int_clk, freq * 1000); + + if (err) + goto unlock; + + data->curr_freq = freq; +unlock: + mutex_unlock(&data->lock); + if (err) + return NOTIFY_BAD; + return NOTIFY_OK; + case PM_POST_RESTORE: + case PM_POST_SUSPEND: + /* Reactivate */ + mutex_lock(&data->lock); + data->disabled = false; + mutex_unlock(&data->lock); + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +static __devinit int exynos5_busfreq_int_probe(struct platform_device *pdev) +{ + struct busfreq_data_int *data; + struct opp *opp; + struct device *dev = &pdev->dev; + struct device_node *np; + unsigned long initial_freq; + unsigned long initial_volt; + int err = 0; + int i; + + data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data_int), + GFP_KERNEL); + if (data == NULL) { + dev_err(dev, "Cannot allocate memory.\n"); + return -ENOMEM; + } + + np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-ppmu"); + if (np == NULL) { + pr_err("Unable to find PPMU node\n"); + return -ENOENT; + } + + for (i = PPMU_RIGHT; i < PPMU_END; i++) { + /* map PPMU memory region */ + data->ppmu[i].hw_base = of_iomap(np, i); + if (data->ppmu[i].hw_base == NULL) { + dev_err(&pdev->dev, "failed to map memory region\n"); + return -ENOMEM; + } + } + data->pm_notifier.notifier_call = exynos5_busfreq_int_pm_notifier_event; + data->dev = dev; + mutex_init(&data->lock); + + err = exynos5250_init_int_tables(data); + if (err) + goto err_regulator; + + data->vdd_int = regulator_get(dev, "vdd_int"); + if (IS_ERR(data->vdd_int)) { + dev_err(dev, "Cannot get the regulator \"vdd_int\"\n"); + err = PTR_ERR(data->vdd_int); + goto err_regulator; + } + + data->int_clk = clk_get(dev, "int_clk"); + if (IS_ERR(data->int_clk)) { + dev_err(dev, "Cannot get clock \"int_clk\"\n"); + err = PTR_ERR(data->int_clk); + goto err_clock; + } + + rcu_read_lock(); + opp = opp_find_freq_floor(dev, + &exynos5_devfreq_int_profile.initial_freq); + if (IS_ERR(opp)) { + rcu_read_unlock(); + dev_err(dev, "Invalid initial frequency %lu kHz.\n", + exynos5_devfreq_int_profile.initial_freq); + err = PTR_ERR(opp); + goto err_opp_add; + } + initial_freq = opp_get_freq(opp); + initial_volt = opp_get_voltage(opp); + rcu_read_unlock(); + data->curr_freq = initial_freq; + + err = clk_set_rate(data->int_clk, initial_freq * 1000); + if (err) { + dev_err(dev, "Failed to set initial frequency\n"); + goto err_opp_add; + } + + err = exynos5_int_setvolt(data, initial_volt); + if (err) + goto err_opp_add; + + platform_set_drvdata(pdev, data); + + busfreq_mon_reset(data); + + data->devfreq = devfreq_add_device(dev, &exynos5_devfreq_int_profile, + "simple_ondemand", NULL); + + if (IS_ERR(data->devfreq)) { + err = PTR_ERR(data->devfreq); + goto err_devfreq_add; + } + + devfreq_register_opp_notifier(dev, data->devfreq); + + err = register_pm_notifier(&data->pm_notifier); + if (err) { + dev_err(dev, "Failed to setup pm notifier\n"); + goto err_devfreq_add; + } + + /* TODO: Add a new QOS class for int/mif bus */ + pm_qos_add_request(&data->int_req, PM_QOS_NETWORK_THROUGHPUT, -1); + + return 0; + +err_devfreq_add: + devfreq_remove_device(data->devfreq); + platform_set_drvdata(pdev, NULL); +err_opp_add: + clk_put(data->int_clk); +err_clock: + regulator_put(data->vdd_int); +err_regulator: + return err; +} + +static __devexit int exynos5_busfreq_int_remove(struct platform_device *pdev) +{ + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + pm_qos_remove_request(&data->int_req); + unregister_pm_notifier(&data->pm_notifier); + devfreq_remove_device(data->devfreq); + regulator_put(data->vdd_int); + clk_put(data->int_clk); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static int exynos5_busfreq_int_resume(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + busfreq_mon_reset(data); + return 0; +} + +static const struct dev_pm_ops exynos5_busfreq_int_pm = { + .resume = exynos5_busfreq_int_resume, +}; + +/* platform device pointer for exynos5 devfreq device. */ +static struct platform_device *exynos5_devfreq_pdev; + +static struct platform_driver exynos5_busfreq_int_driver = { + .probe = exynos5_busfreq_int_probe, + .remove = __devexit_p(exynos5_busfreq_int_remove), + .driver = { + .name = "exynos5-bus-int", + .owner = THIS_MODULE, + .pm = &exynos5_busfreq_int_pm, + }, +}; + +static int __init exynos5_busfreq_int_init(void) +{ + int ret; + + ret = platform_driver_register(&exynos5_busfreq_int_driver); + if (ret < 0) + goto out; + + exynos5_devfreq_pdev = + platform_device_register_simple("exynos5-bus-int", -1, NULL, 0); + if (IS_ERR_OR_NULL(exynos5_devfreq_pdev)) { + ret = PTR_ERR(exynos5_devfreq_pdev); + goto out1; + } + + return 0; +out1: + platform_driver_unregister(&exynos5_busfreq_int_driver); +out: + return ret; +} +late_initcall(exynos5_busfreq_int_init); + +static void __exit exynos5_busfreq_int_exit(void) +{ + platform_device_unregister(exynos5_devfreq_pdev); + platform_driver_unregister(&exynos5_busfreq_int_driver); +} +module_exit(exynos5_busfreq_int_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("EXYNOS5 busfreq driver with devfreq framework"); diff --git a/drivers/devfreq/exynos/exynos_ppmu.c b/drivers/devfreq/exynos/exynos_ppmu.c new file mode 100644 index 0000000..d667825 --- /dev/null +++ b/drivers/devfreq/exynos/exynos_ppmu.c @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS - PPMU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/io.h> +#include <linux/exynos_ppmu.h> + +void exynos_ppmu_reset(void __iomem *ppmu_base) +{ + __raw_writel(PPMU_CYCLE_RESET | PPMU_COUNTER_RESET, ppmu_base); + __raw_writel(PPMU_ENABLE_CYCLE | + PPMU_ENABLE_COUNT0 | + PPMU_ENABLE_COUNT1 | + PPMU_ENABLE_COUNT2 | + PPMU_ENABLE_COUNT3, + ppmu_base + PPMU_CNTENS); +} + +void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch, + unsigned int evt) +{ + __raw_writel(evt, ppmu_base + PPMU_BEVTSEL(ch)); +} + +void exynos_ppmu_start(void __iomem *ppmu_base) +{ + __raw_writel(PPMU_ENABLE, ppmu_base); +} + +void exynos_ppmu_stop(void __iomem *ppmu_base) +{ + __raw_writel(PPMU_DISABLE, ppmu_base); +} + +unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch) +{ + unsigned int total; + + if (ch == PPMU_PMNCNT3) + total = ((__raw_readl(ppmu_base + PMCNT_OFFSET(ch)) << 8) | + __raw_readl(ppmu_base + PMCNT_OFFSET(ch + 1))); + else + total = __raw_readl(ppmu_base + PMCNT_OFFSET(ch)); + + return total; +} diff --git a/include/linux/exynos_ppmu.h b/include/linux/exynos_ppmu.h new file mode 100644 index 0000000..b46d31b --- /dev/null +++ b/include/linux/exynos_ppmu.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS PPMU header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __DEVFREQ_EXYNOS_PPMU_H +#define __DEVFREQ_EXYNOS_PPMU_H __FILE__ + +#include <linux/ktime.h> + +/* For PPMU Control */ +#define PPMU_ENABLE BIT(0) +#define PPMU_DISABLE 0x0 +#define PPMU_CYCLE_RESET BIT(1) +#define PPMU_COUNTER_RESET BIT(2) + +#define PPMU_ENABLE_COUNT0 BIT(0) +#define PPMU_ENABLE_COUNT1 BIT(1) +#define PPMU_ENABLE_COUNT2 BIT(2) +#define PPMU_ENABLE_COUNT3 BIT(3) +#define PPMU_ENABLE_CYCLE BIT(31) + +#define PPMU_CNTENS 0x10 +#define PPMU_FLAG 0x50 +#define PPMU_CCNT_OVERFLOW BIT(31) +#define PPMU_CCNT 0x100 + +#define PPMU_PMCNT0 0x110 +#define PPMU_PMCNT_OFFSET 0x10 +#define PMCNT_OFFSET(x) (PPMU_PMCNT0 + (PPMU_PMCNT_OFFSET * x)) + +#define PPMU_BEVT0SEL 0x1000 +#define PPMU_BEVTSEL_OFFSET 0x100 +#define PPMU_BEVTSEL(x) (PPMU_BEVT0SEL + (ch * PPMU_BEVTSEL_OFFSET)) + +/* For Event Selection */ +#define RD_DATA_COUNT 0x5 +#define WR_DATA_COUNT 0x6 +#define RDWR_DATA_COUNT 0x7 + +enum ppmu_counter { + PPMU_PMNCNT0, + PPMU_PMCCNT1, + PPMU_PMNCNT2, + PPMU_PMNCNT3, + PPMU_PMNCNT_MAX, +}; + +struct bus_opp_table { + unsigned int idx; + unsigned long clk; + unsigned long volt; +}; + +struct exynos_ppmu { + void __iomem *hw_base; + unsigned int ccnt; + unsigned int event[PPMU_PMNCNT_MAX]; + unsigned int count[PPMU_PMNCNT_MAX]; + unsigned long long ns; + ktime_t reset_time; + bool ccnt_overflow; + bool count_overflow[PPMU_PMNCNT_MAX]; +}; + +void exynos_ppmu_reset(void __iomem *ppmu_base); +void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch, + unsigned int evt); +void exynos_ppmu_start(void __iomem *ppmu_base); +void exynos_ppmu_stop(void __iomem *ppmu_base); +unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch); +#endif /* __DEVFREQ_EXYNOS_PPMU_H */ + -- 1.7.8.6 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v4 4/4] PM: Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 2013-01-18 13:24 ` [PATCH v4 4/4] PM: Devfreq: " Abhilash Kesavan @ 2013-02-03 15:47 ` Abhilash Kesavan 2013-02-04 6:41 ` myungjoo.ham 2013-02-04 12:14 ` [PATCH v5 " Abhilash Kesavan 1 sibling, 1 reply; 18+ messages in thread From: Abhilash Kesavan @ 2013-02-03 15:47 UTC (permalink / raw) To: myungjoo.ham, linux-kernel, linux-pm, kgene.kim Cc: kyungmin.park, rjw, jhbird.choi Hi Myungjoo, Any comments on this patch ? Abhilash On Fri, Jan 18, 2013 at 6:54 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote: > Exynos5-bus device devfreq driver monitors PPMU counters and > adjusts operating frequencies and voltages with OPP. ASV should > be used to provide appropriate voltages as per the speed group > of the SoC rather than using a constant 1.025V. > > Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> > Cc: Jonghwan Choi <jhbird.choi@samsung.com> > Cc: Kukjin Kim <kgene.kim@samsung.com> > --- > Changes since RFC v1: > * Moved the Exynos5 PPMU driver to machine specific directory > * Migrated to the PM QOS framework > Changes since v2: > * Moved the PPMU driver to drivers/devfreq/exynos > * Fixed whitespace, commenting, empty lines in PPMU driver > Changes since v3: > * Removed the custom devfreq monitor and PPMU polling function > * Moved exynos5 PPMU access functions to the devfreq driver > > drivers/devfreq/Kconfig | 10 + > drivers/devfreq/Makefile | 1 + > drivers/devfreq/exynos/Makefile | 1 + > drivers/devfreq/exynos/exynos5_bus.c | 502 ++++++++++++++++++++++++++++++++++ > drivers/devfreq/exynos/exynos_ppmu.c | 55 ++++ > include/linux/exynos_ppmu.h | 79 ++++++ > 6 files changed, 648 insertions(+), 0 deletions(-) > create mode 100644 drivers/devfreq/exynos/exynos5_bus.c > create mode 100644 drivers/devfreq/exynos/exynos_ppmu.c > create mode 100644 include/linux/exynos_ppmu.h > > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig > index 0f079be..1560d0d 100644 > --- a/drivers/devfreq/Kconfig > +++ b/drivers/devfreq/Kconfig > @@ -78,4 +78,14 @@ config ARM_EXYNOS4_BUS_DEVFREQ > To operate with optimal voltages, ASV support is required > (CONFIG_EXYNOS_ASV). > > +config ARM_EXYNOS5_BUS_DEVFREQ > + bool "ARM Exynos5250 Bus DEVFREQ Driver" > + depends on SOC_EXYNOS5250 > + select ARCH_HAS_OPP > + select DEVFREQ_GOV_SIMPLE_ONDEMAND > + help > + This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int). > + It reads PPMU counters of memory controllers and adjusts the > + operating frequencies and voltages with OPP support. > + > endif # PM_DEVFREQ > diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile > index 3bc1fef..16138c9 100644 > --- a/drivers/devfreq/Makefile > +++ b/drivers/devfreq/Makefile > @@ -6,3 +6,4 @@ obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o > > # DEVFREQ Drivers > obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/ > +obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/ > diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile > index 1498823..bfaaf5b 100644 > --- a/drivers/devfreq/exynos/Makefile > +++ b/drivers/devfreq/exynos/Makefile > @@ -1,2 +1,3 @@ > # Exynos DEVFREQ Drivers > obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o > +obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_bus.o > diff --git a/drivers/devfreq/exynos/exynos5_bus.c b/drivers/devfreq/exynos/exynos5_bus.c > new file mode 100644 > index 0000000..fbdcbaf > --- /dev/null > +++ b/drivers/devfreq/exynos/exynos5_bus.c > @@ -0,0 +1,502 @@ > +/* > + * Copyright (c) 2012 Samsung Electronics Co., Ltd. > + * http://www.samsung.com/ > + * > + * EXYNOS5 INT clock frequency scaling support using DEVFREQ framework > + * Based on work done by Jonghwan Choi <jhbird.choi@samsung.com> > + * Support for only EXYNOS5250 is present. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + * > + */ > + > +#include <linux/module.h> > +#include <linux/devfreq.h> > +#include <linux/io.h> > +#include <linux/opp.h> > +#include <linux/slab.h> > +#include <linux/suspend.h> > +#include <linux/opp.h> > +#include <linux/clk.h> > +#include <linux/delay.h> > +#include <linux/platform_device.h> > +#include <linux/pm_qos.h> > +#include <linux/regulator/consumer.h> > +#include <linux/of_address.h> > +#include <linux/of_platform.h> > +#include <linux/exynos_ppmu.h> > + > +#define MAX_SAFEVOLT 1100000 /* 1.10V */ > +/* Assume that the bus is saturated if the utilization is 25% */ > +#define INT_BUS_SATURATION_RATIO 25 > + > +enum int_level_idx { > + LV_0, > + LV_1, > + LV_2, > + LV_3, > + LV_4, > + _LV_END > +}; > + > +enum exynos_ppmu_list { > + PPMU_RIGHT, > + PPMU_END, > +}; > + > +struct busfreq_data_int { > + struct device *dev; > + struct devfreq *devfreq; > + struct regulator *vdd_int; > + struct exynos_ppmu ppmu[PPMU_END]; > + unsigned long curr_freq; > + bool disabled; > + > + struct notifier_block pm_notifier; > + struct mutex lock; > + struct pm_qos_request int_req; > + struct clk *int_clk; > +}; > + > +struct int_bus_opp_table { > + unsigned int idx; > + unsigned long clk; > + unsigned long volt; > +}; > + > +static struct int_bus_opp_table exynos5_int_opp_table[] = { > + {LV_0, 266000, 1025000}, > + {LV_1, 200000, 1025000}, > + {LV_2, 160000, 1025000}, > + {LV_3, 133000, 1025000}, > + {LV_4, 100000, 1025000}, > + {0, 0, 0}, > +}; > + > +static void busfreq_mon_reset(struct busfreq_data_int *data) > +{ > + unsigned int i; > + > + for (i = PPMU_RIGHT; i < PPMU_END; i++) { > + void __iomem *ppmu_base = data->ppmu[i].hw_base; > + > + /* Reset the performance and cycle counters */ > + exynos_ppmu_reset(ppmu_base); > + > + /* Setup count registers to monitor read/write transactions */ > + data->ppmu[i].event[PPMU_PMNCNT3] = RDWR_DATA_COUNT; > + exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3, > + data->ppmu[i].event[PPMU_PMNCNT3]); > + > + exynos_ppmu_start(ppmu_base); > + } > +} > + > +static void exynos5_read_ppmu(struct busfreq_data_int *data) > +{ > + int i, j; > + > + for (i = PPMU_RIGHT; i < PPMU_END; i++) { > + void __iomem *ppmu_base = data->ppmu[i].hw_base; > + > + exynos_ppmu_stop(ppmu_base); > + > + /* Update local data from PPMU */ > + data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT); > + > + for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) { > + if (data->ppmu[i].event[j] == 0) > + data->ppmu[i].count[j] = 0; > + else > + data->ppmu[i].count[j] = > + exynos_ppmu_read(ppmu_base, j); > + } > + } > + > + busfreq_mon_reset(data); > +} > + > +static int exynos5_int_setvolt(struct busfreq_data_int *data, > + unsigned long volt) > +{ > + return regulator_set_voltage(data->vdd_int, volt, MAX_SAFEVOLT); > +} > + > +static int exynos5_busfreq_int_target(struct device *dev, unsigned long *_freq, > + u32 flags) > +{ > + int err = 0; > + struct platform_device *pdev = container_of(dev, struct platform_device, > + dev); > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + struct opp *opp; > + unsigned long old_freq, freq; > + unsigned long volt; > + > + rcu_read_lock(); > + opp = devfreq_recommended_opp(dev, _freq, flags); > + if (IS_ERR(opp)) { > + rcu_read_unlock(); > + dev_err(dev, "%s: Invalid OPP.\n", __func__); > + return PTR_ERR(opp); > + } > + > + freq = opp_get_freq(opp); > + volt = opp_get_voltage(opp); > + rcu_read_unlock(); > + > + old_freq = data->curr_freq; > + > + if (old_freq == freq) > + return 0; > + > + dev_dbg(dev, "targetting %lukHz %luuV\n", freq, volt); > + > + mutex_lock(&data->lock); > + > + if (data->disabled) > + goto out; > + > + if (freq > exynos5_int_opp_table[0].clk) > + pm_qos_update_request(&data->int_req, freq * 16 / 1000); > + else > + pm_qos_update_request(&data->int_req, -1); > + > + if (old_freq < freq) > + err = exynos5_int_setvolt(data, volt); > + if (err) > + goto out; > + > + err = clk_set_rate(data->int_clk, freq * 1000); > + > + if (err) > + goto out; > + > + if (old_freq > freq) > + err = exynos5_int_setvolt(data, volt); > + if (err) > + goto out; > + > + data->curr_freq = freq; > +out: > + mutex_unlock(&data->lock); > + return err; > +} > + > +static int exynos5_get_busier_dmc(struct busfreq_data_int *data) > +{ > + int i, j; > + int busy = 0; > + unsigned int temp = 0; > + > + for (i = PPMU_RIGHT; i < PPMU_END; i++) { > + for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) { > + if (data->ppmu[i].count[j] > temp) { > + temp = data->ppmu[i].count[j]; > + busy = i; > + } > + } > + } > + > + return busy; > +} > + > +static int exynos5_int_get_dev_status(struct device *dev, > + struct devfreq_dev_status *stat) > +{ > + struct platform_device *pdev = container_of(dev, struct platform_device, > + dev); > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + int busier_dmc; > + > + exynos5_read_ppmu(data); > + busier_dmc = exynos5_get_busier_dmc(data); > + > + stat->current_frequency = data->curr_freq; > + > + /* Number of cycles spent on memory access */ > + stat->busy_time = data->ppmu[busier_dmc].count[PPMU_PMNCNT3]; > + stat->busy_time *= 100 / INT_BUS_SATURATION_RATIO; > + stat->total_time = data->ppmu[busier_dmc].ccnt; > + > + return 0; > +} > +static void exynos5_int_exit(struct device *dev) > +{ > + struct platform_device *pdev = container_of(dev, struct platform_device, > + dev); > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + > + devfreq_unregister_opp_notifier(dev, data->devfreq); > +} > + > +static struct devfreq_dev_profile exynos5_devfreq_int_profile = { > + .initial_freq = 160000, > + .polling_ms = 100, > + .target = exynos5_busfreq_int_target, > + .get_dev_status = exynos5_int_get_dev_status, > + .exit = exynos5_int_exit, > +}; > + > +static int exynos5250_init_int_tables(struct busfreq_data_int *data) > +{ > + int i, err = 0; > + > + for (i = LV_0; i < _LV_END; i++) { > + err = opp_add(data->dev, exynos5_int_opp_table[i].clk, > + exynos5_int_opp_table[i].volt); > + if (err) { > + dev_err(data->dev, "Cannot add opp entries.\n"); > + return err; > + } > + } > + > + return 0; > +} > + > +static int exynos5_busfreq_int_pm_notifier_event(struct notifier_block *this, > + unsigned long event, void *ptr) > +{ > + struct busfreq_data_int *data = container_of(this, > + struct busfreq_data_int, pm_notifier); > + struct opp *opp; > + unsigned long maxfreq = ULONG_MAX; > + unsigned long freq; > + unsigned long volt; > + int err = 0; > + > + switch (event) { > + case PM_SUSPEND_PREPARE: > + /* Set Fastest and Deactivate DVFS */ > + mutex_lock(&data->lock); > + > + data->disabled = true; > + > + rcu_read_lock(); > + opp = opp_find_freq_floor(data->dev, &maxfreq); > + if (IS_ERR(opp)) { > + rcu_read_unlock(); > + err = PTR_ERR(opp); > + goto unlock; > + } > + freq = opp_get_freq(opp); > + volt = opp_get_voltage(opp); > + rcu_read_unlock(); > + > + err = exynos5_int_setvolt(data, volt); > + if (err) > + goto unlock; > + > + err = clk_set_rate(data->int_clk, freq * 1000); > + > + if (err) > + goto unlock; > + > + data->curr_freq = freq; > +unlock: > + mutex_unlock(&data->lock); > + if (err) > + return NOTIFY_BAD; > + return NOTIFY_OK; > + case PM_POST_RESTORE: > + case PM_POST_SUSPEND: > + /* Reactivate */ > + mutex_lock(&data->lock); > + data->disabled = false; > + mutex_unlock(&data->lock); > + return NOTIFY_OK; > + } > + > + return NOTIFY_DONE; > +} > + > +static __devinit int exynos5_busfreq_int_probe(struct platform_device *pdev) > +{ > + struct busfreq_data_int *data; > + struct opp *opp; > + struct device *dev = &pdev->dev; > + struct device_node *np; > + unsigned long initial_freq; > + unsigned long initial_volt; > + int err = 0; > + int i; > + > + data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data_int), > + GFP_KERNEL); > + if (data == NULL) { > + dev_err(dev, "Cannot allocate memory.\n"); > + return -ENOMEM; > + } > + > + np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-ppmu"); > + if (np == NULL) { > + pr_err("Unable to find PPMU node\n"); > + return -ENOENT; > + } > + > + for (i = PPMU_RIGHT; i < PPMU_END; i++) { > + /* map PPMU memory region */ > + data->ppmu[i].hw_base = of_iomap(np, i); > + if (data->ppmu[i].hw_base == NULL) { > + dev_err(&pdev->dev, "failed to map memory region\n"); > + return -ENOMEM; > + } > + } > + data->pm_notifier.notifier_call = exynos5_busfreq_int_pm_notifier_event; > + data->dev = dev; > + mutex_init(&data->lock); > + > + err = exynos5250_init_int_tables(data); > + if (err) > + goto err_regulator; > + > + data->vdd_int = regulator_get(dev, "vdd_int"); > + if (IS_ERR(data->vdd_int)) { > + dev_err(dev, "Cannot get the regulator \"vdd_int\"\n"); > + err = PTR_ERR(data->vdd_int); > + goto err_regulator; > + } > + > + data->int_clk = clk_get(dev, "int_clk"); > + if (IS_ERR(data->int_clk)) { > + dev_err(dev, "Cannot get clock \"int_clk\"\n"); > + err = PTR_ERR(data->int_clk); > + goto err_clock; > + } > + > + rcu_read_lock(); > + opp = opp_find_freq_floor(dev, > + &exynos5_devfreq_int_profile.initial_freq); > + if (IS_ERR(opp)) { > + rcu_read_unlock(); > + dev_err(dev, "Invalid initial frequency %lu kHz.\n", > + exynos5_devfreq_int_profile.initial_freq); > + err = PTR_ERR(opp); > + goto err_opp_add; > + } > + initial_freq = opp_get_freq(opp); > + initial_volt = opp_get_voltage(opp); > + rcu_read_unlock(); > + data->curr_freq = initial_freq; > + > + err = clk_set_rate(data->int_clk, initial_freq * 1000); > + if (err) { > + dev_err(dev, "Failed to set initial frequency\n"); > + goto err_opp_add; > + } > + > + err = exynos5_int_setvolt(data, initial_volt); > + if (err) > + goto err_opp_add; > + > + platform_set_drvdata(pdev, data); > + > + busfreq_mon_reset(data); > + > + data->devfreq = devfreq_add_device(dev, &exynos5_devfreq_int_profile, > + "simple_ondemand", NULL); > + > + if (IS_ERR(data->devfreq)) { > + err = PTR_ERR(data->devfreq); > + goto err_devfreq_add; > + } > + > + devfreq_register_opp_notifier(dev, data->devfreq); > + > + err = register_pm_notifier(&data->pm_notifier); > + if (err) { > + dev_err(dev, "Failed to setup pm notifier\n"); > + goto err_devfreq_add; > + } > + > + /* TODO: Add a new QOS class for int/mif bus */ > + pm_qos_add_request(&data->int_req, PM_QOS_NETWORK_THROUGHPUT, -1); > + > + return 0; > + > +err_devfreq_add: > + devfreq_remove_device(data->devfreq); > + platform_set_drvdata(pdev, NULL); > +err_opp_add: > + clk_put(data->int_clk); > +err_clock: > + regulator_put(data->vdd_int); > +err_regulator: > + return err; > +} > + > +static __devexit int exynos5_busfreq_int_remove(struct platform_device *pdev) > +{ > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + > + pm_qos_remove_request(&data->int_req); > + unregister_pm_notifier(&data->pm_notifier); > + devfreq_remove_device(data->devfreq); > + regulator_put(data->vdd_int); > + clk_put(data->int_clk); > + platform_set_drvdata(pdev, NULL); > + > + return 0; > +} > + > +static int exynos5_busfreq_int_resume(struct device *dev) > +{ > + struct platform_device *pdev = container_of(dev, struct platform_device, > + dev); > + struct busfreq_data_int *data = platform_get_drvdata(pdev); > + > + busfreq_mon_reset(data); > + return 0; > +} > + > +static const struct dev_pm_ops exynos5_busfreq_int_pm = { > + .resume = exynos5_busfreq_int_resume, > +}; > + > +/* platform device pointer for exynos5 devfreq device. */ > +static struct platform_device *exynos5_devfreq_pdev; > + > +static struct platform_driver exynos5_busfreq_int_driver = { > + .probe = exynos5_busfreq_int_probe, > + .remove = __devexit_p(exynos5_busfreq_int_remove), > + .driver = { > + .name = "exynos5-bus-int", > + .owner = THIS_MODULE, > + .pm = &exynos5_busfreq_int_pm, > + }, > +}; > + > +static int __init exynos5_busfreq_int_init(void) > +{ > + int ret; > + > + ret = platform_driver_register(&exynos5_busfreq_int_driver); > + if (ret < 0) > + goto out; > + > + exynos5_devfreq_pdev = > + platform_device_register_simple("exynos5-bus-int", -1, NULL, 0); > + if (IS_ERR_OR_NULL(exynos5_devfreq_pdev)) { > + ret = PTR_ERR(exynos5_devfreq_pdev); > + goto out1; > + } > + > + return 0; > +out1: > + platform_driver_unregister(&exynos5_busfreq_int_driver); > +out: > + return ret; > +} > +late_initcall(exynos5_busfreq_int_init); > + > +static void __exit exynos5_busfreq_int_exit(void) > +{ > + platform_device_unregister(exynos5_devfreq_pdev); > + platform_driver_unregister(&exynos5_busfreq_int_driver); > +} > +module_exit(exynos5_busfreq_int_exit); > + > +MODULE_LICENSE("GPL"); > +MODULE_DESCRIPTION("EXYNOS5 busfreq driver with devfreq framework"); > diff --git a/drivers/devfreq/exynos/exynos_ppmu.c b/drivers/devfreq/exynos/exynos_ppmu.c > new file mode 100644 > index 0000000..d667825 > --- /dev/null > +++ b/drivers/devfreq/exynos/exynos_ppmu.c > @@ -0,0 +1,55 @@ > +/* > + * Copyright (c) 2012 Samsung Electronics Co., Ltd. > + * http://www.samsung.com/ > + * > + * EXYNOS - PPMU support > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > + */ > + > +#include <linux/kernel.h> > +#include <linux/types.h> > +#include <linux/io.h> > +#include <linux/exynos_ppmu.h> > + > +void exynos_ppmu_reset(void __iomem *ppmu_base) > +{ > + __raw_writel(PPMU_CYCLE_RESET | PPMU_COUNTER_RESET, ppmu_base); > + __raw_writel(PPMU_ENABLE_CYCLE | > + PPMU_ENABLE_COUNT0 | > + PPMU_ENABLE_COUNT1 | > + PPMU_ENABLE_COUNT2 | > + PPMU_ENABLE_COUNT3, > + ppmu_base + PPMU_CNTENS); > +} > + > +void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch, > + unsigned int evt) > +{ > + __raw_writel(evt, ppmu_base + PPMU_BEVTSEL(ch)); > +} > + > +void exynos_ppmu_start(void __iomem *ppmu_base) > +{ > + __raw_writel(PPMU_ENABLE, ppmu_base); > +} > + > +void exynos_ppmu_stop(void __iomem *ppmu_base) > +{ > + __raw_writel(PPMU_DISABLE, ppmu_base); > +} > + > +unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch) > +{ > + unsigned int total; > + > + if (ch == PPMU_PMNCNT3) > + total = ((__raw_readl(ppmu_base + PMCNT_OFFSET(ch)) << 8) | > + __raw_readl(ppmu_base + PMCNT_OFFSET(ch + 1))); > + else > + total = __raw_readl(ppmu_base + PMCNT_OFFSET(ch)); > + > + return total; > +} > diff --git a/include/linux/exynos_ppmu.h b/include/linux/exynos_ppmu.h > new file mode 100644 > index 0000000..b46d31b > --- /dev/null > +++ b/include/linux/exynos_ppmu.h > @@ -0,0 +1,79 @@ > +/* > + * Copyright (c) 2012 Samsung Electronics Co., Ltd. > + * http://www.samsung.com/ > + * > + * EXYNOS PPMU header > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 as > + * published by the Free Software Foundation. > +*/ > + > +#ifndef __DEVFREQ_EXYNOS_PPMU_H > +#define __DEVFREQ_EXYNOS_PPMU_H __FILE__ > + > +#include <linux/ktime.h> > + > +/* For PPMU Control */ > +#define PPMU_ENABLE BIT(0) > +#define PPMU_DISABLE 0x0 > +#define PPMU_CYCLE_RESET BIT(1) > +#define PPMU_COUNTER_RESET BIT(2) > + > +#define PPMU_ENABLE_COUNT0 BIT(0) > +#define PPMU_ENABLE_COUNT1 BIT(1) > +#define PPMU_ENABLE_COUNT2 BIT(2) > +#define PPMU_ENABLE_COUNT3 BIT(3) > +#define PPMU_ENABLE_CYCLE BIT(31) > + > +#define PPMU_CNTENS 0x10 > +#define PPMU_FLAG 0x50 > +#define PPMU_CCNT_OVERFLOW BIT(31) > +#define PPMU_CCNT 0x100 > + > +#define PPMU_PMCNT0 0x110 > +#define PPMU_PMCNT_OFFSET 0x10 > +#define PMCNT_OFFSET(x) (PPMU_PMCNT0 + (PPMU_PMCNT_OFFSET * x)) > + > +#define PPMU_BEVT0SEL 0x1000 > +#define PPMU_BEVTSEL_OFFSET 0x100 > +#define PPMU_BEVTSEL(x) (PPMU_BEVT0SEL + (ch * PPMU_BEVTSEL_OFFSET)) > + > +/* For Event Selection */ > +#define RD_DATA_COUNT 0x5 > +#define WR_DATA_COUNT 0x6 > +#define RDWR_DATA_COUNT 0x7 > + > +enum ppmu_counter { > + PPMU_PMNCNT0, > + PPMU_PMCCNT1, > + PPMU_PMNCNT2, > + PPMU_PMNCNT3, > + PPMU_PMNCNT_MAX, > +}; > + > +struct bus_opp_table { > + unsigned int idx; > + unsigned long clk; > + unsigned long volt; > +}; > + > +struct exynos_ppmu { > + void __iomem *hw_base; > + unsigned int ccnt; > + unsigned int event[PPMU_PMNCNT_MAX]; > + unsigned int count[PPMU_PMNCNT_MAX]; > + unsigned long long ns; > + ktime_t reset_time; > + bool ccnt_overflow; > + bool count_overflow[PPMU_PMNCNT_MAX]; > +}; > + > +void exynos_ppmu_reset(void __iomem *ppmu_base); > +void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch, > + unsigned int evt); > +void exynos_ppmu_start(void __iomem *ppmu_base); > +void exynos_ppmu_stop(void __iomem *ppmu_base); > +unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch); > +#endif /* __DEVFREQ_EXYNOS_PPMU_H */ > + > -- > 1.7.8.6 > ^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH v4 4/4] PM: Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 2013-02-03 15:47 ` Abhilash Kesavan @ 2013-02-04 6:41 ` myungjoo.ham 2013-02-04 8:03 ` Abhilash Kesavan 0 siblings, 1 reply; 18+ messages in thread From: myungjoo.ham @ 2013-02-04 6:41 UTC (permalink / raw) To: 'Abhilash Kesavan', linux-kernel, linux-pm, kgene.kim Cc: kyungmin.park, rjw, jhbird.choi > > > -----Original Message----- > From: Abhilash Kesavan [mailto:kesavan.abhilash@gmail.com] > Sent: Monday, February 04, 2013 12:48 AM > To: myungjoo.ham@samsung.com; linux-kernel@vger.kernel.org; linux-pm@vger.kernel.org; kgene.kim@samsung.com > Cc: kyungmin.park@samsung.com; rjw@sisk.pl; jhbird.choi@samsung.com > Subject: Re: [PATCH v4 4/4] PM: Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 > > Hi Myungjoo, > > Any comments on this patch ? > > Abhilash > Sorry for being late. One concern is that I cannot apply Patch 1/4 directly as the .dts file isn't available to me. Do you intend to apply that patch to another tree and apply the other three to devfreq tree? Another is the location of exynos_ppmu.h. Who is going to refer exynos_ppmu.h? If Exynos devfreq drivers are the only files to refer, wouldn't it be better located at drivers/devfreq/exynos/ ? Or do you intend to let someone else (drivers located not in drivers/devfreq) access exynos-ppmu? (If so, who's going to be? and that means we are going to have include/linux/devfreq/, I don't think it'd be appropriate to populate include/linux with device driver specific headers) And, there are errors (we do not have __devinit/__devexit anymore): CC drivers/devfreq/exynos/exynos5_bus.o drivers/devfreq/exynos/exynos5_bus.c:315:18: error: expected =, ,, ;, asm or __attribute__ before int drivers/devfreq/exynos/exynos5_bus.c:430:18: error: expected =, ,, ;, asm or __attribute__ before int drivers/devfreq/exynos/exynos5_bus.c:462:11: error: exynos5_busfreq_int_probe undeclared here (not in a function) drivers/devfreq/exynos/exynos5_bus.c:463:2: error: implicit declaration of function __devexit_p [-Werror=implicit-function-declaration] drivers/devfreq/exynos/exynos5_bus.c:463:24: error: exynos5_busfreq_int_remove undeclared here (not in a function) drivers/devfreq/exynos/exynos5_bus.c:235:35: warning: exynos5_devfreq_int_profile defined but not used [-Wunused-variable] drivers/devfreq/exynos/exynos5_bus.c:243:12: warning: exynos5250_init_int_tables defined but not used [-Wunused-function] drivers/devfreq/exynos/exynos5_bus.c:259:12: warning: exynos5_busfreq_int_pm_notifier_event defined but not used [-Wunused-function] cc1: some warnings being treated as errors Cheers, MyungJoo. > On Fri, Jan 18, 2013 at 6:54 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote: > > Exynos5-bus device devfreq driver monitors PPMU counters and adjusts > > operating frequencies and voltages with OPP. ASV should be used to > > provide appropriate voltages as per the speed group of the SoC rather > > than using a constant 1.025V. > > > > Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> > > Cc: Jonghwan Choi <jhbird.choi@samsung.com> > > Cc: Kukjin Kim <kgene.kim@samsung.com> > > --- > > Changes since RFC v1: > > * Moved the Exynos5 PPMU driver to machine specific directory > > * Migrated to the PM QOS framework > > Changes since v2: > > * Moved the PPMU driver to drivers/devfreq/exynos > > * Fixed whitespace, commenting, empty lines in PPMU driver Changes > > since v3: > > * Removed the custom devfreq monitor and PPMU polling function > > * Moved exynos5 PPMU access functions to the devfreq driver > > > > drivers/devfreq/Kconfig | 10 + > > drivers/devfreq/Makefile | 1 + > > drivers/devfreq/exynos/Makefile | 1 + > > drivers/devfreq/exynos/exynos5_bus.c | 502 ++++++++++++++++++++++++++++++++++ > > drivers/devfreq/exynos/exynos_ppmu.c | 55 ++++ > > include/linux/exynos_ppmu.h | 79 ++++++ > > 6 files changed, 648 insertions(+), 0 deletions(-) create mode > > 100644 drivers/devfreq/exynos/exynos5_bus.c > > create mode 100644 drivers/devfreq/exynos/exynos_ppmu.c > > create mode 100644 include/linux/exynos_ppmu.h > > ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v4 4/4] PM: Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 2013-02-04 6:41 ` myungjoo.ham @ 2013-02-04 8:03 ` Abhilash Kesavan 0 siblings, 0 replies; 18+ messages in thread From: Abhilash Kesavan @ 2013-02-04 8:03 UTC (permalink / raw) To: myungjoo.ham Cc: linux-kernel, linux-pm, kgene.kim, kyungmin.park, rjw, jhbird.choi Hi, > Sorry for being late. > > One concern is that I cannot apply Patch 1/4 directly as the .dts file isn't > available to me. > Do you intend to apply that patch to another tree and apply the other three > to devfreq tree? I have been merging the devfreq tree into Kgene's tree for my testing. I am not sure how this should get in, any suggestions ? > > Another is the location of exynos_ppmu.h. > Who is going to refer exynos_ppmu.h? > If Exynos devfreq drivers are the only files to refer, wouldn't it be better > located at drivers/devfreq/exynos/ ? > > Or do you intend to let someone else (drivers located not in > drivers/devfreq) access exynos-ppmu? > (If so, who's going to be? and that means we are going to have > include/linux/devfreq/, I don't think it'd be appropriate to populate > include/linux with device driver specific headers) In an earlier comment on this patch Olof suggested I place it in include/linux/. It is going to be used only by Exynos and I will move it into drivers/devfreq/exynos as per your suggestion. > > > > And, there are errors (we do not have __devinit/__devexit anymore): > > CC drivers/devfreq/exynos/exynos5_bus.o > drivers/devfreq/exynos/exynos5_bus.c:315:18: error: expected =, ,, ;, asm or > __attribute__ before int > drivers/devfreq/exynos/exynos5_bus.c:430:18: error: expected =, ,, ;, asm or > __attribute__ before int > drivers/devfreq/exynos/exynos5_bus.c:462:11: error: > exynos5_busfreq_int_probe undeclared here (not in a function) > drivers/devfreq/exynos/exynos5_bus.c:463:2: error: implicit declaration of > function __devexit_p [-Werror=implicit-function-declaration] > drivers/devfreq/exynos/exynos5_bus.c:463:24: error: > exynos5_busfreq_int_remove undeclared here (not in a function) > drivers/devfreq/exynos/exynos5_bus.c:235:35: warning: > exynos5_devfreq_int_profile defined but not used [-Wunused-variable] > drivers/devfreq/exynos/exynos5_bus.c:243:12: warning: > exynos5250_init_int_tables defined but not used [-Wunused-function] > drivers/devfreq/exynos/exynos5_bus.c:259:12: warning: > exynos5_busfreq_int_pm_notifier_event defined but not used > [-Wunused-function] > cc1: some warnings being treated as errors I will fix these and re-post. > > > > Cheers, > MyungJoo. > Abhilash ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v5 4/4] PM: Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 2013-01-18 13:24 ` [PATCH v4 4/4] PM: Devfreq: " Abhilash Kesavan 2013-02-03 15:47 ` Abhilash Kesavan @ 2013-02-04 12:14 ` Abhilash Kesavan 2013-02-05 9:56 ` MyungJoo Ham 1 sibling, 1 reply; 18+ messages in thread From: Abhilash Kesavan @ 2013-02-04 12:14 UTC (permalink / raw) To: myungjoo.ham, linux-kernel, linux-pm Cc: Abhilash Kesavan, Jonghwan Choi, Kukjin Kim Exynos5-bus device devfreq driver monitors PPMU counters and adjusts operating frequencies and voltages with OPP. ASV should be used to provide appropriate voltages as per the speed group of the SoC rather than using a constant 1.025V. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Cc: Jonghwan Choi <jhbird.choi@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> --- Changes since RFC v1: * Moved the Exynos5 PPMU driver to machine specific directory * Migrated to the PM QOS framework Changes since v2: * Moved the PPMU driver to drivers/devfreq/exynos * Fixed whitespace, commenting, empty lines in PPMU driver Changes since v3: * Removed the custom devfreq monitor and PPMU polling function * Moved exynos5 PPMU access functions to the devfreq driver Changes since v4: * Fixed compilation errors due to presence of devinit/devexit * Moved exynos ppmu header to the drivers/devfreq/exynos directory drivers/devfreq/Kconfig | 10 + drivers/devfreq/Makefile | 1 + drivers/devfreq/exynos/Makefile | 1 + drivers/devfreq/exynos/exynos5_bus.c | 503 ++++++++++++++++++++++++++++++++++ drivers/devfreq/exynos/exynos_ppmu.c | 56 ++++ drivers/devfreq/exynos/exynos_ppmu.h | 79 ++++++ 6 files changed, 650 insertions(+), 0 deletions(-) create mode 100644 drivers/devfreq/exynos/exynos5_bus.c create mode 100644 drivers/devfreq/exynos/exynos_ppmu.c create mode 100644 drivers/devfreq/exynos/exynos_ppmu.h diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 0f079be..1560d0d 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -78,4 +78,14 @@ config ARM_EXYNOS4_BUS_DEVFREQ To operate with optimal voltages, ASV support is required (CONFIG_EXYNOS_ASV). +config ARM_EXYNOS5_BUS_DEVFREQ + bool "ARM Exynos5250 Bus DEVFREQ Driver" + depends on SOC_EXYNOS5250 + select ARCH_HAS_OPP + select DEVFREQ_GOV_SIMPLE_ONDEMAND + help + This adds the DEVFREQ driver for Exynos5250 bus interface (vdd_int). + It reads PPMU counters of memory controllers and adjusts the + operating frequencies and voltages with OPP support. + endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 3bc1fef..16138c9 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o # DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos/ +obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos/ diff --git a/drivers/devfreq/exynos/Makefile b/drivers/devfreq/exynos/Makefile index 1498823..bfaaf5b 100644 --- a/drivers/devfreq/exynos/Makefile +++ b/drivers/devfreq/exynos/Makefile @@ -1,2 +1,3 @@ # Exynos DEVFREQ Drivers obj-$(CONFIG_ARM_EXYNOS4_BUS_DEVFREQ) += exynos4_bus.o +obj-$(CONFIG_ARM_EXYNOS5_BUS_DEVFREQ) += exynos_ppmu.o exynos5_bus.o diff --git a/drivers/devfreq/exynos/exynos5_bus.c b/drivers/devfreq/exynos/exynos5_bus.c new file mode 100644 index 0000000..574b16b --- /dev/null +++ b/drivers/devfreq/exynos/exynos5_bus.c @@ -0,0 +1,503 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS5 INT clock frequency scaling support using DEVFREQ framework + * Based on work done by Jonghwan Choi <jhbird.choi@samsung.com> + * Support for only EXYNOS5250 is present. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#include <linux/module.h> +#include <linux/devfreq.h> +#include <linux/io.h> +#include <linux/opp.h> +#include <linux/slab.h> +#include <linux/suspend.h> +#include <linux/opp.h> +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/platform_device.h> +#include <linux/pm_qos.h> +#include <linux/regulator/consumer.h> +#include <linux/of_address.h> +#include <linux/of_platform.h> + +#include "exynos_ppmu.h" + +#define MAX_SAFEVOLT 1100000 /* 1.10V */ +/* Assume that the bus is saturated if the utilization is 25% */ +#define INT_BUS_SATURATION_RATIO 25 + +enum int_level_idx { + LV_0, + LV_1, + LV_2, + LV_3, + LV_4, + _LV_END +}; + +enum exynos_ppmu_list { + PPMU_RIGHT, + PPMU_END, +}; + +struct busfreq_data_int { + struct device *dev; + struct devfreq *devfreq; + struct regulator *vdd_int; + struct exynos_ppmu ppmu[PPMU_END]; + unsigned long curr_freq; + bool disabled; + + struct notifier_block pm_notifier; + struct mutex lock; + struct pm_qos_request int_req; + struct clk *int_clk; +}; + +struct int_bus_opp_table { + unsigned int idx; + unsigned long clk; + unsigned long volt; +}; + +static struct int_bus_opp_table exynos5_int_opp_table[] = { + {LV_0, 266000, 1025000}, + {LV_1, 200000, 1025000}, + {LV_2, 160000, 1025000}, + {LV_3, 133000, 1025000}, + {LV_4, 100000, 1025000}, + {0, 0, 0}, +}; + +static void busfreq_mon_reset(struct busfreq_data_int *data) +{ + unsigned int i; + + for (i = PPMU_RIGHT; i < PPMU_END; i++) { + void __iomem *ppmu_base = data->ppmu[i].hw_base; + + /* Reset the performance and cycle counters */ + exynos_ppmu_reset(ppmu_base); + + /* Setup count registers to monitor read/write transactions */ + data->ppmu[i].event[PPMU_PMNCNT3] = RDWR_DATA_COUNT; + exynos_ppmu_setevent(ppmu_base, PPMU_PMNCNT3, + data->ppmu[i].event[PPMU_PMNCNT3]); + + exynos_ppmu_start(ppmu_base); + } +} + +static void exynos5_read_ppmu(struct busfreq_data_int *data) +{ + int i, j; + + for (i = PPMU_RIGHT; i < PPMU_END; i++) { + void __iomem *ppmu_base = data->ppmu[i].hw_base; + + exynos_ppmu_stop(ppmu_base); + + /* Update local data from PPMU */ + data->ppmu[i].ccnt = __raw_readl(ppmu_base + PPMU_CCNT); + + for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) { + if (data->ppmu[i].event[j] == 0) + data->ppmu[i].count[j] = 0; + else + data->ppmu[i].count[j] = + exynos_ppmu_read(ppmu_base, j); + } + } + + busfreq_mon_reset(data); +} + +static int exynos5_int_setvolt(struct busfreq_data_int *data, + unsigned long volt) +{ + return regulator_set_voltage(data->vdd_int, volt, MAX_SAFEVOLT); +} + +static int exynos5_busfreq_int_target(struct device *dev, unsigned long *_freq, + u32 flags) +{ + int err = 0; + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + struct opp *opp; + unsigned long old_freq, freq; + unsigned long volt; + + rcu_read_lock(); + opp = devfreq_recommended_opp(dev, _freq, flags); + if (IS_ERR(opp)) { + rcu_read_unlock(); + dev_err(dev, "%s: Invalid OPP.\n", __func__); + return PTR_ERR(opp); + } + + freq = opp_get_freq(opp); + volt = opp_get_voltage(opp); + rcu_read_unlock(); + + old_freq = data->curr_freq; + + if (old_freq == freq) + return 0; + + dev_dbg(dev, "targetting %lukHz %luuV\n", freq, volt); + + mutex_lock(&data->lock); + + if (data->disabled) + goto out; + + if (freq > exynos5_int_opp_table[0].clk) + pm_qos_update_request(&data->int_req, freq * 16 / 1000); + else + pm_qos_update_request(&data->int_req, -1); + + if (old_freq < freq) + err = exynos5_int_setvolt(data, volt); + if (err) + goto out; + + err = clk_set_rate(data->int_clk, freq * 1000); + + if (err) + goto out; + + if (old_freq > freq) + err = exynos5_int_setvolt(data, volt); + if (err) + goto out; + + data->curr_freq = freq; +out: + mutex_unlock(&data->lock); + return err; +} + +static int exynos5_get_busier_dmc(struct busfreq_data_int *data) +{ + int i, j; + int busy = 0; + unsigned int temp = 0; + + for (i = PPMU_RIGHT; i < PPMU_END; i++) { + for (j = PPMU_PMNCNT0; j < PPMU_PMNCNT_MAX; j++) { + if (data->ppmu[i].count[j] > temp) { + temp = data->ppmu[i].count[j]; + busy = i; + } + } + } + + return busy; +} + +static int exynos5_int_get_dev_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + int busier_dmc; + + exynos5_read_ppmu(data); + busier_dmc = exynos5_get_busier_dmc(data); + + stat->current_frequency = data->curr_freq; + + /* Number of cycles spent on memory access */ + stat->busy_time = data->ppmu[busier_dmc].count[PPMU_PMNCNT3]; + stat->busy_time *= 100 / INT_BUS_SATURATION_RATIO; + stat->total_time = data->ppmu[busier_dmc].ccnt; + + return 0; +} +static void exynos5_int_exit(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + devfreq_unregister_opp_notifier(dev, data->devfreq); +} + +static struct devfreq_dev_profile exynos5_devfreq_int_profile = { + .initial_freq = 160000, + .polling_ms = 100, + .target = exynos5_busfreq_int_target, + .get_dev_status = exynos5_int_get_dev_status, + .exit = exynos5_int_exit, +}; + +static int exynos5250_init_int_tables(struct busfreq_data_int *data) +{ + int i, err = 0; + + for (i = LV_0; i < _LV_END; i++) { + err = opp_add(data->dev, exynos5_int_opp_table[i].clk, + exynos5_int_opp_table[i].volt); + if (err) { + dev_err(data->dev, "Cannot add opp entries.\n"); + return err; + } + } + + return 0; +} + +static int exynos5_busfreq_int_pm_notifier_event(struct notifier_block *this, + unsigned long event, void *ptr) +{ + struct busfreq_data_int *data = container_of(this, + struct busfreq_data_int, pm_notifier); + struct opp *opp; + unsigned long maxfreq = ULONG_MAX; + unsigned long freq; + unsigned long volt; + int err = 0; + + switch (event) { + case PM_SUSPEND_PREPARE: + /* Set Fastest and Deactivate DVFS */ + mutex_lock(&data->lock); + + data->disabled = true; + + rcu_read_lock(); + opp = opp_find_freq_floor(data->dev, &maxfreq); + if (IS_ERR(opp)) { + rcu_read_unlock(); + err = PTR_ERR(opp); + goto unlock; + } + freq = opp_get_freq(opp); + volt = opp_get_voltage(opp); + rcu_read_unlock(); + + err = exynos5_int_setvolt(data, volt); + if (err) + goto unlock; + + err = clk_set_rate(data->int_clk, freq * 1000); + + if (err) + goto unlock; + + data->curr_freq = freq; +unlock: + mutex_unlock(&data->lock); + if (err) + return NOTIFY_BAD; + return NOTIFY_OK; + case PM_POST_RESTORE: + case PM_POST_SUSPEND: + /* Reactivate */ + mutex_lock(&data->lock); + data->disabled = false; + mutex_unlock(&data->lock); + return NOTIFY_OK; + } + + return NOTIFY_DONE; +} + +static int exynos5_busfreq_int_probe(struct platform_device *pdev) +{ + struct busfreq_data_int *data; + struct opp *opp; + struct device *dev = &pdev->dev; + struct device_node *np; + unsigned long initial_freq; + unsigned long initial_volt; + int err = 0; + int i; + + data = devm_kzalloc(&pdev->dev, sizeof(struct busfreq_data_int), + GFP_KERNEL); + if (data == NULL) { + dev_err(dev, "Cannot allocate memory.\n"); + return -ENOMEM; + } + + np = of_find_compatible_node(NULL, NULL, "samsung,exynos5250-ppmu"); + if (np == NULL) { + pr_err("Unable to find PPMU node\n"); + return -ENOENT; + } + + for (i = PPMU_RIGHT; i < PPMU_END; i++) { + /* map PPMU memory region */ + data->ppmu[i].hw_base = of_iomap(np, i); + if (data->ppmu[i].hw_base == NULL) { + dev_err(&pdev->dev, "failed to map memory region\n"); + return -ENOMEM; + } + } + data->pm_notifier.notifier_call = exynos5_busfreq_int_pm_notifier_event; + data->dev = dev; + mutex_init(&data->lock); + + err = exynos5250_init_int_tables(data); + if (err) + goto err_regulator; + + data->vdd_int = regulator_get(dev, "vdd_int"); + if (IS_ERR(data->vdd_int)) { + dev_err(dev, "Cannot get the regulator \"vdd_int\"\n"); + err = PTR_ERR(data->vdd_int); + goto err_regulator; + } + + data->int_clk = clk_get(dev, "int_clk"); + if (IS_ERR(data->int_clk)) { + dev_err(dev, "Cannot get clock \"int_clk\"\n"); + err = PTR_ERR(data->int_clk); + goto err_clock; + } + + rcu_read_lock(); + opp = opp_find_freq_floor(dev, + &exynos5_devfreq_int_profile.initial_freq); + if (IS_ERR(opp)) { + rcu_read_unlock(); + dev_err(dev, "Invalid initial frequency %lu kHz.\n", + exynos5_devfreq_int_profile.initial_freq); + err = PTR_ERR(opp); + goto err_opp_add; + } + initial_freq = opp_get_freq(opp); + initial_volt = opp_get_voltage(opp); + rcu_read_unlock(); + data->curr_freq = initial_freq; + + err = clk_set_rate(data->int_clk, initial_freq * 1000); + if (err) { + dev_err(dev, "Failed to set initial frequency\n"); + goto err_opp_add; + } + + err = exynos5_int_setvolt(data, initial_volt); + if (err) + goto err_opp_add; + + platform_set_drvdata(pdev, data); + + busfreq_mon_reset(data); + + data->devfreq = devfreq_add_device(dev, &exynos5_devfreq_int_profile, + "simple_ondemand", NULL); + + if (IS_ERR(data->devfreq)) { + err = PTR_ERR(data->devfreq); + goto err_devfreq_add; + } + + devfreq_register_opp_notifier(dev, data->devfreq); + + err = register_pm_notifier(&data->pm_notifier); + if (err) { + dev_err(dev, "Failed to setup pm notifier\n"); + goto err_devfreq_add; + } + + /* TODO: Add a new QOS class for int/mif bus */ + pm_qos_add_request(&data->int_req, PM_QOS_NETWORK_THROUGHPUT, -1); + + return 0; + +err_devfreq_add: + devfreq_remove_device(data->devfreq); + platform_set_drvdata(pdev, NULL); +err_opp_add: + clk_put(data->int_clk); +err_clock: + regulator_put(data->vdd_int); +err_regulator: + return err; +} + +static int exynos5_busfreq_int_remove(struct platform_device *pdev) +{ + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + pm_qos_remove_request(&data->int_req); + unregister_pm_notifier(&data->pm_notifier); + devfreq_remove_device(data->devfreq); + regulator_put(data->vdd_int); + clk_put(data->int_clk); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static int exynos5_busfreq_int_resume(struct device *dev) +{ + struct platform_device *pdev = container_of(dev, struct platform_device, + dev); + struct busfreq_data_int *data = platform_get_drvdata(pdev); + + busfreq_mon_reset(data); + return 0; +} + +static const struct dev_pm_ops exynos5_busfreq_int_pm = { + .resume = exynos5_busfreq_int_resume, +}; + +/* platform device pointer for exynos5 devfreq device. */ +static struct platform_device *exynos5_devfreq_pdev; + +static struct platform_driver exynos5_busfreq_int_driver = { + .probe = exynos5_busfreq_int_probe, + .remove = exynos5_busfreq_int_remove, + .driver = { + .name = "exynos5-bus-int", + .owner = THIS_MODULE, + .pm = &exynos5_busfreq_int_pm, + }, +}; + +static int __init exynos5_busfreq_int_init(void) +{ + int ret; + + ret = platform_driver_register(&exynos5_busfreq_int_driver); + if (ret < 0) + goto out; + + exynos5_devfreq_pdev = + platform_device_register_simple("exynos5-bus-int", -1, NULL, 0); + if (IS_ERR_OR_NULL(exynos5_devfreq_pdev)) { + ret = PTR_ERR(exynos5_devfreq_pdev); + goto out1; + } + + return 0; +out1: + platform_driver_unregister(&exynos5_busfreq_int_driver); +out: + return ret; +} +late_initcall(exynos5_busfreq_int_init); + +static void __exit exynos5_busfreq_int_exit(void) +{ + platform_device_unregister(exynos5_devfreq_pdev); + platform_driver_unregister(&exynos5_busfreq_int_driver); +} +module_exit(exynos5_busfreq_int_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("EXYNOS5 busfreq driver with devfreq framework"); diff --git a/drivers/devfreq/exynos/exynos_ppmu.c b/drivers/devfreq/exynos/exynos_ppmu.c new file mode 100644 index 0000000..85fc5ac --- /dev/null +++ b/drivers/devfreq/exynos/exynos_ppmu.c @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS - PPMU support + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/types.h> +#include <linux/io.h> + +#include "exynos_ppmu.h" + +void exynos_ppmu_reset(void __iomem *ppmu_base) +{ + __raw_writel(PPMU_CYCLE_RESET | PPMU_COUNTER_RESET, ppmu_base); + __raw_writel(PPMU_ENABLE_CYCLE | + PPMU_ENABLE_COUNT0 | + PPMU_ENABLE_COUNT1 | + PPMU_ENABLE_COUNT2 | + PPMU_ENABLE_COUNT3, + ppmu_base + PPMU_CNTENS); +} + +void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch, + unsigned int evt) +{ + __raw_writel(evt, ppmu_base + PPMU_BEVTSEL(ch)); +} + +void exynos_ppmu_start(void __iomem *ppmu_base) +{ + __raw_writel(PPMU_ENABLE, ppmu_base); +} + +void exynos_ppmu_stop(void __iomem *ppmu_base) +{ + __raw_writel(PPMU_DISABLE, ppmu_base); +} + +unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch) +{ + unsigned int total; + + if (ch == PPMU_PMNCNT3) + total = ((__raw_readl(ppmu_base + PMCNT_OFFSET(ch)) << 8) | + __raw_readl(ppmu_base + PMCNT_OFFSET(ch + 1))); + else + total = __raw_readl(ppmu_base + PMCNT_OFFSET(ch)); + + return total; +} diff --git a/drivers/devfreq/exynos/exynos_ppmu.h b/drivers/devfreq/exynos/exynos_ppmu.h new file mode 100644 index 0000000..b46d31b --- /dev/null +++ b/drivers/devfreq/exynos/exynos_ppmu.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com/ + * + * EXYNOS PPMU header + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __DEVFREQ_EXYNOS_PPMU_H +#define __DEVFREQ_EXYNOS_PPMU_H __FILE__ + +#include <linux/ktime.h> + +/* For PPMU Control */ +#define PPMU_ENABLE BIT(0) +#define PPMU_DISABLE 0x0 +#define PPMU_CYCLE_RESET BIT(1) +#define PPMU_COUNTER_RESET BIT(2) + +#define PPMU_ENABLE_COUNT0 BIT(0) +#define PPMU_ENABLE_COUNT1 BIT(1) +#define PPMU_ENABLE_COUNT2 BIT(2) +#define PPMU_ENABLE_COUNT3 BIT(3) +#define PPMU_ENABLE_CYCLE BIT(31) + +#define PPMU_CNTENS 0x10 +#define PPMU_FLAG 0x50 +#define PPMU_CCNT_OVERFLOW BIT(31) +#define PPMU_CCNT 0x100 + +#define PPMU_PMCNT0 0x110 +#define PPMU_PMCNT_OFFSET 0x10 +#define PMCNT_OFFSET(x) (PPMU_PMCNT0 + (PPMU_PMCNT_OFFSET * x)) + +#define PPMU_BEVT0SEL 0x1000 +#define PPMU_BEVTSEL_OFFSET 0x100 +#define PPMU_BEVTSEL(x) (PPMU_BEVT0SEL + (ch * PPMU_BEVTSEL_OFFSET)) + +/* For Event Selection */ +#define RD_DATA_COUNT 0x5 +#define WR_DATA_COUNT 0x6 +#define RDWR_DATA_COUNT 0x7 + +enum ppmu_counter { + PPMU_PMNCNT0, + PPMU_PMCCNT1, + PPMU_PMNCNT2, + PPMU_PMNCNT3, + PPMU_PMNCNT_MAX, +}; + +struct bus_opp_table { + unsigned int idx; + unsigned long clk; + unsigned long volt; +}; + +struct exynos_ppmu { + void __iomem *hw_base; + unsigned int ccnt; + unsigned int event[PPMU_PMNCNT_MAX]; + unsigned int count[PPMU_PMNCNT_MAX]; + unsigned long long ns; + ktime_t reset_time; + bool ccnt_overflow; + bool count_overflow[PPMU_PMNCNT_MAX]; +}; + +void exynos_ppmu_reset(void __iomem *ppmu_base); +void exynos_ppmu_setevent(void __iomem *ppmu_base, unsigned int ch, + unsigned int evt); +void exynos_ppmu_start(void __iomem *ppmu_base); +void exynos_ppmu_stop(void __iomem *ppmu_base); +unsigned int exynos_ppmu_read(void __iomem *ppmu_base, unsigned int ch); +#endif /* __DEVFREQ_EXYNOS_PPMU_H */ + -- 1.7.8.6 ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v5 4/4] PM: Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 2013-02-04 12:14 ` [PATCH v5 " Abhilash Kesavan @ 2013-02-05 9:56 ` MyungJoo Ham 0 siblings, 0 replies; 18+ messages in thread From: MyungJoo Ham @ 2013-02-05 9:56 UTC (permalink / raw) To: Abhilash Kesavan; +Cc: linux-kernel, linux-pm, Jonghwan Choi, Kukjin Kim On Mon, Feb 4, 2013 at 9:14 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote: > Exynos5-bus device devfreq driver monitors PPMU counters and > adjusts operating frequencies and voltages with OPP. ASV should > be used to provide appropriate voltages as per the speed group > of the SoC rather than using a constant 1.025V. applied. thanks. ps. Devfreq patches are stacking up at devfreq's for-rafael branch and will be pull-requested for 3.9 soon. > > Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> > Cc: Jonghwan Choi <jhbird.choi@samsung.com> > Cc: Kukjin Kim <kgene.kim@samsung.com> > --- > Changes since RFC v1: > * Moved the Exynos5 PPMU driver to machine specific directory > * Migrated to the PM QOS framework > Changes since v2: > * Moved the PPMU driver to drivers/devfreq/exynos > * Fixed whitespace, commenting, empty lines in PPMU driver > Changes since v3: > * Removed the custom devfreq monitor and PPMU polling function > * Moved exynos5 PPMU access functions to the devfreq driver > Changes since v4: > * Fixed compilation errors due to presence of devinit/devexit > * Moved exynos ppmu header to the drivers/devfreq/exynos directory > -- MyungJoo Ham, Ph.D. Mobile Software Platform Lab, DMC Business, Samsung Electronics ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support 2013-01-09 12:06 [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support Abhilash Kesavan ` (2 preceding siblings ...) 2013-01-09 12:06 ` [PATCH 4/4] PM/Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 Abhilash Kesavan @ 2013-01-14 14:26 ` MyungJoo Ham 2013-01-18 13:23 ` [PATCH v4 " Abhilash Kesavan 4 siblings, 0 replies; 18+ messages in thread From: MyungJoo Ham @ 2013-01-14 14:26 UTC (permalink / raw) To: Abhilash Kesavan Cc: linux-kernel, linux-pm, kgene.kim, kyungmin.park, rjw, jhbird.choi On Wed, Jan 9, 2013 at 9:06 PM, Abhilash Kesavan <a.kesavan@samsung.com> wrote: > PPMU is required by the devfreq driver. Add a device tree > node for it. > > Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> > Cc: Jonghwan Choi <jhbird.choi@samsung.com> > Cc: Kukjin Kim <kgene.kim@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> > --- > .../bindings/arm/exynos/ppmu-exynos5.txt | 28 ++++++++++++++++++++ > arch/arm/boot/dts/exynos5250.dtsi | 9 ++++++ > 2 files changed, 37 insertions(+), 0 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt > > diff --git a/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt > new file mode 100644 > index 0000000..a424dfa > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt > @@ -0,0 +1,28 @@ > +Exynos5 PPMU driver > +------------------- > + > +Performance events are primitive values used to get performance data. These > +events provide information about the behavior of the SoC that can be used > +when analyzing system performance. These events are made visible using the > +PPMU logic. > +Exynos5 PPMU driver is used by the exynos5 devfreq driver to control the bus > +frequency/voltage. > + > +Required properties: > +- compatible: should be one of the following. > + * samsung,exynos5-ppmu - for exynos5250 type ppmu. > +- reg: > + * physical base address of the PPMUs (DDR, Right Bus and CPU) and > + length of memory mapped region. > + > +Example: > +-------- > + > + ppmu { > + compatible = "samsung,exynos5250-ppmu"; > + reg = <0x10C40000 0x2000 > + 0x10C50000 0x2000 > + 0x10C60000 0x2000 > + 0x10CB0000 0x2000 > + 0x13660000 0x2000>; > + }; > diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi > index 30485de..d504cba 100644 > --- a/arch/arm/boot/dts/exynos5250.dtsi > +++ b/arch/arm/boot/dts/exynos5250.dtsi > @@ -732,4 +732,13 @@ > interrupt-parent = <&combiner>; > interrupts = <24 1>; > }; > + > + ppmu { > + compatible = "samsung,exynos5250-ppmu"; > + reg = <0x10C40000 0x2000 /* PPMU_DDR_C */ > + 0x10C50000 0x2000 /* PPMU_DDR_R1 */ > + 0x10CB0000 0x2000 /* PPMU_DDR_L */ > + 0x13660000 0x2000 /* PPMU_DDR_RIGHT */ > + 0x10C60000 0x2000>; /* PPMU_DDR_CPU */ > + }; > }; > -- > 1.7.8.6 > > -- > To unsubscribe from this list: send the line "unsubscribe linux-pm" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- MyungJoo Ham, Ph.D. Mobile Software Platform Lab, DMC Business, Samsung Electronics ^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v4 1/4] ARM: EXYNOS5: Add PPMU device tree support 2013-01-09 12:06 [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support Abhilash Kesavan ` (3 preceding siblings ...) 2013-01-14 14:26 ` [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support MyungJoo Ham @ 2013-01-18 13:23 ` Abhilash Kesavan 4 siblings, 0 replies; 18+ messages in thread From: Abhilash Kesavan @ 2013-01-18 13:23 UTC (permalink / raw) To: myungjoo.ham, linux-kernel, linux-pm, kgene.kim Cc: kyungmin.park, rjw, jhbird.choi PPMU is required by the devfreq driver. Add a device tree node for it. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Cc: Jonghwan Choi <jhbird.choi@samsung.com> Cc: Kukjin Kim <kgene.kim@samsung.com> --- Changes since v3: * Modified the dt bindings as per updated devfreq driver Changes before v3: * No change Tested after merging for-rafael branch of git://git.kernel.org/pub/scm/linux/kernel/git/mzx/devfreq.git with for-next branch of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git .../bindings/arm/exynos/ppmu-exynos5.txt | 24 ++++++++++++++++++++ arch/arm/boot/dts/exynos5250.dtsi | 5 ++++ 2 files changed, 29 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt diff --git a/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt new file mode 100644 index 0000000..06d40d5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/exynos/ppmu-exynos5.txt @@ -0,0 +1,24 @@ +Exynos5 PPMU driver +------------------- + +Performance events are primitive values used to get performance data. These +events provide information about the behavior of the SoC that can be used +when analyzing system performance. These events are made visible using the +PPMU logic. +Exynos5 PPMU driver is used by the exynos5 devfreq driver to control the bus +frequency/voltage. + +Required properties: +- compatible: should be one of the following. + * samsung,exynos5-ppmu - for exynos5250 type ppmu. +- reg: + * physical base address of the Right PPMU and length of memory mapped + region + +Example: +-------- + + ppmu { + compatible = "samsung,exynos5250-ppmu"; + reg = <0x13660000 0x2000>; + }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 30485de..96ef6ed 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -732,4 +732,9 @@ interrupt-parent = <&combiner>; interrupts = <24 1>; }; + + ppmu { + compatible = "samsung,exynos5250-ppmu"; + reg = <0x13660000 0x2000>; /* PPMU_DDR_RIGHT */ + }; }; -- 1.7.8.6 ^ permalink raw reply related [flat|nested] 18+ messages in thread
end of thread, other threads:[~2013-02-05 9:56 UTC | newest] Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2013-01-09 12:06 [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support Abhilash Kesavan 2013-01-09 12:06 ` [PATCH 2/4] ARM: EXYNOS5: Support Exynos5-bus devfreq driver Abhilash Kesavan 2013-01-14 14:29 ` MyungJoo Ham 2013-01-18 13:23 ` [PATCH v4 " Abhilash Kesavan 2013-01-09 12:06 ` [PATCH 3/4] PM: DEVFREQ: Move exynos4 devfreq driver into a new sub-directory Abhilash Kesavan 2013-01-14 14:30 ` MyungJoo Ham 2013-01-18 13:24 ` [PATCH v4 " Abhilash Kesavan 2013-01-09 12:06 ` [PATCH 4/4] PM/Devfreq: Add Exynos5-bus devfreq driver for Exynos5250 Abhilash Kesavan 2013-01-09 14:14 ` Rajagopal Venkat 2013-01-18 13:22 ` Abhilash Kesavan 2013-01-18 13:24 ` [PATCH v4 4/4] PM: Devfreq: " Abhilash Kesavan 2013-02-03 15:47 ` Abhilash Kesavan 2013-02-04 6:41 ` myungjoo.ham 2013-02-04 8:03 ` Abhilash Kesavan 2013-02-04 12:14 ` [PATCH v5 " Abhilash Kesavan 2013-02-05 9:56 ` MyungJoo Ham 2013-01-14 14:26 ` [PATCH 1/4] ARM: EXYNOS5: Add PPMU device tree support MyungJoo Ham 2013-01-18 13:23 ` [PATCH v4 " Abhilash Kesavan
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