* [PATCH v4 0/2] arm64: qcom: add initial support for qcom sa8775p-ride
@ 2023-02-14 9:27 Bartosz Golaszewski
2023-02-14 9:27 ` [PATCH v4 1/2] dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform Bartosz Golaszewski
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Bartosz Golaszewski @ 2023-02-14 9:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio,
Manivannan Sadhasivam, Jassi Brar, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, linux-kernel, devicetree, Bartosz Golaszewski
From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Bjorn,
I'm resending this because it's been discussed with Qualcomm that we need to
drop the watchdog node from the DT. Please don't apply the previous version.
I've also dropped the patches you already have in your tree so these are the
two remaining.
v3 -> v4:
- drop the watchdog node from DT
- drop the watchdog dt-bindings patch
- drop the patches already in Bjorn's tree
- collect tags
v2 -> v3:
- reorder properties (reg always first, etc.)
- tweak node names
- remove properties filled in by the firmware
v1 -> v2:
- lots of improvements all around the place to make the dts pass dtbs_check
(with some additional patches fixing bugs in existing dt bindings),
make dtbs W=1 and checkpatch.pl
- move board-specific properties to the board .dts file
- ordered top-level nodes alphabetically and sub-nodes by the reg property
- fixed licensing
- set #address-cells and #size-cells to <2> in the soc node and update sub-nodes
Bartosz Golaszewski (2):
dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform
arm64: dts: qcom: add initial support for qcom sa8775p-ride
.../bindings/mailbox/qcom-ipcc.yaml | 1 +
arch/arm64/boot/dts/qcom/Makefile | 1 +
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 47 +
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 805 ++++++++++++++++++
4 files changed, 854 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts
create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi
--
2.37.2
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v4 1/2] dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform 2023-02-14 9:27 [PATCH v4 0/2] arm64: qcom: add initial support for qcom sa8775p-ride Bartosz Golaszewski @ 2023-02-14 9:27 ` Bartosz Golaszewski 2023-02-14 9:27 ` [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride Bartosz Golaszewski 2023-03-15 23:34 ` (subset) [PATCH v4 0/2] arm64: " Bjorn Andersson 2 siblings, 0 replies; 8+ messages in thread From: Bartosz Golaszewski @ 2023-02-14 9:27 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam, Jassi Brar, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, linux-kernel, devicetree, Bartosz Golaszewski, Krzysztof Kozlowski From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Add a compatible for the ipcc on sa8775p platforms. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index f5c73437fef4..de56640cecca 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -24,6 +24,7 @@ properties: compatible: items: - enum: + - qcom,sa8775p-ipcc - qcom,sc7280-ipcc - qcom,sc8280xp-ipcc - qcom,sm6350-ipcc -- 2.37.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride 2023-02-14 9:27 [PATCH v4 0/2] arm64: qcom: add initial support for qcom sa8775p-ride Bartosz Golaszewski 2023-02-14 9:27 ` [PATCH v4 1/2] dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform Bartosz Golaszewski @ 2023-02-14 9:27 ` Bartosz Golaszewski 2023-03-06 13:26 ` Bartosz Golaszewski 2023-03-14 6:25 ` Shazad Hussain 2023-03-15 23:34 ` (subset) [PATCH v4 0/2] arm64: " Bjorn Andersson 2 siblings, 2 replies; 8+ messages in thread From: Bartosz Golaszewski @ 2023-02-14 9:27 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam, Jassi Brar, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, linux-kernel, devicetree, Bartosz Golaszewski From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> This adds basic support for the Qualcomm sa8775p platform and the reference board: sa8775p-ride. The dt files describe the basics of the SoC and enable booting to shell. Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 47 ++ arch/arm64/boot/dts/qcom/sa8775p.dtsi | 805 ++++++++++++++++++++++ 3 files changed, 853 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 31aa54f0428c..b63cd1861e68 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts new file mode 100644 index 000000000000..3adf7349f4e5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include "sa8775p.dtsi" + +/ { + model = "Qualcomm SA8775P Ride"; + compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; + + aliases { + serial0 = &uart10; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32764>; +}; + +&tlmm { + qup_uart10_default: qup-uart10-state { + pins = "gpio46", "gpio47"; + function = "qup1_se3"; + }; +}; + +&uart10 { + compatible = "qcom,geni-debug-uart"; + pinctrl-0 = <&qup_uart10_default>; + pinctrl-names = "default"; + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi new file mode 100644 index 000000000000..565c1376073e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -0,0 +1,805 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sa8775p-gcc.h> +#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@10000 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10000>; + enable-method = "psci"; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + L3_1: l3-cache { + compatible = "cache"; + }; + + }; + }; + + CPU5: cpu@10100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10100>; + enable-method = "psci"; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + }; + }; + + CPU6: cpu@10200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10200>; + enable-method = "psci"; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + }; + }; + + CPU7: cpu@10300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x10300>; + enable-method = "psci"; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + + core3 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm { + compatible = "qcom,scm-sa8775p", "qcom,scm"; + }; + }; + + aggre1_noc: interconnect-aggre1-noc { + compatible = "qcom,sa8775p-aggre1-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre2_noc: interconnect-aggre2-noc { + compatible = "qcom,sa8775p-aggre2-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + clk_virt: interconnect-clk-virt { + compatible = "qcom,sa8775p-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + config_noc: interconnect-config-noc { + compatible = "qcom,sa8775p-config-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + dc_noc: interconnect-dc-noc { + compatible = "qcom,sa8775p-dc-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gem_noc: interconnect-gem-noc { + compatible = "qcom,sa8775p-gem-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + gpdsp_anoc: interconnect-gpdsp-anoc { + compatible = "qcom,sa8775p-gpdsp-anoc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect-lpass-ag-noc { + compatible = "qcom,sa8775p-lpass-ag-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sa8775p-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mmss_noc: interconnect-mmss-noc { + compatible = "qcom,sa8775p-mmss-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspa_noc: interconnect-nspa-noc { + compatible = "qcom,sa8775p-nspa-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + nspb_noc: interconnect-nspb-noc { + compatible = "qcom,sa8775p-nspb-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + pcie_anoc: interconnect-pcie-anoc { + compatible = "qcom,sa8775p-pcie-anoc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + system_noc: interconnect-system-noc { + compatible = "qcom,sa8775p-system-noc"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + /* Will be updated by the bootloader. */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x0>; + }; + + qup_opp_table_100mhz: opp-table-qup100mhz { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + sail_ss_mem: sail-ss@80000000 { + reg = <0x0 0x80000000 0x0 0x10000000>; + no-map; + }; + + hyp_mem: hyp@90000000 { + reg = <0x0 0x90000000 0x0 0x600000>; + no-map; + }; + + xbl_boot_mem: xbl-boot@90600000 { + reg = <0x0 0x90600000 0x0 0x200000>; + no-map; + }; + + aop_image_mem: aop-image@90800000 { + reg = <0x0 0x90800000 0x0 0x60000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@90860000 { + compatible = "qcom,cmd-db"; + reg = <0x0 0x90860000 0x0 0x20000>; + no-map; + }; + + uefi_log: uefi-log@908b0000 { + reg = <0x0 0x908b0000 0x0 0x10000>; + no-map; + }; + + reserved_mem: reserved@908f0000 { + reg = <0x0 0x908f0000 0x0 0xf000>; + no-map; + }; + + secdata_apss_mem: secdata-apss@908ff000 { + reg = <0x0 0x908ff000 0x0 0x1000>; + no-map; + }; + + smem_mem: smem@90900000 { + compatible = "qcom,smem"; + reg = <0x0 0x90900000 0x0 0x200000>; + no-map; + hwlocks = <&tcsr_mutex 3>; + }; + + cpucp_fw_mem: cpucp-fw@90b00000 { + reg = <0x0 0x90b00000 0x0 0x100000>; + no-map; + }; + + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { + reg = <0x0 0x93b00000 0x0 0xf00000>; + no-map; + }; + + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { + reg = <0x0 0x94a00000 0x0 0x800000>; + no-map; + }; + + pil_camera_mem: pil-camera@95200000 { + reg = <0x0 0x95200000 0x0 0x500000>; + no-map; + }; + + pil_adsp_mem: pil-adsp@95c00000 { + reg = <0x0 0x95c00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp0_mem: pil-gdsp0@97b00000 { + reg = <0x0 0x97b00000 0x0 0x1e00000>; + no-map; + }; + + pil_gdsp1_mem: pil-gdsp1@99900000 { + reg = <0x0 0x99900000 0x0 0x1e00000>; + no-map; + }; + + pil_cdsp0_mem: pil-cdsp0@9b800000 { + reg = <0x0 0x9b800000 0x0 0x1e00000>; + no-map; + }; + + pil_gpu_mem: pil-gpu@9d600000 { + reg = <0x0 0x9d600000 0x0 0x2000>; + no-map; + }; + + pil_cdsp1_mem: pil-cdsp1@9d700000 { + reg = <0x0 0x9d700000 0x0 0x1e00000>; + no-map; + }; + + pil_cvp_mem: pil-cvp@9f500000 { + reg = <0x0 0x9f500000 0x0 0x700000>; + no-map; + }; + + pil_video_mem: pil-video@9fc00000 { + reg = <0x0 0x9fc00000 0x0 0x700000>; + no-map; + }; + + hyptz_reserved_mem: hyptz-reserved@beb00000 { + reg = <0x0 0xbeb00000 0x0 0x11500000>; + no-map; + }; + + tz_stat_mem: tz-stat@d0000000 { + reg = <0x0 0xd0000000 0x0 0x100000>; + no-map; + }; + + tags_mem: tags@d0100000 { + reg = <0x0 0xd0100000 0x0 0x1200000>; + no-map; + }; + + qtee_mem: qtee@d1300000 { + reg = <0x0 0xd1300000 0x0 0x500000>; + no-map; + }; + + trusted_apps_mem: trusted-apps@d1800000 { + reg = <0x0 0xd1800000 0x0 0x3900000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,sa8775p-gcc"; + reg = <0x0 0x100000 0x0 0xc7018>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd SA8775P_CX>; + }; + + ipcc: mailbox@408000 { + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; + reg = <0x0 0x408000 0x0 0x1000>; + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xac0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x443 0x0>; + status = "disabled"; + + uart10: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0xa8c000 0x0 0x4000>; + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 + &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 + &config_noc SLAVE_QUP_1 0>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + }; + + memtimer: timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + ranges = <0x0 0x0 0x0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17c21000 { + reg = <0x17c21000 0x1000>, + <0x17c22000 0x1000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <0>; + }; + + frame@17c23000 { + reg = <0x17c23000 0x1000>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <1>; + status = "disabled"; + }; + + frame@17c25000 { + reg = <0x17c25000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <2>; + status = "disabled"; + }; + + frame@17c27000 { + reg = <0x17c27000 0x1000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <3>; + status = "disabled"; + }; + + frame@17c29000 { + reg = <0x17c29000 0x1000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <4>; + status = "disabled"; + }; + + frame@17c2b000 { + reg = <0x17c2b000 0x1000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <5>; + status = "disabled"; + }; + + frame@17c2d000 { + reg = <0x17c2d000 0x1000>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + frame-number = <6>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 2>, + <SLEEP_TCS 3>, + <WAKE_TCS 3>, + <CONTROL_TCS 0>; + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sa8775p-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board_clk>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sa8775p-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-0 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp-1 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp-4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp-5 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp-6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp-7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp-8 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp-9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x1f40000 0x0 0x20000>; + #hwlock-cells = <1>; + }; + + tlmm: pinctrl@f000000 { + compatible = "qcom,sa8775p-tlmm"; + reg = <0x0 0xf000000 0x0 0x1000000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 149>; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0x0 0x15000000 0x0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- 2.37.2 ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride 2023-02-14 9:27 ` [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride Bartosz Golaszewski @ 2023-03-06 13:26 ` Bartosz Golaszewski 2023-03-14 6:25 ` Shazad Hussain 1 sibling, 0 replies; 8+ messages in thread From: Bartosz Golaszewski @ 2023-03-06 13:26 UTC (permalink / raw) To: Bjorn Andersson Cc: linux-arm-msm, Andy Gross, Jassi Brar, linux-kernel, devicetree, Bartosz Golaszewski, Manivannan Sadhasivam, Krzysztof Kozlowski, Rob Herring, Konrad Dybcio On Tue, Feb 14, 2023 at 10:27 AM Bartosz Golaszewski <brgl@bgdev.pl> wrote: > > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > This adds basic support for the Qualcomm sa8775p platform and the > reference board: sa8775p-ride. The dt files describe the basics of the > SoC and enable booting to shell. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- Bjorn, Now that the merge window is closed, could you pick this up into your tree? Thanks, Bartosz ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride 2023-02-14 9:27 ` [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride Bartosz Golaszewski 2023-03-06 13:26 ` Bartosz Golaszewski @ 2023-03-14 6:25 ` Shazad Hussain 2023-03-14 8:19 ` Bartosz Golaszewski 1 sibling, 1 reply; 8+ messages in thread From: Shazad Hussain @ 2023-03-14 6:25 UTC (permalink / raw) To: Bartosz Golaszewski, Andy Gross, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam, Jassi Brar, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, linux-kernel, devicetree, Bartosz Golaszewski On 2/14/2023 2:57 PM, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > This adds basic support for the Qualcomm sa8775p platform and the > reference board: sa8775p-ride. The dt files describe the basics of the > SoC and enable booting to shell. > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 47 ++ > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 805 ++++++++++++++++++++++ > 3 files changed, 853 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts > create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index 31aa54f0428c..b63cd1861e68 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb > +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb > dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb > dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb > dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > new file mode 100644 > index 000000000000..3adf7349f4e5 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > @@ -0,0 +1,47 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2023, Linaro Limited > + */ > + > +/dts-v1/; > + > +#include "sa8775p.dtsi" > + > +/ { > + model = "Qualcomm SA8775P Ride"; > + compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; > + > + aliases { > + serial0 = &uart10; > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > +}; > + > +&qupv3_id_1 { > + status = "okay"; > +}; > + > +&sleep_clk { > + clock-frequency = <32764>; > +}; > + > +&tlmm { > + qup_uart10_default: qup-uart10-state { > + pins = "gpio46", "gpio47"; > + function = "qup1_se3"; > + }; > +}; Can we keep &tlmm at the end ? As this would be expanding. -Shazad > + > +&uart10 { > + compatible = "qcom,geni-debug-uart"; > + pinctrl-0 = <&qup_uart10_default>; > + pinctrl-names = "default"; > + status = "okay"; > +}; > + > +&xo_board_clk { > + clock-frequency = <38400000>; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > new file mode 100644 > index 000000000000..565c1376073e > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -0,0 +1,805 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2023, Linaro Limited > + */ > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/qcom,rpmh.h> > +#include <dt-bindings/clock/qcom,sa8775p-gcc.h> > +#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> > +#include <dt-bindings/power/qcom-rpmpd.h> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h> > + > +/ { > + interrupt-parent = <&intc>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + > + clocks { > + xo_board_clk: xo-board-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + > + sleep_clk: sleep-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; > + }; > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + CPU0: cpu@0 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x0>; > + enable-method = "psci"; > + next-level-cache = <&L2_0>; > + L2_0: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + L3_0: l3-cache { > + compatible = "cache"; > + }; > + }; > + }; > + > + CPU1: cpu@100 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x100>; > + enable-method = "psci"; > + next-level-cache = <&L2_1>; > + L2_1: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU2: cpu@200 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x200>; > + enable-method = "psci"; > + next-level-cache = <&L2_2>; > + L2_2: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU3: cpu@300 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x300>; > + enable-method = "psci"; > + next-level-cache = <&L2_3>; > + L2_3: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_0>; > + }; > + }; > + > + CPU4: cpu@10000 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10000>; > + enable-method = "psci"; > + next-level-cache = <&L2_4>; > + L2_4: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + L3_1: l3-cache { > + compatible = "cache"; > + }; > + > + }; > + }; > + > + CPU5: cpu@10100 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10100>; > + enable-method = "psci"; > + next-level-cache = <&L2_5>; > + L2_5: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + }; > + }; > + > + CPU6: cpu@10200 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10200>; > + enable-method = "psci"; > + next-level-cache = <&L2_6>; > + L2_6: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + }; > + }; > + > + CPU7: cpu@10300 { > + device_type = "cpu"; > + compatible = "qcom,kryo"; > + reg = <0x0 0x10300>; > + enable-method = "psci"; > + next-level-cache = <&L2_7>; > + L2_7: l2-cache { > + compatible = "cache"; > + next-level-cache = <&L3_1>; > + }; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&CPU0>; > + }; > + > + core1 { > + cpu = <&CPU1>; > + }; > + > + core2 { > + cpu = <&CPU2>; > + }; > + > + core3 { > + cpu = <&CPU3>; > + }; > + }; > + > + cluster1 { > + core0 { > + cpu = <&CPU4>; > + }; > + > + core1 { > + cpu = <&CPU5>; > + }; > + > + core2 { > + cpu = <&CPU6>; > + }; > + > + core3 { > + cpu = <&CPU7>; > + }; > + }; > + }; > + }; > + > + firmware { > + scm { > + compatible = "qcom,scm-sa8775p", "qcom,scm"; > + }; > + }; > + > + aggre1_noc: interconnect-aggre1-noc { > + compatible = "qcom,sa8775p-aggre1-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + aggre2_noc: interconnect-aggre2-noc { > + compatible = "qcom,sa8775p-aggre2-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + clk_virt: interconnect-clk-virt { > + compatible = "qcom,sa8775p-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + config_noc: interconnect-config-noc { > + compatible = "qcom,sa8775p-config-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + dc_noc: interconnect-dc-noc { > + compatible = "qcom,sa8775p-dc-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + gem_noc: interconnect-gem-noc { > + compatible = "qcom,sa8775p-gem-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + gpdsp_anoc: interconnect-gpdsp-anoc { > + compatible = "qcom,sa8775p-gpdsp-anoc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + lpass_ag_noc: interconnect-lpass-ag-noc { > + compatible = "qcom,sa8775p-lpass-ag-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mc_virt: interconnect-mc-virt { > + compatible = "qcom,sa8775p-mc-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mmss_noc: interconnect-mmss-noc { > + compatible = "qcom,sa8775p-mmss-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + nspa_noc: interconnect-nspa-noc { > + compatible = "qcom,sa8775p-nspa-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + nspb_noc: interconnect-nspb-noc { > + compatible = "qcom,sa8775p-nspb-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + pcie_anoc: interconnect-pcie-anoc { > + compatible = "qcom,sa8775p-pcie-anoc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + system_noc: interconnect-system-noc { > + compatible = "qcom,sa8775p-system-noc"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + /* Will be updated by the bootloader. */ > + memory@80000000 { > + device_type = "memory"; > + reg = <0x0 0x80000000 0x0 0x0>; > + }; > + > + qup_opp_table_100mhz: opp-table-qup100mhz { > + compatible = "operating-points-v2"; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + > + psci { > + compatible = "arm,psci-1.0"; > + method = "smc"; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + sail_ss_mem: sail-ss@80000000 { > + reg = <0x0 0x80000000 0x0 0x10000000>; > + no-map; > + }; > + > + hyp_mem: hyp@90000000 { > + reg = <0x0 0x90000000 0x0 0x600000>; > + no-map; > + }; > + > + xbl_boot_mem: xbl-boot@90600000 { > + reg = <0x0 0x90600000 0x0 0x200000>; > + no-map; > + }; > + > + aop_image_mem: aop-image@90800000 { > + reg = <0x0 0x90800000 0x0 0x60000>; > + no-map; > + }; > + > + aop_cmd_db_mem: aop-cmd-db@90860000 { > + compatible = "qcom,cmd-db"; > + reg = <0x0 0x90860000 0x0 0x20000>; > + no-map; > + }; > + > + uefi_log: uefi-log@908b0000 { > + reg = <0x0 0x908b0000 0x0 0x10000>; > + no-map; > + }; > + > + reserved_mem: reserved@908f0000 { > + reg = <0x0 0x908f0000 0x0 0xf000>; > + no-map; > + }; > + > + secdata_apss_mem: secdata-apss@908ff000 { > + reg = <0x0 0x908ff000 0x0 0x1000>; > + no-map; > + }; > + > + smem_mem: smem@90900000 { > + compatible = "qcom,smem"; > + reg = <0x0 0x90900000 0x0 0x200000>; > + no-map; > + hwlocks = <&tcsr_mutex 3>; > + }; > + > + cpucp_fw_mem: cpucp-fw@90b00000 { > + reg = <0x0 0x90b00000 0x0 0x100000>; > + no-map; > + }; > + > + lpass_machine_learning_mem: lpass-machine-learning@93b00000 { > + reg = <0x0 0x93b00000 0x0 0xf00000>; > + no-map; > + }; > + > + adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 { > + reg = <0x0 0x94a00000 0x0 0x800000>; > + no-map; > + }; > + > + pil_camera_mem: pil-camera@95200000 { > + reg = <0x0 0x95200000 0x0 0x500000>; > + no-map; > + }; > + > + pil_adsp_mem: pil-adsp@95c00000 { > + reg = <0x0 0x95c00000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_gdsp0_mem: pil-gdsp0@97b00000 { > + reg = <0x0 0x97b00000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_gdsp1_mem: pil-gdsp1@99900000 { > + reg = <0x0 0x99900000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_cdsp0_mem: pil-cdsp0@9b800000 { > + reg = <0x0 0x9b800000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_gpu_mem: pil-gpu@9d600000 { > + reg = <0x0 0x9d600000 0x0 0x2000>; > + no-map; > + }; > + > + pil_cdsp1_mem: pil-cdsp1@9d700000 { > + reg = <0x0 0x9d700000 0x0 0x1e00000>; > + no-map; > + }; > + > + pil_cvp_mem: pil-cvp@9f500000 { > + reg = <0x0 0x9f500000 0x0 0x700000>; > + no-map; > + }; > + > + pil_video_mem: pil-video@9fc00000 { > + reg = <0x0 0x9fc00000 0x0 0x700000>; > + no-map; > + }; > + > + hyptz_reserved_mem: hyptz-reserved@beb00000 { > + reg = <0x0 0xbeb00000 0x0 0x11500000>; > + no-map; > + }; > + > + tz_stat_mem: tz-stat@d0000000 { > + reg = <0x0 0xd0000000 0x0 0x100000>; > + no-map; > + }; > + > + tags_mem: tags@d0100000 { > + reg = <0x0 0xd0100000 0x0 0x1200000>; > + no-map; > + }; > + > + qtee_mem: qtee@d1300000 { > + reg = <0x0 0xd1300000 0x0 0x500000>; > + no-map; > + }; > + > + trusted_apps_mem: trusted-apps@d1800000 { > + reg = <0x0 0xd1800000 0x0 0x3900000>; > + no-map; > + }; > + }; > + > + soc: soc@0 { > + compatible = "simple-bus"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges = <0 0 0 0 0x10 0>; > + > + gcc: clock-controller@100000 { > + compatible = "qcom,sa8775p-gcc"; > + reg = <0x0 0x100000 0x0 0xc7018>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&sleep_clk>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>; > + power-domains = <&rpmhpd SA8775P_CX>; > + }; > + > + ipcc: mailbox@408000 { > + compatible = "qcom,sa8775p-ipcc", "qcom,ipcc"; > + reg = <0x0 0x408000 0x0 0x1000>; > + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <3>; > + #mbox-cells = <2>; > + }; > + > + qupv3_id_1: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0x0 0xac0000 0x0 0x6000>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + clock-names = "m-ahb", "s-ahb"; > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + iommus = <&apps_smmu 0x443 0x0>; > + status = "disabled"; > + > + uart10: serial@a8c000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0xa8c000 0x0 0x4000>; > + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > + clock-names = "se"; > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + interconnect-names = "qup-core", "qup-config"; > + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 > + &clk_virt SLAVE_QUP_CORE_1 0>, > + <&gem_noc MASTER_APPSS_PROC 0 > + &config_noc SLAVE_QUP_1 0>; > + power-domains = <&rpmhpd SA8775P_CX>; > + operating-points-v2 = <&qup_opp_table_100mhz>; > + status = "disabled"; > + }; > + }; > + > + intc: interrupt-controller@17a00000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ > + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ > + interrupt-controller; > + #interrupt-cells = <3>; > + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x20000>; > + }; > + > + memtimer: timer@17c20000 { > + compatible = "arm,armv7-timer-mem"; > + reg = <0x0 0x17c20000 0x0 0x1000>; > + ranges = <0x0 0x0 0x0 0x20000000>; > + #address-cells = <1>; > + #size-cells = <1>; > + > + frame@17c21000 { > + reg = <0x17c21000 0x1000>, > + <0x17c22000 0x1000>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <0>; > + }; > + > + frame@17c23000 { > + reg = <0x17c23000 0x1000>; > + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <1>; > + status = "disabled"; > + }; > + > + frame@17c25000 { > + reg = <0x17c25000 0x1000>; > + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <2>; > + status = "disabled"; > + }; > + > + frame@17c27000 { > + reg = <0x17c27000 0x1000>; > + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <3>; > + status = "disabled"; > + }; > + > + frame@17c29000 { > + reg = <0x17c29000 0x1000>; > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <4>; > + status = "disabled"; > + }; > + > + frame@17c2b000 { > + reg = <0x17c2b000 0x1000>; > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <5>; > + status = "disabled"; > + }; > + > + frame@17c2d000 { > + reg = <0x17c2d000 0x1000>; > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; > + frame-number = <6>; > + status = "disabled"; > + }; > + }; > + > + apps_rsc: rsc@18200000 { > + compatible = "qcom,rpmh-rsc"; > + reg = <0x0 0x18200000 0x0 0x10000>, > + <0x0 0x18210000 0x0 0x10000>, > + <0x0 0x18220000 0x0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = <ACTIVE_TCS 2>, > + <SLEEP_TCS 3>, > + <WAKE_TCS 3>, > + <CONTROL_TCS 0>; > + label = "apps_rsc"; > + > + apps_bcm_voter: bcm-voter { > + compatible = "qcom,bcm-voter"; > + }; > + > + rpmhcc: clock-controller { > + compatible = "qcom,sa8775p-rpmh-clk"; > + #clock-cells = <1>; > + clock-names = "xo"; > + clocks = <&xo_board_clk>; > + }; > + > + rpmhpd: power-controller { > + compatible = "qcom,sa8775p-rpmhpd"; > + #power-domain-cells = <1>; > + operating-points-v2 = <&rpmhpd_opp_table>; > + > + rpmhpd_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + rpmhpd_opp_ret: opp-0 { > + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; > + }; > + > + rpmhpd_opp_min_svs: opp-1 { > + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; > + }; > + > + rpmhpd_opp_low_svs: opp2 { > + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; > + }; > + > + rpmhpd_opp_svs: opp3 { > + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; > + }; > + > + rpmhpd_opp_svs_l1: opp-4 { > + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; > + }; > + > + rpmhpd_opp_nom: opp-5 { > + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; > + }; > + > + rpmhpd_opp_nom_l1: opp-6 { > + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; > + }; > + > + rpmhpd_opp_nom_l2: opp-7 { > + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; > + }; > + > + rpmhpd_opp_turbo: opp-8 { > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; > + }; > + > + rpmhpd_opp_turbo_l1: opp-9 { > + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; > + }; > + }; > + }; > + }; > + > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0x0 0x1f40000 0x0 0x20000>; > + #hwlock-cells = <1>; > + }; > + > + tlmm: pinctrl@f000000 { > + compatible = "qcom,sa8775p-tlmm"; > + reg = <0x0 0xf000000 0x0 0x1000000>; > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + gpio-controller; > + #gpio-cells = <2>; > + interrupt-controller; > + #interrupt-cells = <2>; > + gpio-ranges = <&tlmm 0 0 149>; > + }; > + > + apps_smmu: iommu@15000000 { > + compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500"; > + reg = <0x0 0x15000000 0x0 0x100000>; > + #iommu-cells = <2>; > + #global-interrupts = <2>; > + > + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>; > + }; > + }; > + > + arch_timer: timer { > + compatible = "arm,armv8-timer"; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, > + <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; > + }; > +}; ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride 2023-03-14 6:25 ` Shazad Hussain @ 2023-03-14 8:19 ` Bartosz Golaszewski 2023-03-14 9:30 ` Shazad Hussain 0 siblings, 1 reply; 8+ messages in thread From: Bartosz Golaszewski @ 2023-03-14 8:19 UTC (permalink / raw) To: Shazad Hussain Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam, Jassi Brar, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-kernel, devicetree, Bartosz Golaszewski On Tue, Mar 14, 2023 at 7:26 AM Shazad Hussain <quic_shazhuss@quicinc.com> wrote: > > > > On 2/14/2023 2:57 PM, Bartosz Golaszewski wrote: > > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > > > This adds basic support for the Qualcomm sa8775p platform and the > > reference board: sa8775p-ride. The dt files describe the basics of the > > SoC and enable booting to shell. > > > > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/Makefile | 1 + > > arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 47 ++ > > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 805 ++++++++++++++++++++++ > > 3 files changed, 853 insertions(+) > > create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts > > create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi > > > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > > index 31aa54f0428c..b63cd1861e68 100644 > > --- a/arch/arm64/boot/dts/qcom/Makefile > > +++ b/arch/arm64/boot/dts/qcom/Makefile > > @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb > > dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb > > dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb > > dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb > > +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb > > dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb > > dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb > > dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > > new file mode 100644 > > index 000000000000..3adf7349f4e5 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts > > @@ -0,0 +1,47 @@ > > +// SPDX-License-Identifier: BSD-3-Clause > > +/* > > + * Copyright (c) 2023, Linaro Limited > > + */ > > + > > +/dts-v1/; > > + > > +#include "sa8775p.dtsi" > > + > > +/ { > > + model = "Qualcomm SA8775P Ride"; > > + compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; > > + > > + aliases { > > + serial0 = &uart10; > > + }; > > + > > + chosen { > > + stdout-path = "serial0:115200n8"; > > + }; > > +}; > > + > > +&qupv3_id_1 { > > + status = "okay"; > > +}; > > + > > +&sleep_clk { > > + clock-frequency = <32764>; > > +}; > > + > > +&tlmm { > > + qup_uart10_default: qup-uart10-state { > > + pins = "gpio46", "gpio47"; > > + function = "qup1_se3"; > > + }; > > +}; > > Can we keep &tlmm at the end ? As this would be expanding. > The overridden nodes are ordered alphabetically. Why would expanding them be a reason to put it at the end? Bart [...] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride 2023-03-14 8:19 ` Bartosz Golaszewski @ 2023-03-14 9:30 ` Shazad Hussain 0 siblings, 0 replies; 8+ messages in thread From: Shazad Hussain @ 2023-03-14 9:30 UTC (permalink / raw) To: Bartosz Golaszewski Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Manivannan Sadhasivam, Jassi Brar, Rob Herring, Krzysztof Kozlowski, linux-arm-msm, linux-kernel, devicetree, Bartosz Golaszewski On 3/14/2023 1:49 PM, Bartosz Golaszewski wrote: > On Tue, Mar 14, 2023 at 7:26 AM Shazad Hussain > <quic_shazhuss@quicinc.com> wrote: >> >> >> >> On 2/14/2023 2:57 PM, Bartosz Golaszewski wrote: >>> From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >>> >>> This adds basic support for the Qualcomm sa8775p platform and the >>> reference board: sa8775p-ride. The dt files describe the basics of the >>> SoC and enable booting to shell. >>> >>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> >>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> >>> --- >>> arch/arm64/boot/dts/qcom/Makefile | 1 + >>> arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 47 ++ >>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 805 ++++++++++++++++++++++ >>> 3 files changed, 853 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/qcom/sa8775p-ride.dts >>> create mode 100644 arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile >>> index 31aa54f0428c..b63cd1861e68 100644 >>> --- a/arch/arm64/boot/dts/qcom/Makefile >>> +++ b/arch/arm64/boot/dts/qcom/Makefile >>> @@ -75,6 +75,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb >>> +dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb >>> dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb >>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts >>> new file mode 100644 >>> index 000000000000..3adf7349f4e5 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts >>> @@ -0,0 +1,47 @@ >>> +// SPDX-License-Identifier: BSD-3-Clause >>> +/* >>> + * Copyright (c) 2023, Linaro Limited >>> + */ >>> + >>> +/dts-v1/; >>> + >>> +#include "sa8775p.dtsi" >>> + >>> +/ { >>> + model = "Qualcomm SA8775P Ride"; >>> + compatible = "qcom,sa8775p-ride", "qcom,sa8775p"; >>> + >>> + aliases { >>> + serial0 = &uart10; >>> + }; >>> + >>> + chosen { >>> + stdout-path = "serial0:115200n8"; >>> + }; >>> +}; >>> + >>> +&qupv3_id_1 { >>> + status = "okay"; >>> +}; >>> + >>> +&sleep_clk { >>> + clock-frequency = <32764>; >>> +}; >>> + >>> +&tlmm { >>> + qup_uart10_default: qup-uart10-state { >>> + pins = "gpio46", "gpio47"; >>> + function = "qup1_se3"; >>> + }; >>> +}; >> >> Can we keep &tlmm at the end ? As this would be expanding. >> > > The overridden nodes are ordered alphabetically. Why would expanding > them be a reason to put it at the end? > > Bart > I agree that it follows alphabetically, but typically the pin configuration node go last after /* PINCTRL */ delimiter as this particular section tends to become long. -Shazad > [...] ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: (subset) [PATCH v4 0/2] arm64: qcom: add initial support for qcom sa8775p-ride 2023-02-14 9:27 [PATCH v4 0/2] arm64: qcom: add initial support for qcom sa8775p-ride Bartosz Golaszewski 2023-02-14 9:27 ` [PATCH v4 1/2] dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform Bartosz Golaszewski 2023-02-14 9:27 ` [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride Bartosz Golaszewski @ 2023-03-15 23:34 ` Bjorn Andersson 2 siblings, 0 replies; 8+ messages in thread From: Bjorn Andersson @ 2023-03-15 23:34 UTC (permalink / raw) To: Jassi Brar, Krzysztof Kozlowski, Rob Herring, Konrad Dybcio, Bartosz Golaszewski, Manivannan Sadhasivam, Andy Gross Cc: Bartosz Golaszewski, devicetree, linux-arm-msm, linux-kernel On Tue, 14 Feb 2023 10:27:11 +0100, Bartosz Golaszewski wrote: > From: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> > > Bjorn, > > I'm resending this because it's been discussed with Qualcomm that we need to > drop the watchdog node from the DT. Please don't apply the previous version. > > [...] Applied, thanks! [2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride commit: 603f96d4c9d0cb42f934fb0b99440bb9e8ba4385 Best regards, -- Bjorn Andersson <andersson@kernel.org> ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-03-15 23:32 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-02-14 9:27 [PATCH v4 0/2] arm64: qcom: add initial support for qcom sa8775p-ride Bartosz Golaszewski 2023-02-14 9:27 ` [PATCH v4 1/2] dt-bindings: mailbox: qcom-ipcc: document the sa8775p platform Bartosz Golaszewski 2023-02-14 9:27 ` [PATCH v4 2/2] arm64: dts: qcom: add initial support for qcom sa8775p-ride Bartosz Golaszewski 2023-03-06 13:26 ` Bartosz Golaszewski 2023-03-14 6:25 ` Shazad Hussain 2023-03-14 8:19 ` Bartosz Golaszewski 2023-03-14 9:30 ` Shazad Hussain 2023-03-15 23:34 ` (subset) [PATCH v4 0/2] arm64: " Bjorn Andersson
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