[PATCH v4 0/8] enable usb support on rk356x

[PATCH v4 0/8] enable usb support on rk356x

[Peter Geis]

Good Morning,

This is my patch series that I have maintained out of tree until the
combophy driver landed.

Patch 1 fixes the grf dt binding from the combophy merge.
Patch 2 adds the dt bindings for the grf changes necessary.
Patch 3 adds the SoC specific binding.
Patch 4 adds support to the grf driver to set the rk3566 otg clock
source.
Patch 5 is a downstream patch ported forward to shut down the usb3 clock
when the controller is operating in usb2 mode.
Patch 6 adds the dwc3 nodes to the rk356x device tree includes.
Patch 7 enables the dwc3 nodes on the Quartz64 Model A.
Patch 8 enables the dwc3 nodes on the rk3568-evb.

Note, there are functional changes from previous versions.

Please review and apply.

Very Respectfully,
Peter Geis

Changelog:
v4:
- Add SoC specific binding, fall back to core.
 
v3:
- Drop the dwc-of-simple method in favor of using dwc core.
- Drop all quirks except snps,dis_u2_susphy_quirk, which is necessary to
  prevent device detection failures in some states.
- Drop the reset-names.

v2:
- Add a dt-bindings fix for grf.yaml
- Unify the reset names.
- Constrain the force usb2 clock dwc3 patch to only supported variants of
the ip.
- Change dwc3-of-simple to support of-match-data.
- Drop the PCLK-PIPE clk.
- Rename the usb nodes to be more friendly.
- Add the rk3568-evb enable patch.

Bin Yang (1):
  usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode

Michael Riesch (2):
  dt-bindings: usb: add rk3568 compatible to rockchip, dwc3
  arm64: dts: rockchip: add usb3 support to rk3568-evb1-v10

Peter Geis (5):
  dt-bindings: soc: grf: fix rk3568 usb definitions
  dt-bindings: soc: grf: add rk3566-pipe-grf compatible
  soc: rockchip: set dwc3 clock for rk3566
  arm64: dts: rockchip: add rk356x dwc3 usb3 nodes
  arm64: dts: rockchip: enable dwc3 on quartz64-a

 .../devicetree/bindings/soc/rockchip/grf.yaml |  5 +-
 .../bindings/usb/rockchip,dwc3.yaml           |  2 +
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 37 +++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3566.dtsi      | 11 +++++
 .../boot/dts/rockchip/rk3568-evb1-v10.dts     | 46 +++++++++++++++++++
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |  9 ++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 35 +++++++++++++-
 drivers/soc/rockchip/grf.c                    | 17 +++++++
 drivers/usb/dwc3/core.c                       |  5 ++
 drivers/usb/dwc3/core.h                       |  1 +
 10 files changed, 165 insertions(+), 3 deletions(-)

-- 
2.25.1

[PATCH v4 1/8] dt-bindings: soc: grf: fix rk3568 usb definitions

[Peter Geis]

The rockchip,rk3568-pipe-grf and rockchip,rk3568-pipe-phy-grf
compatibles were incorrectly assigned to the syscon, simple-mfd
enumeration, vice only the syscon enumeration.
This leads a dtbs_check failure.

Move these to the syscon enumeration.

Fixes: b3df807e1fb0 ("dt-bindings: soc: grf: add naneng combo phy register compatible")

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 072318fcd57b..5079e9d24af6 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -15,6 +15,8 @@ properties:
       - items:
           - enum:
               - rockchip,rk3288-sgrf
+              - rockchip,rk3568-pipe-grf
+              - rockchip,rk3568-pipe-phy-grf
               - rockchip,rk3568-usb2phy-grf
               - rockchip,rv1108-usbgrf
           - const: syscon
@@ -39,8 +41,6 @@ properties:
               - rockchip,rk3399-grf
               - rockchip,rk3399-pmugrf
               - rockchip,rk3568-grf
-              - rockchip,rk3568-pipe-grf
-              - rockchip,rk3568-pipe-phy-grf
               - rockchip,rk3568-pmugrf
               - rockchip,rv1108-grf
               - rockchip,rv1108-pmugrf
-- 
2.25.1

[PATCH v4 2/8] dt-bindings: soc: grf: add rk3566-pipe-grf compatible

[Peter Geis]

The rk3566 requires special handling for the dwc3-otg clock in order for
the port to function correctly.
Add a binding for the rk3566-pipe-grf so we can handle setup with the
grf driver.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
index 5079e9d24af6..75a2b8bb25fb 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
@@ -15,6 +15,7 @@ properties:
       - items:
           - enum:
               - rockchip,rk3288-sgrf
+              - rockchip,rk3566-pipe-grf
               - rockchip,rk3568-pipe-grf
               - rockchip,rk3568-pipe-phy-grf
               - rockchip,rk3568-usb2phy-grf
-- 
2.25.1

[PATCH v4 3/8] dt-bindings: usb: add rk3568 compatible to rockchip, dwc3

[Peter Geis]

From: Michael Riesch <michael.riesch@wolfvision.net>

Add the compatible for the Rockchip RK3568 variant.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
 Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
index 04077f2d7faf..b3798d94d2fd 100644
--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
@@ -30,6 +30,7 @@ select:
         enum:
           - rockchip,rk3328-dwc3
           - rockchip,rk3399-dwc3
+          - rockchip,rk3568-dwc3
   required:
     - compatible
 
@@ -39,6 +40,7 @@ properties:
       - enum:
           - rockchip,rk3328-dwc3
           - rockchip,rk3399-dwc3
+          - rockchip,rk3568-dwc3
       - const: snps,dwc3
 
   reg:
-- 
2.25.1

[PATCH v4 4/8] soc: rockchip: set dwc3 clock for rk3566

[Peter Geis]

The rk3566 dwc3 otg port clock is unavailable at boot, as it defaults to
the combophy as the clock source. As combophy0 doesn't exist on rk3566,
we need to set the clock source to the usb2 phy instead.

Add handling to the grf driver to handle this on boot.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 drivers/soc/rockchip/grf.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c
index 494cf2b5bf7b..384461b70684 100644
--- a/drivers/soc/rockchip/grf.c
+++ b/drivers/soc/rockchip/grf.c
@@ -108,6 +108,20 @@ static const struct rockchip_grf_info rk3399_grf __initconst = {
 	.num_values = ARRAY_SIZE(rk3399_defaults),
 };
 
+#define RK3566_GRF_USB3OTG0_CON1	0x0104
+
+static const struct rockchip_grf_value rk3566_defaults[] __initconst = {
+	{ "usb3otg port switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(0, 1, 12) },
+	{ "usb3otg clock switch", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 7) },
+	{ "usb3otg disable usb3", RK3566_GRF_USB3OTG0_CON1, HIWORD_UPDATE(1, 1, 0) },
+};
+
+static const struct rockchip_grf_info rk3566_pipegrf __initconst = {
+	.values = rk3566_defaults,
+	.num_values = ARRAY_SIZE(rk3566_defaults),
+};
+
+
 static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
 	{
 		.compatible = "rockchip,rk3036-grf",
@@ -130,6 +144,9 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = {
 	}, {
 		.compatible = "rockchip,rk3399-grf",
 		.data = (void *)&rk3399_grf,
+	}, {
+		.compatible = "rockchip,rk3566-pipe-grf",
+		.data = (void *)&rk3566_pipegrf,
 	},
 	{ /* sentinel */ },
 };
-- 
2.25.1

[PATCH v4 5/8] usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode

[Peter Geis]

From: Bin Yang <yangbin@rock-chips.com>

In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.

Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 drivers/usb/dwc3/core.c | 5 +++++
 drivers/usb/dwc3/core.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 18adddfba3da..416d83a055fe 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1167,6 +1167,11 @@ static int dwc3_core_init(struct dwc3 *dwc)
 		if (dwc->parkmode_disable_ss_quirk)
 			reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
 
+		if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
+		    (dwc->maximum_speed == USB_SPEED_HIGH ||
+		     dwc->maximum_speed == USB_SPEED_FULL))
+			reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
+
 		dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 	}
 
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index eb9c1efced05..ea3ca04406bb 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -259,6 +259,7 @@
 /* Global User Control 1 Register */
 #define DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT	BIT(31)
 #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS	BIT(28)
+#define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK	BIT(26)
 #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW		BIT(24)
 #define DWC3_GUCTL1_PARKMODE_DISABLE_SS		BIT(17)
 
-- 
2.25.1

[PATCH v4 6/8] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes

[Peter Geis]

Add the dwc3 device nodes to the rk356x device trees.
The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable
dwc3 host controller.
The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable
dwc3 host controller.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566.dtsi | 11 ++++++++
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  9 ++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 35 +++++++++++++++++++++++-
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
index 3839eef5e4f7..0b957068ff89 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
@@ -6,6 +6,10 @@ / {
 	compatible = "rockchip,rk3566";
 };
 
+&pipegrf {
+	compatible = "rockchip,rk3566-pipe-grf", "syscon";
+};
+
 &power {
 	power-domain@RK3568_PD_PIPE {
 		reg = <RK3568_PD_PIPE>;
@@ -18,3 +22,10 @@ power-domain@RK3568_PD_PIPE {
 		#power-domain-cells = <0>;
 	};
 };
+
+&usb_host0_xhci {
+	phys = <&usb2phy0_otg>;
+	phy-names = "usb2-phy";
+	extcon = <&usb2phy0>;
+	maximum-speed = "high-speed";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 5b0f528d6818..8ba9334f9753 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -99,6 +99,10 @@ opp-1992000000 {
 	};
 };
 
+&pipegrf {
+	compatible = "rockchip,rk3568-pipe-grf", "syscon";
+};
+
 &power {
 	power-domain@RK3568_PD_PIPE {
 		reg = <RK3568_PD_PIPE>;
@@ -114,3 +118,8 @@ power-domain@RK3568_PD_PIPE {
 		#power-domain-cells = <0>;
 	};
 };
+
+&usb_host0_xhci {
+	phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>;
+	phy-names = "usb2-phy", "usb3-phy";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7cdef800cb3c..ca20d7b91fe5 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -230,6 +230,40 @@ scmi_shmem: sram@0 {
 		};
 	};
 
+	usb_host0_xhci: usb@fcc00000 {
+		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+		reg = <0x0 0xfcc00000 0x0 0x400000>;
+		interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
+			 <&cru ACLK_USB3OTG0>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk";
+		dr_mode = "host";
+		phy_type = "utmi_wide";
+		power-domains = <&power RK3568_PD_PIPE>;
+		resets = <&cru SRST_USB3OTG0>;
+		snps,dis_u2_susphy_quirk;
+		status = "disabled";
+	};
+
+	usb_host1_xhci: usb@fd000000 {
+		compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
+		reg = <0x0 0xfd000000 0x0 0x400000>;
+		interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
+			 <&cru ACLK_USB3OTG1>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk";
+		dr_mode = "host";
+		phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
+		phy-names = "usb2-phy", "usb3-phy";
+		phy_type = "utmi_wide";
+		power-domains = <&power RK3568_PD_PIPE>;
+		resets = <&cru SRST_USB3OTG1>;
+		snps,dis_u2_susphy_quirk;
+		status = "disabled";
+	};
+
 	gic: interrupt-controller@fd400000 {
 		compatible = "arm,gic-v3";
 		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
@@ -297,7 +331,6 @@ pmu_io_domains: io-domains {
 	};
 
 	pipegrf: syscon@fdc50000 {
-		compatible = "rockchip,rk3568-pipe-grf", "syscon";
 		reg = <0x0 0xfdc50000 0x0 0x1000>;
 	};
 
-- 
2.25.1

[PATCH v4 7/8] arm64: dts: rockchip: enable dwc3 on quartz64-a

[Peter Geis]

The quartz64 model a has support for both the dwc3 otg port and the dwc3
host port. Add the otg power supply and dwc3 nodes to the device tree to
enable support for these.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 37 +++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index dd7f4b9b686b..141a433429b5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -151,6 +151,16 @@ vcc5v0_usb20_host: vcc5v0_usb20_host {
 		vin-supply = <&vcc5v0_usb>;
 	};
 
+	vcc5v0_usb20_otg: vcc5v0_usb20_otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
+		regulator-name = "vcc5v0_usb20_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dcdc_boost>;
+	};
+
 	vcc3v3_sd: vcc3v3_sd {
 		compatible = "regulator-fixed";
 		enable-active-low;
@@ -187,6 +197,10 @@ vcc_wl: vcc_wl {
 	};
 };
 
+&combphy1 {
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&vdd_cpu>;
 };
@@ -672,6 +686,29 @@ &usb_host1_ohci {
 	status = "okay";
 };
 
+&usb_host0_xhci {
+	status = "okay";
+};
+
+/* usb3 controller is muxed with sata1 */
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb20_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	phy-supply = <&vcc5v0_usb20_otg>;
+	status = "okay";
+};
+
 &usb2phy1 {
 	status = "okay";
 };
-- 
2.25.1

[PATCH v4 8/8] arm64: dts: rockchip: add usb3 support to rk3568-evb1-v10

[Peter Geis]

From: Michael Riesch <michael.riesch@wolfvision.net>

The Rockchip RK3568 EVB1 features one USB 3.0 device-only
(USB 2.0 OTG) port and one USB 3.0 host-only port.
Activate the USB 3.0 controller nodes and phy nodes in the
device tree.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
---
 .../boot/dts/rockchip/rk3568-evb1-v10.dts     | 46 +++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
index a794a0ea5c70..622be8be9813 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
@@ -103,6 +103,18 @@ vcc5v0_usb_host: vcc5v0-usb-host {
 		vin-supply = <&vcc5v0_usb>;
 	};
 
+	vcc5v0_usb_otg: vcc5v0-usb-otg {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+		regulator-name = "vcc5v0_usb_otg";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v0_usb>;
+	};
+
 	vcc3v3_lcd0_n: vcc3v3-lcd0-n {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc3v3_lcd0_n";
@@ -136,6 +148,14 @@ regulator-state-mem {
 	};
 };
 
+&combphy0 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
 &cpu0 {
 	cpu-supply = <&vdd_cpu>;
 };
@@ -507,6 +527,9 @@ usb {
 		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
 			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
+		vcc5v0_usb_otg_en: vcc5v0_usb_otg_en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
 	};
 };
 
@@ -568,6 +591,11 @@ &usb_host0_ohci {
 	status = "okay";
 };
 
+&usb_host0_xhci {
+	extcon = <&usb2phy0>;
+	status = "okay";
+};
+
 &usb_host1_ehci {
 	status = "okay";
 };
@@ -576,6 +604,24 @@ &usb_host1_ohci {
 	status = "okay";
 };
 
+&usb_host1_xhci {
+	status = "okay";
+};
+
+&usb2phy0 {
+	status = "okay";
+};
+
+&usb2phy0_host {
+	phy-supply = <&vcc5v0_usb_host>;
+	status = "okay";
+};
+
+&usb2phy0_otg {
+	vbus-supply = <&vcc5v0_usb_otg>;
+	status = "okay";
+};
+
 &usb2phy1 {
 	status = "okay";
 };
-- 
2.25.1

Re: [PATCH v4 0/8] enable usb support on rk356x

[Michael Riesch]

Hi Peter,

On 2/28/22 14:56, Peter Geis wrote:
> Good Morning,
> 
> This is my patch series that I have maintained out of tree until the
> combophy driver landed.
> 
> Patch 1 fixes the grf dt binding from the combophy merge.
> Patch 2 adds the dt bindings for the grf changes necessary.
> Patch 3 adds the SoC specific binding.
> Patch 4 adds support to the grf driver to set the rk3566 otg clock
> source.
> Patch 5 is a downstream patch ported forward to shut down the usb3 clock
> when the controller is operating in usb2 mode.
> Patch 6 adds the dwc3 nodes to the rk356x device tree includes.
> Patch 7 enables the dwc3 nodes on the Quartz64 Model A.
> Patch 8 enables the dwc3 nodes on the rk3568-evb.

As far as the RK3568 EVB1 is concerned:

Tested-by: Michael Riesch <michael.riesch@wolfvision.net>

for the v4 of this series.

Thanks and best regards,
Michael

> 
> Note, there are functional changes from previous versions.
> 
> Please review and apply.
> 
> Very Respectfully,
> Peter Geis
> 
> Changelog:
> v4:
> - Add SoC specific binding, fall back to core.
>  
> v3:
> - Drop the dwc-of-simple method in favor of using dwc core.
> - Drop all quirks except snps,dis_u2_susphy_quirk, which is necessary to
>   prevent device detection failures in some states.
> - Drop the reset-names.
> 
> v2:
> - Add a dt-bindings fix for grf.yaml
> - Unify the reset names.
> - Constrain the force usb2 clock dwc3 patch to only supported variants of
> the ip.
> - Change dwc3-of-simple to support of-match-data.
> - Drop the PCLK-PIPE clk.
> - Rename the usb nodes to be more friendly.
> - Add the rk3568-evb enable patch.
> 
> Bin Yang (1):
>   usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode
> 
> Michael Riesch (2):
>   dt-bindings: usb: add rk3568 compatible to rockchip, dwc3
>   arm64: dts: rockchip: add usb3 support to rk3568-evb1-v10
> 
> Peter Geis (5):
>   dt-bindings: soc: grf: fix rk3568 usb definitions
>   dt-bindings: soc: grf: add rk3566-pipe-grf compatible
>   soc: rockchip: set dwc3 clock for rk3566
>   arm64: dts: rockchip: add rk356x dwc3 usb3 nodes
>   arm64: dts: rockchip: enable dwc3 on quartz64-a
> 
>  .../devicetree/bindings/soc/rockchip/grf.yaml |  5 +-
>  .../bindings/usb/rockchip,dwc3.yaml           |  2 +
>  .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 37 +++++++++++++++
>  arch/arm64/boot/dts/rockchip/rk3566.dtsi      | 11 +++++
>  .../boot/dts/rockchip/rk3568-evb1-v10.dts     | 46 +++++++++++++++++++
>  arch/arm64/boot/dts/rockchip/rk3568.dtsi      |  9 ++++
>  arch/arm64/boot/dts/rockchip/rk356x.dtsi      | 35 +++++++++++++-
>  drivers/soc/rockchip/grf.c                    | 17 +++++++
>  drivers/usb/dwc3/core.c                       |  5 ++
>  drivers/usb/dwc3/core.h                       |  1 +
>  10 files changed, 165 insertions(+), 3 deletions(-)
> 

Re: [PATCH v4 1/8] dt-bindings: soc: grf: fix rk3568 usb definitions

[Peter Geis]

Good Morning,

Would it be possible to pull this patch individually, to fix the
current error reported by Rob?

Thanks,
Peter

On Mon, Feb 28, 2022 at 8:57 AM Peter Geis <pgwipeout@gmail.com> wrote:
>
> The rockchip,rk3568-pipe-grf and rockchip,rk3568-pipe-phy-grf
> compatibles were incorrectly assigned to the syscon, simple-mfd
> enumeration, vice only the syscon enumeration.
> This leads a dtbs_check failure.
>
> Move these to the syscon enumeration.
>
> Fixes: b3df807e1fb0 ("dt-bindings: soc: grf: add naneng combo phy register compatible")
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> index 072318fcd57b..5079e9d24af6 100644
> --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> @@ -15,6 +15,8 @@ properties:
>        - items:
>            - enum:
>                - rockchip,rk3288-sgrf
> +              - rockchip,rk3568-pipe-grf
> +              - rockchip,rk3568-pipe-phy-grf
>                - rockchip,rk3568-usb2phy-grf
>                - rockchip,rv1108-usbgrf
>            - const: syscon
> @@ -39,8 +41,6 @@ properties:
>                - rockchip,rk3399-grf
>                - rockchip,rk3399-pmugrf
>                - rockchip,rk3568-grf
> -              - rockchip,rk3568-pipe-grf
> -              - rockchip,rk3568-pipe-phy-grf
>                - rockchip,rk3568-pmugrf
>                - rockchip,rv1108-grf
>                - rockchip,rv1108-pmugrf
> --
> 2.25.1
>

Re: [PATCH v4 1/8] dt-bindings: soc: grf: fix rk3568 usb definitions

[Vinod Koul]

On 01-03-22, 09:52, Peter Geis wrote:
> Good Morning,
> 
> Would it be possible to pull this patch individually, to fix the
> current error reported by Rob?

This does not apply for me on phy-next. What was this based on..?

> 
> Thanks,
> Peter
> 
> On Mon, Feb 28, 2022 at 8:57 AM Peter Geis <pgwipeout@gmail.com> wrote:
> >
> > The rockchip,rk3568-pipe-grf and rockchip,rk3568-pipe-phy-grf
> > compatibles were incorrectly assigned to the syscon, simple-mfd
> > enumeration, vice only the syscon enumeration.
> > This leads a dtbs_check failure.
> >
> > Move these to the syscon enumeration.
> >
> > Fixes: b3df807e1fb0 ("dt-bindings: soc: grf: add naneng combo phy register compatible")
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> >  Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > index 072318fcd57b..5079e9d24af6 100644
> > --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > @@ -15,6 +15,8 @@ properties:
> >        - items:
> >            - enum:
> >                - rockchip,rk3288-sgrf
> > +              - rockchip,rk3568-pipe-grf
> > +              - rockchip,rk3568-pipe-phy-grf
> >                - rockchip,rk3568-usb2phy-grf
> >                - rockchip,rv1108-usbgrf
> >            - const: syscon
> > @@ -39,8 +41,6 @@ properties:
> >                - rockchip,rk3399-grf
> >                - rockchip,rk3399-pmugrf
> >                - rockchip,rk3568-grf
> > -              - rockchip,rk3568-pipe-grf
> > -              - rockchip,rk3568-pipe-phy-grf
> >                - rockchip,rk3568-pmugrf
> >                - rockchip,rv1108-grf
> >                - rockchip,rv1108-pmugrf
> > --
> > 2.25.1
> >

-- 
~Vinod

Re: [PATCH v4 1/8] dt-bindings: soc: grf: fix rk3568 usb definitions

[Peter Geis]

On Wed, Mar 2, 2022 at 3:16 AM Vinod Koul <vkoul@kernel.org> wrote:
>
> On 01-03-22, 09:52, Peter Geis wrote:
> > Good Morning,
> >
> > Would it be possible to pull this patch individually, to fix the
> > current error reported by Rob?
>
> This does not apply for me on phy-next. What was this based on..?

This is based on linux-next, which the applicable patch was accepted on 24 Feb.
The original patch was correct, but it seems a merge error happened
and these two lines were moved into an incorrect location.
This patch corrects that, but I see on the original patch chain you
are discussing reverting and reapplying to fix it.

>
> >
> > Thanks,
> > Peter
> >
> > On Mon, Feb 28, 2022 at 8:57 AM Peter Geis <pgwipeout@gmail.com> wrote:
> > >
> > > The rockchip,rk3568-pipe-grf and rockchip,rk3568-pipe-phy-grf
> > > compatibles were incorrectly assigned to the syscon, simple-mfd
> > > enumeration, vice only the syscon enumeration.
> > > This leads a dtbs_check failure.
> > >
> > > Move these to the syscon enumeration.
> > >
> > > Fixes: b3df807e1fb0 ("dt-bindings: soc: grf: add naneng combo phy register compatible")
> > >
> > > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > > ---
> > >  Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > > index 072318fcd57b..5079e9d24af6 100644
> > > --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > > +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
> > > @@ -15,6 +15,8 @@ properties:
> > >        - items:
> > >            - enum:
> > >                - rockchip,rk3288-sgrf
> > > +              - rockchip,rk3568-pipe-grf
> > > +              - rockchip,rk3568-pipe-phy-grf
> > >                - rockchip,rk3568-usb2phy-grf
> > >                - rockchip,rv1108-usbgrf
> > >            - const: syscon
> > > @@ -39,8 +41,6 @@ properties:
> > >                - rockchip,rk3399-grf
> > >                - rockchip,rk3399-pmugrf
> > >                - rockchip,rk3568-grf
> > > -              - rockchip,rk3568-pipe-grf
> > > -              - rockchip,rk3568-pipe-phy-grf
> > >                - rockchip,rk3568-pmugrf
> > >                - rockchip,rv1108-grf
> > >                - rockchip,rv1108-pmugrf
> > > --
> > > 2.25.1
> > >
>
> --
> ~Vinod

Re: [PATCH v4 1/8] dt-bindings: soc: grf: fix rk3568 usb definitions

[Vinod Koul]

On 02-03-22, 07:18, Peter Geis wrote:
> On Wed, Mar 2, 2022 at 3:16 AM Vinod Koul <vkoul@kernel.org> wrote:
> >
> > On 01-03-22, 09:52, Peter Geis wrote:
> > > Good Morning,
> > >
> > > Would it be possible to pull this patch individually, to fix the
> > > current error reported by Rob?
> >
> > This does not apply for me on phy-next. What was this based on..?
> 
> This is based on linux-next, which the applicable patch was accepted on 24 Feb.
> The original patch was correct, but it seems a merge error happened
> and these two lines were moved into an incorrect location.
> This patch corrects that, but I see on the original patch chain you
> are discussing reverting and reapplying to fix it.

Ok let me revert than so that it is easy for everyone to fix up

Thanks

-- 
~Vinod

Aw: [PATCH v4 6/8] arm64: dts: rockchip: add rk356x dwc3 usb3 nodes

[Frank Wunderlich]

Tested this Series on my rk3568 Bananapi R2 Pro v00

Tested-by: Frank Wunderlich <frank-w@public-files.de>

regards Frank

Re: [PATCH v4 2/8] dt-bindings: soc: grf: add rk3566-pipe-grf compatible

[Rob Herring]

On Mon, 28 Feb 2022 08:56:53 -0500, Peter Geis wrote:
> The rk3566 requires special handling for the dwc3-otg clock in order for
> the port to function correctly.
> Add a binding for the rk3566-pipe-grf so we can handle setup with the
> grf driver.
> 
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
>  Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v4 3/8] dt-bindings: usb: add rk3568 compatible to rockchip, dwc3

[Rob Herring]

On Mon, 28 Feb 2022 08:56:54 -0500, Peter Geis wrote:
> From: Michael Riesch <michael.riesch@wolfvision.net>
> 
> Add the compatible for the Rockchip RK3568 variant.
> 
> Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
> ---
>  Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml | 2 ++
>  1 file changed, 2 insertions(+)
> 

Acked-by: Rob Herring <robh@kernel.org>