[PATCH 1/2] clk: renesas: r8a779a0: Add the DU clock

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* [PATCH 1/2] clk: renesas: r8a779a0: Add the DU clock
       [not found] <20210622232711.3219697-1-kieran.bingham@ideasonboard.com>
@ 2021-06-22 23:27 ` Kieran Bingham
  2021-06-23 12:18   ` Geert Uytterhoeven
  2021-06-22 23:27 ` [PATCH 2/2] clk: renesas: r8a779a0: Add the DSI clocks Kieran Bingham
  1 sibling, 1 reply; 4+ messages in thread
From: Kieran Bingham @ 2021-06-22 23:27 UTC (permalink / raw)
  To: Geert Uytterhoeven, Kieran Bingham, linux-renesas-soc
  Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
	open list:COMMON CLK FRAMEWORK, open list

The DU clock is added to the S3D1 clock parent. The Renesas BSP lists
S2D1 as the clock parent, however there is no S2 clock on this platform.

S3D1 is chosen as a best effort guess and demonstrates functionality but
is not guaranteed to be correct.

Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index acaf5a93f1d3..a1bd158defb5 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -167,6 +167,7 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
 	DEF_MOD("csi41",	400,	R8A779A0_CLK_CSI0),
 	DEF_MOD("csi42",	401,	R8A779A0_CLK_CSI0),
 	DEF_MOD("csi43",	402,	R8A779A0_CLK_CSI0),
+	DEF_MOD("du",		411,	R8A779A0_CLK_S3D1),
 	DEF_MOD("fcpvd0",	508,	R8A779A0_CLK_S3D1),
 	DEF_MOD("fcpvd1",	509,	R8A779A0_CLK_S3D1),
 	DEF_MOD("hscif0",	514,	R8A779A0_CLK_S1D2),
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH 1/2] clk: renesas: r8a779a0: Add the DU clock
  2021-06-22 23:27 ` [PATCH 1/2] clk: renesas: r8a779a0: Add the DU clock Kieran Bingham
@ 2021-06-23 12:18   ` Geert Uytterhoeven
  0 siblings, 0 replies; 4+ messages in thread
From: Geert Uytterhoeven @ 2021-06-23 12:18 UTC (permalink / raw)
  To: Kieran Bingham
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	open list:COMMON CLK FRAMEWORK, open list

Hi Kieran,

On Wed, Jun 23, 2021 at 1:27 AM Kieran Bingham
<kieran.bingham@ideasonboard.com> wrote:
> The DU clock is added to the S3D1 clock parent. The Renesas BSP lists
> S2D1 as the clock parent, however there is no S2 clock on this platform.
>
> S3D1 is chosen as a best effort guess and demonstrates functionality but
> is not guaranteed to be correct.

Makes sense.

> Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.15.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 2/2] clk: renesas: r8a779a0: Add the DSI clocks
       [not found] <20210622232711.3219697-1-kieran.bingham@ideasonboard.com>
  2021-06-22 23:27 ` [PATCH 1/2] clk: renesas: r8a779a0: Add the DU clock Kieran Bingham
@ 2021-06-22 23:27 ` Kieran Bingham
  2021-06-23 12:22   ` Geert Uytterhoeven
  1 sibling, 1 reply; 4+ messages in thread
From: Kieran Bingham @ 2021-06-22 23:27 UTC (permalink / raw)
  To: Geert Uytterhoeven, Kieran Bingham, linux-renesas-soc
  Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd,
	open list:COMMON CLK FRAMEWORK, open list

The DSI clock is incorrectly defined as a fixed clock. This
demonstrates itself as the dsi-encoders failing to correctly enable and
start their PPI and HS clocks internally, and causes failures.

Move the DSI parent clock to match the updates in the BSP, which
resolves the initialisation procedures.

Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>
---
 drivers/clk/renesas/r8a779a0-cpg-mssr.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index a1bd158defb5..f16d125ca009 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -135,7 +135,6 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 	DEF_FIXED("zt",		R8A779A0_CLK_ZT,	CLK_PLL1_DIV2,	2, 1),
 	DEF_FIXED("ztr",	R8A779A0_CLK_ZTR,	CLK_PLL1_DIV2,	2, 1),
 	DEF_FIXED("zr",		R8A779A0_CLK_ZR,	CLK_PLL1_DIV2,	1, 1),
-	DEF_FIXED("dsi",	R8A779A0_CLK_DSI,	CLK_PLL5_DIV4,	1, 1),
 	DEF_FIXED("cnndsp",	R8A779A0_CLK_CNNDSP,	CLK_PLL5_DIV4,	1, 1),
 	DEF_FIXED("vip",	R8A779A0_CLK_VIP,	CLK_PLL5,	5, 1),
 	DEF_FIXED("adgh",	R8A779A0_CLK_ADGH,	CLK_PLL5_DIV4,	1, 1),
@@ -151,6 +150,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
 	DEF_DIV6P1("mso",	R8A779A0_CLK_MSO,	CLK_PLL5_DIV4,	0x87c),
 	DEF_DIV6P1("canfd",	R8A779A0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),
 	DEF_DIV6P1("csi0",	R8A779A0_CLK_CSI0,	CLK_PLL5_DIV4,	0x880),
+	DEF_DIV6P1("dsi",	R8A779A0_CLK_DSI,	CLK_PLL5_DIV4,	0x884),
 
 	DEF_OSC("osc",		R8A779A0_CLK_OSC,	CLK_EXTAL,	8),
 	DEF_MDSEL("r",		R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
@@ -168,6 +168,8 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
 	DEF_MOD("csi42",	401,	R8A779A0_CLK_CSI0),
 	DEF_MOD("csi43",	402,	R8A779A0_CLK_CSI0),
 	DEF_MOD("du",		411,	R8A779A0_CLK_S3D1),
+	DEF_MOD("dsi0",		415,	R8A779A0_CLK_DSI),
+	DEF_MOD("dsi1",		416,	R8A779A0_CLK_DSI),
 	DEF_MOD("fcpvd0",	508,	R8A779A0_CLK_S3D1),
 	DEF_MOD("fcpvd1",	509,	R8A779A0_CLK_S3D1),
 	DEF_MOD("hscif0",	514,	R8A779A0_CLK_S1D2),
-- 
2.30.2


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH 2/2] clk: renesas: r8a779a0: Add the DSI clocks
  2021-06-22 23:27 ` [PATCH 2/2] clk: renesas: r8a779a0: Add the DSI clocks Kieran Bingham
@ 2021-06-23 12:22   ` Geert Uytterhoeven
  0 siblings, 0 replies; 4+ messages in thread
From: Geert Uytterhoeven @ 2021-06-23 12:22 UTC (permalink / raw)
  To: Kieran Bingham
  Cc: Linux-Renesas, Michael Turquette, Stephen Boyd,
	open list:COMMON CLK FRAMEWORK, open list

On Wed, Jun 23, 2021 at 1:27 AM Kieran Bingham
<kieran.bingham@ideasonboard.com> wrote:
> The DSI clock is incorrectly defined as a fixed clock. This
> demonstrates itself as the dsi-encoders failing to correctly enable and
> start their PPI and HS clocks internally, and causes failures.
>
> Move the DSI parent clock to match the updates in the BSP, which
> resolves the initialisation procedures.
>
> Signed-off-by: Kieran Bingham <kieran.bingham@ideasonboard.com>

Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U")
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.15.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-06-23 12:22 UTC | newest]

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     [not found] <20210622232711.3219697-1-kieran.bingham@ideasonboard.com>
2021-06-22 23:27 ` [PATCH 1/2] clk: renesas: r8a779a0: Add the DU clock Kieran Bingham
2021-06-23 12:18   ` Geert Uytterhoeven
2021-06-22 23:27 ` [PATCH 2/2] clk: renesas: r8a779a0: Add the DSI clocks Kieran Bingham
2021-06-23 12:22   ` Geert Uytterhoeven

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