From: Geert Uytterhoeven <geert@linux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Linus Walleij <linus.walleij@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Philipp Zabel <p.zabel@pengutronix.de>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
Phil Edworthy <phil.edworthy@renesas.com>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v3 5/5] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt
Date: Fri, 13 May 2022 08:53:38 +0200 [thread overview]
Message-ID: <CAMuHMdVazy9y_U6Nva+B-3vuX1Ersq+QirXDDgSh28pj8s=EJA@mail.gmail.com> (raw)
In-Reply-To: <CA+V-a8tNrJQtAQYoUKVwH9w4QOyA9JUWNjiYDPUPsj6UuJ4vaA@mail.gmail.com>
Hi Prabhakar,
On Thu, May 12, 2022 at 7:36 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Thu, May 12, 2022 at 8:39 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, May 11, 2022 at 8:32 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > Add IRQ domian to RZ/G2L pinctrl driver to handle GPIO interrupt.
> > > GPIO0-GPIO122 pins can be used as IRQ lines but only 32 pins can be
> > > used as IRQ lines at given time. Selection of pins as IRQ lines
> > > is handled by IA55 (which is the IRQC block) which sits in between the
> > > GPIO and GIC.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> > > +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> >
> > > static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
> > > {
> > > struct device_node *np = pctrl->dev->of_node;
> > > struct gpio_chip *chip = &pctrl->gpio_chip;
> > > const char *name = dev_name(pctrl->dev);
> > > + struct irq_domain *parent_domain;
> > > struct of_phandle_args of_args;
> > > + struct device_node *parent_np;
> > > + struct gpio_irq_chip *girq;
> > > int ret;
> > >
> > > + parent_np = of_irq_find_parent(np);
> > > + if (!parent_np)
> > > + return -ENXIO;
> > > +
> > > + parent_domain = irq_find_host(parent_np);
> > > + of_node_put(parent_np);
> > > + if (!parent_domain)
> > > + return -EPROBE_DEFER;
> > > +
> > > ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args);
> > > if (ret) {
> > > dev_err(pctrl->dev, "Unable to parse gpio-ranges\n");
> > > @@ -1138,6 +1330,15 @@ static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl)
> > > chip->base = -1;
> > > chip->ngpio = of_args.args[2];
> > >
> > > + girq = &chip->irq;
> > > + girq->chip = &rzg2l_gpio_irqchip;
> > > + girq->fwnode = of_node_to_fwnode(np);
> > > + girq->parent_domain = parent_domain;
> > > + girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq;
> > > + girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec;
> > > + girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free;
> > > + girq->ngirq = RZG2L_TINT_MAX_INTERRUPT;
> > > +
> >
> > I think you need to provide a .init_valid_mask() callback, as
> > gpiochip_irqchip_remove() relies on that for destroying interrupts.
> Are you suggesting the callback to avoid looping through all the GPIO pins?
gpiochip_irqchip_remove() does:
/* Remove all IRQ mappings and delete the domain */
if (gc->irq.domain) {
unsigned int irq;
for (offset = 0; offset < gc->ngpio; offset++) {
if (!gpiochip_irqchip_irq_valid(gc, offset))
continue;
irq = irq_find_mapping(gc->irq.domain, offset);
irq_dispose_mapping(irq);
}
irq_domain_remove(gc->irq.domain);
}
The main thing is not about avoiding to loop through all GPIO pins,
but to avoid irq_{find,dispose}_mapping() doing the wrong thing.
The loop is over all GPIO offsets, while not all of them are mapped
to valid interrupts. Does the above work correctly?
> > However, the mask will need to be dynamic, as GPIO interrupts can be
> > mapped and unmapped to one of the 32 available interrupts dynamically,
> > right?
> Yep that's correct.
>
> > I'm not sure if that can be done easily: if gpiochip_irqchip_irq_valid()
> > is ever called too early, before the mapping is done, it would fail.
> >
> The mask initialization is a one time process and that is during
> adding the GPIO chip. At this stage we won't be knowing what will be
> the valid GPIO pins used as interrupts. Maybe the core needs to
> implement a callback which lands in the GPIO controller driver to tell
> if the gpio irq line is valid. This way we can handle dynamic
> interrupts.
Upon closer look, I think the mask is a red herring, and we don't
need it.
But we do need to handle the (possible) mismatch between GPIO
offset (index) and IRQ offset in the above code.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2022-05-13 6:54 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-11 18:32 [PATCH v3 0/5] Renesas RZ/G2L IRQC support Lad Prabhakar
2022-05-11 18:32 ` [PATCH v3 1/5] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller Lad Prabhakar
2022-05-12 6:14 ` Biju Das
2022-05-12 6:43 ` Geert Uytterhoeven
2022-05-12 17:58 ` Lad, Prabhakar
2022-05-11 18:32 ` [PATCH v3 2/5] irqchip: Add RZ/G2L IA55 Interrupt Controller driver Lad Prabhakar
2022-05-11 19:25 ` Biju Das
2022-05-12 18:01 ` Lad, Prabhakar
2022-05-12 7:05 ` Geert Uytterhoeven
2022-05-12 7:23 ` Marc Zyngier
2022-05-12 7:26 ` Geert Uytterhoeven
2022-05-12 18:08 ` Lad, Prabhakar
2022-05-11 18:32 ` [PATCH v3 3/5] gpio: gpiolib: Allow free() callback to be overridden Lad Prabhakar
2022-05-12 7:06 ` Geert Uytterhoeven
2022-05-12 11:19 ` Marc Zyngier
2022-05-12 12:48 ` Lad, Prabhakar
2022-05-12 13:24 ` Marc Zyngier
2022-05-12 13:50 ` Lad, Prabhakar
2022-05-12 16:26 ` Marc Zyngier
2022-05-12 17:55 ` Lad, Prabhakar
2022-05-12 22:24 ` Marc Zyngier
2022-05-11 18:32 ` [PATCH v3 4/5] gpio: gpiolib: Add ngirq member to struct gpio_irq_chip Lad Prabhakar
2022-05-12 7:29 ` Geert Uytterhoeven
2022-05-18 18:30 ` Lad, Prabhakar
2022-05-13 20:47 ` Linus Walleij
2022-05-18 18:36 ` Lad, Prabhakar
2022-05-19 13:21 ` Linus Walleij
2022-05-11 18:32 ` [PATCH v3 5/5] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt Lad Prabhakar
2022-05-12 5:35 ` Biju Das
2022-05-12 17:43 ` Lad, Prabhakar
2022-05-12 17:59 ` Biju Das
2022-05-13 6:12 ` Biju Das
2022-05-13 13:42 ` Lad, Prabhakar
2022-05-12 7:39 ` Geert Uytterhoeven
2022-05-12 17:36 ` Lad, Prabhakar
2022-05-13 6:53 ` Geert Uytterhoeven [this message]
2022-05-13 13:55 ` Lad, Prabhakar
2022-05-13 14:29 ` Geert Uytterhoeven
2022-05-13 18:13 ` Lad, Prabhakar
2022-05-15 5:13 ` Biju Das
[not found] ` <87pmkfm0v3.wl-maz@kernel.org>
2022-05-16 7:20 ` Biju Das
[not found] ` <87pmkd6gda.wl-maz@kernel.org>
2022-05-16 8:33 ` Biju Das
[not found] ` <87o7zx6ckp.wl-maz@kernel.org>
2022-05-16 9:56 ` Biju Das
2022-05-16 7:13 ` Geert Uytterhoeven
2022-05-18 19:04 ` Lad, Prabhakar
2022-05-12 11:15 ` Marc Zyngier
2022-05-12 17:46 ` Lad, Prabhakar
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