From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Sagar Kadam <sagar.kadam@sifive.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
Prabhakar <prabhakar.csengg@gmail.com>,
Phil Edworthy <phil.edworthy@renesas.com>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH RFC 1/2] dt-bindings: interrupt-controller: sifive,plic: Document Renesas RZ/Five SoC
Date: Thu, 9 Jun 2022 11:42:10 +0200 [thread overview]
Message-ID: <CAMuHMdVos-hVhGar91oBvZaCOLfjdsNR7vRGnX-KuNt0UX3xWQ@mail.gmail.com> (raw)
In-Reply-To: <20220524172214.5104-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi Prabhakar,
On Tue, May 24, 2022 at 7:22 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Document Renesas RZ/Five (R9A07G043) SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -28,7 +28,10 @@ description:
>
> While the PLIC supports both edge-triggered and level-triggered interrupts,
> interrupt handlers are oblivious to this distinction and therefore it is not
> - specified in the PLIC device-tree binding.
> + specified in the PLIC device-tree binding for SiFive PLIC (and similar PLIC's),
> + but for the Renesas RZ/Five Soc (AX45MP AndesCore) which has NCEPLIC100 we need
> + to specify the interrupt type as the flow for EDGE interrupts is different
> + compared to LEVEL interrupts.
>
> While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
> "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
> @@ -57,6 +60,7 @@ properties:
> - enum:
> - allwinner,sun20i-d1-plic
> - const: thead,c900-plic
> + - const: renesas-r9a07g043-plic
renesas,r9a07g043-plic
>
> reg:
> maxItems: 1
> @@ -64,8 +68,7 @@ properties:
> '#address-cells':
> const: 0
>
> - '#interrupt-cells':
> - const: 1
> + '#interrupt-cells': true
>
> interrupt-controller: true
>
> @@ -91,6 +94,35 @@ required:
> - interrupts-extended
> - riscv,ndev
>
> +if:
> + properties:
> + compatible:
> + contains:
> + const: renesas-r9a07g043-plic
renesas,r9a07g043-plic
> +then:
> + properties:
> + clocks:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + '#interrupt-cells':
> + const: 2
> +
> + required:
> + - clocks
> + - resets
> + - power-domains
> +
> +else:
> + properties:
> + '#interrupt-cells':
> + const: 1
> +
> additionalProperties: false
>
> examples:
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2022-06-09 9:42 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-24 17:22 [PATCH RFC 0/2] Add PLIC support for Renesas RZ/Five SoC Lad Prabhakar
2022-05-24 17:22 ` [PATCH RFC 1/2] dt-bindings: interrupt-controller: sifive,plic: Document " Lad Prabhakar
2022-06-05 14:23 ` Rob Herring
2022-06-24 9:59 ` Lad, Prabhakar
2022-07-06 21:58 ` Rob Herring
2022-07-07 9:51 ` Marc Zyngier
2022-07-12 18:19 ` Rob Herring
2022-07-12 19:21 ` Marc Zyngier
2022-07-22 18:09 ` Rob Herring
2022-06-09 9:42 ` Geert Uytterhoeven [this message]
2022-06-24 10:01 ` Lad, Prabhakar
2022-05-24 17:22 ` [PATCH RFC 2/2] irqchip/sifive-plic: Add support for " Lad Prabhakar
2022-05-25 8:00 ` Geert Uytterhoeven
2022-05-25 9:00 ` Lad, Prabhakar
2022-05-25 9:35 ` Geert Uytterhoeven
2022-05-25 9:43 ` Lad, Prabhakar
2022-05-25 11:46 ` Geert Uytterhoeven
2022-05-27 11:05 ` Lad, Prabhakar
2022-06-06 15:41 ` Marc Zyngier
2022-06-07 12:41 ` Lad, Prabhakar
2022-06-08 10:27 ` Marc Zyngier
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