From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Conor Dooley <Conor.Dooley@microchip.com>
Cc: "Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Alessandro Zummo" <a.zummo@towertech.it>,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Atish Patra" <atishp@rivosinc.com>,
"Bin Meng" <bin.meng@windriver.com>,
"Bartosz Golaszewski" <brgl@bgdev.pl>,
Daire.McNamara@microchip.com,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>, "Heiko Stuebner" <heiko@sntech.de>,
Ivan.Griffin@microchip.com,
"Jassi Brar" <jassisinghbrar@gmail.com>,
"Krzysztof Kozlowski" <krzysztof.kozlowski@canonical.com>,
"Lee Jones" <lee.jones@linaro.org>,
"Lewis Hanly" <Lewis.Hanly@microchip.com>,
"Linus Walleij" <linus.walleij@linaro.org>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
"Linux I2C" <linux-i2c@vger.kernel.org>,
"Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
"Linux PWM List" <linux-pwm@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
linux-rtc@vger.kernel.org, "Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Thierry Reding" <thierry.reding@gmail.com>
Subject: Re: [PATCH v5 06/12] dt-bindings: pwm: add microchip corepwm binding
Date: Wed, 2 Feb 2022 15:02:03 +0100 [thread overview]
Message-ID: <CAMuHMdXvw9cNNzBhp-sSMTXxP2eALhB=fD78Wgx-kks7wr6oiQ@mail.gmail.com> (raw)
In-Reply-To: <3862e358-901c-e848-71af-01eceed26f74@microchip.com>
Hi Conor,
On Wed, Feb 2, 2022 at 2:46 PM <Conor.Dooley@microchip.com> wrote:
> On 02/02/2022 13:28, Geert Uytterhoeven wrote:
> > On Wed, Feb 2, 2022 at 1:33 PM <conor.dooley@microchip.com> wrote:
> >>> On 01/02/2022 07:58, Uwe Kleine-König wrote:
> >>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >>>> On Mon, Jan 31, 2022 at 11:47:21AM +0000, conor.dooley@microchip.com wrote:
> >>>> From: Conor Dooley <conor.dooley@microchip.com>
> >>>>
> >>>> Add device tree bindings for the Microchip fpga fabric based "core" PWM
> >>>> controller.
> >>>>
> >>>> Reviewed-by: Rob Herring <robh@kernel.org>
> >>>>
> >>>> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >>>> ---
> >>>> .../bindings/pwm/microchip,corepwm.yaml | 75 +++++++++++++++++++
> >
> >>>> + microchip,sync-update:
> >>>> + description: |
> >>>> + In synchronous mode, all channels are updated at the beginning of the PWM period.
> >>>> + Asynchronous mode is relevant to applications such as LED control, where
> >>>> + synchronous updates are not required. Asynchronous mode lowers the area size,
> >>>> + reducing shadow register requirements. This can be set at run time, provided
> >>>> + SHADOW_REG_EN is asserted. SHADOW_REG_EN is set by the FPGA bitstream programmed
> >>>> + to the device.
> >>>> + Each bit corresponds to a PWM channel & represents whether synchronous mode is
> >>>> + possible for the PWM channel.
> >>>> +
> >>>> + $ref: /schemas/types.yaml#/definitions/uint16
> >>>> + default: 0
> >>>
> >>> I'm not sure I understand this correctly. This is a soft-core and you
> >>> can synthesize it either with or without the ability to do synchronous
> >>> updates or not, right? All 16 channels share the same period length and
> >>> in the simple implementation changing the duty cycle is done at once
> >>> (maybe introducing a glitch) and in the more expensive implementation
> >>> there is a register to implement both variants?
> >>
> >> Correct. If the IP is instantiated with SHADOW_REG_ENx=1, both
> >> registers that control the duty cycle for channel x have a second
> >> "shadow reg" synthesised. At runtime a bit wide register exposed to
> >> APB can be used to toggle on/off synchronised mode for all channels
> >> it has been synthesised for.
> >>
> >> I will reword this description since it is not clear.
> >
> > Shouldn't it use a different compatible value instead?
> > Differentiation by properties is not recommended, as it's easy to
> > miss a difference.
>
> Either you have something in mind that I've not thought of, or I've done
> a bad job of explaining again. The buffer/"shadow" registers are
> synthesised on a per channel basis, so any combination of the 16
> channels may have this capability. The same applies to the DAC mode, per
> channel there too.
Oops, hadn't noticed this is per channel. Indeed, then a different
compatible value is futile.
So since "microchip,sync-update" is a bitmask, perhaps it should be
called "microchip,sync-update-mask"?
Same for "microchip,dac-mode" -> "microchip,dac-mode-mask"?
Also, using different integer sizes than uint32 is frowned upon, unless
there is a very good reason to do so. I can imagine a future version
would support more channels, and then uint16 becomes a limitation.
For both: Rob?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2022-02-02 14:02 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-31 11:47 [PATCH v5 00/12] Update the Icicle Kit device tree conor.dooley
2022-01-31 11:47 ` [PATCH v5 01/12] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley
2022-02-04 22:39 ` Rob Herring
2022-01-31 11:47 ` [PATCH v5 02/12] dt-bindings: soc/microchip: add services as children of sys ctrlr conor.dooley
2022-02-04 22:42 ` Rob Herring
2022-01-31 11:47 ` [PATCH v5 03/12] dt-bindings: i2c: add bindings for microchip mpfs i2c conor.dooley
2022-01-31 13:37 ` Rob Herring
2022-01-31 15:39 ` Rob Herring
2022-01-31 15:55 ` Conor.Dooley
2022-02-04 22:45 ` Rob Herring
2022-02-05 11:53 ` Conor Dooley
2022-01-31 11:47 ` [PATCH v5 04/12] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley
2022-01-31 13:37 ` Rob Herring
2022-02-04 22:46 ` Rob Herring
2022-01-31 11:47 ` [PATCH v5 05/12] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley
2022-01-31 13:37 ` Rob Herring
2022-01-31 11:47 ` [PATCH v5 06/12] dt-bindings: pwm: add microchip corepwm binding conor.dooley
2022-01-31 13:37 ` Rob Herring
2022-02-01 7:58 ` Uwe Kleine-König
2022-02-02 12:35 ` conor.dooley
2022-02-02 13:28 ` Geert Uytterhoeven
2022-02-02 13:46 ` Conor.Dooley
2022-02-02 14:02 ` Geert Uytterhoeven [this message]
2022-02-02 14:37 ` Conor.Dooley
2022-02-05 12:48 ` Conor Dooley
2022-01-31 11:47 ` [PATCH v5 07/12] riscv: dts: microchip: use clk defines for icicle kit conor.dooley
2022-01-31 11:47 ` [PATCH v5 08/12] riscv: dts: microchip: add fpga fabric section to " conor.dooley
2022-01-31 11:47 ` [PATCH v5 09/12] riscv: dts: microchip: refactor icicle kit device tree conor.dooley
2022-01-31 11:47 ` [PATCH v5 10/12] riscv: dts: microchip: update peripherals in " conor.dooley
2022-01-31 11:47 ` [PATCH v5 11/12] riscv: dts: microchip: add new peripherals to " conor.dooley
2022-01-31 11:47 ` [PATCH v5 12/12] MAINTAINERS: update riscv/microchip entry conor.dooley
2022-02-04 18:09 ` [PATCH v5 00/12] Update the Icicle Kit device tree Palmer Dabbelt
2022-02-04 18:47 ` Conor Dooley
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