From: Zong Li <zong.li@sifive.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Stephen Boyd <sboyd@kernel.org>,
Andreas Schwab <schwab@linux-m68k.org>,
Pragnesh Patel <pragnesh.patel@openfive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Michael Turquette <mturquette@baylibre.com>,
Yash Shah <yash.shah@sifive.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>,
linux-clk@vger.kernel.org,
linux-riscv <linux-riscv@lists.infradead.org>,
Pragnesh Patel <pragnesh.patel@sifive.com>
Subject: Re: [PATCH v4 4/4] clk: sifive: Fix the wrong bit field shift
Date: Mon, 23 Nov 2020 15:18:17 +0800 [thread overview]
Message-ID: <CANXhq0rQtgVNoDJ7DLFcBRwru1H5+4_0LoANCVcGMaB2LmCOMA@mail.gmail.com> (raw)
In-Reply-To: <mhng-738e4a27-9751-4937-b3ed-efdcdce56f0c@palmerdabbelt-glaptop1>
On Sat, Nov 21, 2020 at 9:29 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Wed, 11 Nov 2020 02:06:08 PST (-0800), zong.li@sifive.com wrote:
> > The clk enable bit should be 31 instead of 24.
> >
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > Reported-by: Pragnesh Patel <pragnesh.patel@sifive.com>
> > ---
> > drivers/clk/sifive/sifive-prci.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/clk/sifive/sifive-prci.h b/drivers/clk/sifive/sifive-prci.h
> > index 802fc8fb9c09..da7be9103d4d 100644
> > --- a/drivers/clk/sifive/sifive-prci.h
> > +++ b/drivers/clk/sifive/sifive-prci.h
> > @@ -59,7 +59,7 @@
> >
> > /* DDRPLLCFG1 */
> > #define PRCI_DDRPLLCFG1_OFFSET 0x10
> > -#define PRCI_DDRPLLCFG1_CKE_SHIFT 24
> > +#define PRCI_DDRPLLCFG1_CKE_SHIFT 31
> > #define PRCI_DDRPLLCFG1_CKE_MASK (0x1 << PRCI_DDRPLLCFG1_CKE_SHIFT)
> >
> > /* GEMGXLPLLCFG0 */
> > @@ -81,7 +81,7 @@
> >
> > /* GEMGXLPLLCFG1 */
> > #define PRCI_GEMGXLPLLCFG1_OFFSET 0x20
> > -#define RCI_GEMGXLPLLCFG1_CKE_SHIFT 24
> > +#define RCI_GEMGXLPLLCFG1_CKE_SHIFT 31
> > #define PRCI_GEMGXLPLLCFG1_CKE_MASK (0x1 << PRCI_GEMGXLPLLCFG1_CKE_SHIFT)
> >
> > /* CORECLKSEL */
>
> Section 7.3 of v1.0 of the FU540 manual says that bit 24 contains the PLL clock
> enable for both of these. I don't know if that's accurate, but if it is then I
> believe this would break the FU540. Don't have one to test on, though.
Yes, the manual seems to be wrong and should be corrected. It doesn't
break the FU540 yet because we don't use these fields in s-mode Linux
driver, we set them in m-mode FSBL/U-boot-SPL bootloader during boot
time, and the implementation of FSBL and U-boot-SPL both are correct.
The following link is the U-boot SPL source:
https://github.com/u-boot/u-boot/blob/da09b99ea572cec9a114872e480b798db11f9c6e/drivers/clk/sifive/fu540-prci.c#L128
prev parent reply other threads:[~2020-11-23 7:18 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-11 10:06 [PATCH v4 0/4] clk: add driver for the SiFive FU740 Zong Li
2020-11-11 10:06 ` [PATCH v4 1/4] clk: sifive: Extract prci core to common base Zong Li
2020-11-21 1:29 ` Palmer Dabbelt
2020-11-24 18:42 ` kernel test robot
2020-11-26 3:04 ` Zong Li
2020-11-11 10:06 ` [PATCH v4 2/4] clk: sifive: Use common name for prci configuration Zong Li
2020-11-21 1:29 ` Palmer Dabbelt
2020-11-23 7:16 ` Zong Li
2020-11-11 10:06 ` [PATCH v4 3/4] clk: sifive: Add a driver for the SiFive FU740 PRCI IP block Zong Li
2020-11-21 1:29 ` Palmer Dabbelt
2020-11-23 7:21 ` Zong Li
2020-11-21 1:29 ` Palmer Dabbelt
2020-11-23 7:30 ` Zong Li
2020-11-11 10:06 ` [PATCH v4 4/4] clk: sifive: Fix the wrong bit field shift Zong Li
2020-11-21 1:29 ` Palmer Dabbelt
2020-11-23 7:18 ` Zong Li [this message]
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