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* [PATCH -next v2] riscv: Enable KFENCE for riscv64
@ 2021-06-15  3:07 Liu Shixin
  2021-06-16  9:11 ` Marco Elver
  0 siblings, 1 reply; 4+ messages in thread
From: Liu Shixin @ 2021-06-15  3:07 UTC (permalink / raw)
  To: Paul Walmsley, Palmer Dabbelt, Palmer Dabbelt, Albert Ou,
	Alexander Potapenko, Marco Elver, Dmitry Vyukov
  Cc: linux-riscv, linux-kernel, kasan-dev, Liu Shixin

Add architecture specific implementation details for KFENCE and enable
KFENCE for the riscv64 architecture. In particular, this implements the
required interface in <asm/kfence.h>.

KFENCE requires that attributes for pages from its memory pool can
individually be set. Therefore, force the kfence pool to be mapped at
page granularity.

Testing this patch using the testcases in kfence_test.c and all passed.

Signed-off-by: Liu Shixin <liushixin2@huawei.com>
Acked-by: Marco Elver <elver@google.com>
Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
---
v1->v2: Add the acked-by and Reviewed-by.

 arch/riscv/Kconfig              |  1 +
 arch/riscv/include/asm/kfence.h | 63 +++++++++++++++++++++++++++++++++
 arch/riscv/mm/fault.c           | 11 +++++-
 3 files changed, 74 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/include/asm/kfence.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 4c0bfb2569e9..1421da5ef1a2 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -65,6 +65,7 @@ config RISCV
 	select HAVE_ARCH_JUMP_LABEL_RELATIVE
 	select HAVE_ARCH_KASAN if MMU && 64BIT
 	select HAVE_ARCH_KASAN_VMALLOC if MMU && 64BIT
+	select HAVE_ARCH_KFENCE if MMU && 64BIT
 	select HAVE_ARCH_KGDB
 	select HAVE_ARCH_KGDB_QXFER_PKT
 	select HAVE_ARCH_MMAP_RND_BITS if MMU
diff --git a/arch/riscv/include/asm/kfence.h b/arch/riscv/include/asm/kfence.h
new file mode 100644
index 000000000000..d887a54042aa
--- /dev/null
+++ b/arch/riscv/include/asm/kfence.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _ASM_RISCV_KFENCE_H
+#define _ASM_RISCV_KFENCE_H
+
+#include <linux/kfence.h>
+#include <linux/pfn.h>
+#include <asm-generic/pgalloc.h>
+#include <asm/pgtable.h>
+
+static inline int split_pmd_page(unsigned long addr)
+{
+	int i;
+	unsigned long pfn = PFN_DOWN(__pa((addr & PMD_MASK)));
+	pmd_t *pmd = pmd_off_k(addr);
+	pte_t *pte = pte_alloc_one_kernel(&init_mm);
+
+	if (!pte)
+		return -ENOMEM;
+
+	for (i = 0; i < PTRS_PER_PTE; i++)
+		set_pte(pte + i, pfn_pte(pfn + i, PAGE_KERNEL));
+	set_pmd(pmd, pfn_pmd(PFN_DOWN(__pa(pte)), PAGE_TABLE));
+
+	flush_tlb_kernel_range(addr, addr + PMD_SIZE);
+	return 0;
+}
+
+static inline bool arch_kfence_init_pool(void)
+{
+	int ret;
+	unsigned long addr;
+	pmd_t *pmd;
+
+	for (addr = (unsigned long)__kfence_pool; is_kfence_address((void *)addr);
+	     addr += PAGE_SIZE) {
+		pmd = pmd_off_k(addr);
+
+		if (pmd_leaf(*pmd)) {
+			ret = split_pmd_page(addr);
+			if (ret)
+				return false;
+		}
+	}
+
+	return true;
+}
+
+static inline bool kfence_protect_page(unsigned long addr, bool protect)
+{
+	pte_t *pte = virt_to_kpte(addr);
+
+	if (protect)
+		set_pte(pte, __pte(pte_val(*pte) & ~_PAGE_PRESENT));
+	else
+		set_pte(pte, __pte(pte_val(*pte) | _PAGE_PRESENT));
+
+	flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
+
+	return true;
+}
+
+#endif /* _ASM_RISCV_KFENCE_H */
diff --git a/arch/riscv/mm/fault.c b/arch/riscv/mm/fault.c
index 096463cc6fff..aa08dd2f8fae 100644
--- a/arch/riscv/mm/fault.c
+++ b/arch/riscv/mm/fault.c
@@ -14,6 +14,7 @@
 #include <linux/signal.h>
 #include <linux/uaccess.h>
 #include <linux/kprobes.h>
+#include <linux/kfence.h>
 
 #include <asm/ptrace.h>
 #include <asm/tlbflush.h>
@@ -45,7 +46,15 @@ static inline void no_context(struct pt_regs *regs, unsigned long addr)
 	 * Oops. The kernel tried to access some bad page. We'll have to
 	 * terminate things with extreme prejudice.
 	 */
-	msg = (addr < PAGE_SIZE) ? "NULL pointer dereference" : "paging request";
+	if (addr < PAGE_SIZE)
+		msg = "NULL pointer dereference";
+	else {
+		if (kfence_handle_page_fault(addr, regs->cause == EXC_STORE_PAGE_FAULT, regs))
+			return;
+
+		msg = "paging request";
+	}
+
 	die_kernel_fault(msg, addr, regs);
 }
 
-- 
2.18.0.huawei.25


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH -next v2] riscv: Enable KFENCE for riscv64
  2021-06-15  3:07 [PATCH -next v2] riscv: Enable KFENCE for riscv64 Liu Shixin
@ 2021-06-16  9:11 ` Marco Elver
  2021-07-01  2:38   ` Palmer Dabbelt
  0 siblings, 1 reply; 4+ messages in thread
From: Marco Elver @ 2021-06-16  9:11 UTC (permalink / raw)
  To: Liu Shixin
  Cc: Paul Walmsley, Palmer Dabbelt, Palmer Dabbelt, Albert Ou,
	Alexander Potapenko, Dmitry Vyukov, linux-riscv, LKML, kasan-dev

On Tue, 15 Jun 2021 at 04:35, Liu Shixin <liushixin2@huawei.com> wrote:
> Add architecture specific implementation details for KFENCE and enable
> KFENCE for the riscv64 architecture. In particular, this implements the
> required interface in <asm/kfence.h>.
>
> KFENCE requires that attributes for pages from its memory pool can
> individually be set. Therefore, force the kfence pool to be mapped at
> page granularity.
>
> Testing this patch using the testcases in kfence_test.c and all passed.
>
> Signed-off-by: Liu Shixin <liushixin2@huawei.com>
> Acked-by: Marco Elver <elver@google.com>
> Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>

I can't see this in -next yet. It would be nice if riscv64 could get
KFENCE support.

Thanks,
-- Marco

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH -next v2] riscv: Enable KFENCE for riscv64
  2021-06-16  9:11 ` Marco Elver
@ 2021-07-01  2:38   ` Palmer Dabbelt
  2021-07-01  6:26     ` Marco Elver
  0 siblings, 1 reply; 4+ messages in thread
From: Palmer Dabbelt @ 2021-07-01  2:38 UTC (permalink / raw)
  To: elver
  Cc: liushixin2, Paul Walmsley, aou, glider, dvyukov, linux-riscv,
	linux-kernel, kasan-dev

On Wed, 16 Jun 2021 02:11:53 PDT (-0700), elver@google.com wrote:
> On Tue, 15 Jun 2021 at 04:35, Liu Shixin <liushixin2@huawei.com> wrote:
>> Add architecture specific implementation details for KFENCE and enable
>> KFENCE for the riscv64 architecture. In particular, this implements the
>> required interface in <asm/kfence.h>.
>>
>> KFENCE requires that attributes for pages from its memory pool can
>> individually be set. Therefore, force the kfence pool to be mapped at
>> page granularity.
>>
>> Testing this patch using the testcases in kfence_test.c and all passed.
>>
>> Signed-off-by: Liu Shixin <liushixin2@huawei.com>
>> Acked-by: Marco Elver <elver@google.com>
>> Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
>
> I can't see this in -next yet. It would be nice if riscv64 could get
> KFENCE support.

Thanks, this is on for-next.  I'm just doing a boot test with 
CONFIG_KFENCE=y (and whatever that turns on for defconfig), let me know 
if there's anything more interesting to test on the KFENCE side of 
things.

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH -next v2] riscv: Enable KFENCE for riscv64
  2021-07-01  2:38   ` Palmer Dabbelt
@ 2021-07-01  6:26     ` Marco Elver
  0 siblings, 0 replies; 4+ messages in thread
From: Marco Elver @ 2021-07-01  6:26 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: liushixin2, Paul Walmsley, aou, glider, dvyukov, linux-riscv,
	linux-kernel, kasan-dev

On Thu, 1 Jul 2021 at 04:38, 'Palmer Dabbelt' via kasan-dev
<kasan-dev@googlegroups.com> wrote:
> On Wed, 16 Jun 2021 02:11:53 PDT (-0700), elver@google.com wrote:
> > On Tue, 15 Jun 2021 at 04:35, Liu Shixin <liushixin2@huawei.com> wrote:
> >> Add architecture specific implementation details for KFENCE and enable
> >> KFENCE for the riscv64 architecture. In particular, this implements the
> >> required interface in <asm/kfence.h>.
> >>
> >> KFENCE requires that attributes for pages from its memory pool can
> >> individually be set. Therefore, force the kfence pool to be mapped at
> >> page granularity.
> >>
> >> Testing this patch using the testcases in kfence_test.c and all passed.
> >>
> >> Signed-off-by: Liu Shixin <liushixin2@huawei.com>
> >> Acked-by: Marco Elver <elver@google.com>
> >> Reviewed-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> >
> > I can't see this in -next yet. It would be nice if riscv64 could get
> > KFENCE support.
>
> Thanks, this is on for-next.  I'm just doing a boot test with
> CONFIG_KFENCE=y (and whatever that turns on for defconfig), let me know
> if there's anything more interesting to test on the KFENCE side of
> things.

To test if everything still works, CONFIG_KFENCE_KUNIT_TEST=y
(requires CONFIG_KUNIT=y) will run the KFENCE test suite on boot.

Thanks,
-- Marco

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2021-07-01  6:26 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2021-06-15  3:07 [PATCH -next v2] riscv: Enable KFENCE for riscv64 Liu Shixin
2021-06-16  9:11 ` Marco Elver
2021-07-01  2:38   ` Palmer Dabbelt
2021-07-01  6:26     ` Marco Elver

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