[PATCHv3 0/2] Improved perf support for imx53/ppd

[PATCHv3 0/2] Improved perf support for imx53/ppd

[Sebastian Reichel]

Hi,

This improves perf on imx53 by adding support for enabling the Secure
Debug Enable Register (SDER) SUNIDEN bit. This unlocks new
functionality:

ppd before patchset# perf stat -e cycles,instructions sleep 1 2>&1 | grep instructions
                 0      instructions              #    0.00  insn per cycle

ppd  after patchset# perf stat -e cycles,instructions sleep 1 2>&1 | grep instructions
            177864      instructions              #    0.05  insn per cycle

Changes since PATCHv2:
 * Always enable GPC_DBG_EN when kernel configuration allows using perf
   to allow cleanup of the arm-pmu driver.
Changes since PATCHv1:
 * Update DTS patch to reference imx53.dtsi's pmu node
 * Remove a superfluous newline in first patch

-- Sebastian

Sebastian Reichel (2):
  ARM: imx53: add secure-reg-access support for PMU
  ARM: dts: imx53: PPD: Enable secure-reg-access

 arch/arm/boot/dts/imx53-ppd.dts |  4 ++++
 arch/arm/boot/dts/imx53.dtsi    |  2 +-
 arch/arm/mach-imx/mach-imx53.c  | 41 ++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 45 insertions(+), 2 deletions(-)

-- 
2.15.1

[PATCHv3 1/2] ARM: imx53: add secure-reg-access support for PMU

[Sebastian Reichel]

On i.MX53 it is necessary to set the DBG_EN bit in the
platform GPC register to enable access to PMU counters
other than the cycle counter.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
 arch/arm/mach-imx/mach-imx53.c | 41 ++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 07c2e8dca494..661777ee1cc4 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -28,10 +28,49 @@ static void __init imx53_init_early(void)
 	mxc_set_cpu_type(MXC_CPU_MX53);
 }
 
+#define MXC_CORTEXA8_PLAT_GPC 0x63fa0004
+#define GPC_DBG_EN BIT(16)
+
+/*
+ * This enables the DBGEN bit in ARM_GPC register, which is
+ * required for accessing some performance counter features.
+ * Technically it is only required while perf is used, but to
+ * keep the source code simple we just enable it all the time
+ * when the kernel configuration allows using the feature.
+ */
+static void imx53_pmu_init(void)
+{
+	void __iomem *gpc_reg;
+	struct device_node *node;
+	u32 gpc;
+
+	if (!IS_ENABLED(CONFIG_ARM_PMU))
+		return;
+
+	node = of_find_compatible_node(NULL, NULL, "arm,cortex-a8-pmu");
+	if (!node)
+		return;
+
+	if (!of_property_read_bool(node, "secure-reg-access"))
+		return;
+
+	gpc_reg = ioremap(MXC_CORTEXA8_PLAT_GPC, 4);
+	if (!gpc_reg) {
+		pr_warning("unable to map GPC to enable perf\n");
+		return;
+	}
+
+	gpc = __raw_readl(gpc_reg);
+	gpc |= GPC_DBG_EN;
+	__raw_writel(gpc, gpc_reg);
+
+	return;
+}
+
 static void __init imx53_dt_init(void)
 {
 	imx_src_init();
-
+	imx53_pmu_init();
 	imx_aips_allow_unprivileged_access("fsl,imx53-aipstz");
 }
 
-- 
2.15.1

[PATCHv3 2/2] ARM: dts: imx53: PPD: Enable secure-reg-access

[Sebastian Reichel]

Add secure-reg-access on PPD device tree to enable PMU and
hardware counters for perf.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
 arch/arm/boot/dts/imx53-ppd.dts | 4 ++++
 arch/arm/boot/dts/imx53.dtsi    | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts
index cce959438a79..4ecbe6e4eecb 100644
--- a/arch/arm/boot/dts/imx53-ppd.dts
+++ b/arch/arm/boot/dts/imx53-ppd.dts
@@ -556,6 +556,10 @@
 	};
 };
 
+&pmu {
+	secure-reg-access;
+};
+
 &pwm1 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_pwm1>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 1040251f2951..7df4853dc771 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -116,7 +116,7 @@
 		};
 	};
 
-	pmu {
+	pmu: pmu {
 		compatible = "arm,cortex-a8-pmu";
 		interrupt-parent = <&tzic>;
 		interrupts = <77>;
-- 
2.15.1

Re: [PATCHv3 1/2] ARM: imx53: add secure-reg-access support for PMU

[Fabio Estevam]

On Fri, Feb 9, 2018 at 3:03 PM, Sebastian Reichel
<sebastian.reichel@collabora.co.uk> wrote:

> +       gpc_reg = ioremap(MXC_CORTEXA8_PLAT_GPC, 4);
> +       if (!gpc_reg) {
> +               pr_warning("unable to map GPC to enable perf\n");
> +               return;
> +       }
> +
> +       gpc = __raw_readl(gpc_reg);

You could use readl_relaxed() instead.

> +       gpc |= GPC_DBG_EN;
> +       __raw_writel(gpc, gpc_reg);

You could use writel_relaxed() instead.

> +
> +       return;

This 'return' can be removed.

> +}

Re: [PATCHv3 2/2] ARM: dts: imx53: PPD: Enable secure-reg-access

[Fabio Estevam]

On Fri, Feb 9, 2018 at 3:03 PM, Sebastian Reichel
<sebastian.reichel@collabora.co.uk> wrote:
> Add secure-reg-access on PPD device tree to enable PMU and
> hardware counters for perf.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>