[PATCH] serial: imx: fix cached UCR2 read on software reset

[PATCH] serial: imx: fix cached UCR2 read on software reset

[Stefan Agner]

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To reset the UART the SRST needs be cleared (low active). According
to the documentation the bit will remain active for 4 module clocks
until it is cleared (set to 1).

Hence the real register need to be read in case the cached register
indcates that the SRST bit is zero.

This bug lead to wrong baudrate because the baud rate register got
restored before reset completed in imx_flush_buffer.

Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and UFCR")
Signed-off-by: Stefan Agner <stefan@agner.ch>
Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 drivers/tty/serial/imx.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 91f3a1a5cb7f..4ff6bd6eb9ab 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -316,7 +316,7 @@ static u32 imx_uart_readl(struct imx_port *sport, u32 offset)
 		 * differ from the value that was last written. As it only
 		 * clears after being set, reread conditionally.
 		 */
-		if (sport->ucr2 & UCR2_SRST)
+		if (!(sport->ucr2 & UCR2_SRST))
 			sport->ucr2 = readl(sport->port.membase + offset);
 		return sport->ucr2;
 		break;
-- 
2.17.0

Re: [PATCH] serial: imx: fix cached UCR2 read on software reset

[Stefan Agner]

Hi Uwe,

On 16.04.2018 17:35, Stefan Agner wrote:
> To reset the UART the SRST needs be cleared (low active). According
> to the documentation the bit will remain active for 4 module clocks
> until it is cleared (set to 1).
> 
> Hence the real register need to be read in case the cached register
> indcates that the SRST bit is zero.
> 
> This bug lead to wrong baudrate because the baud rate register got
> restored before reset completed in imx_flush_buffer.

Given that you reviewed my other patch rather quickly, you might have
overlooked this one?

Since it is a regression, this should go into v4.17 still...

--
Stefan

> 
> Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx
> and UFCR")
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
>  drivers/tty/serial/imx.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
> index 91f3a1a5cb7f..4ff6bd6eb9ab 100644
> --- a/drivers/tty/serial/imx.c
> +++ b/drivers/tty/serial/imx.c
> @@ -316,7 +316,7 @@ static u32 imx_uart_readl(struct imx_port *sport,
> u32 offset)
>  		 * differ from the value that was last written. As it only
>  		 * clears after being set, reread conditionally.
>  		 */
> -		if (sport->ucr2 & UCR2_SRST)
> +		if (!(sport->ucr2 & UCR2_SRST))
>  			sport->ucr2 = readl(sport->port.membase + offset);
>  		return sport->ucr2;
>  		break;

Re: [PATCH] serial: imx: fix cached UCR2 read on software reset

[Fabio Estevam]

On Mon, Apr 16, 2018 at 12:35 PM, Stefan Agner <stefan@agner.ch> wrote:
> To reset the UART the SRST needs be cleared (low active). According
> to the documentation the bit will remain active for 4 module clocks
> until it is cleared (set to 1).
>
> Hence the real register need to be read in case the cached register
> indcates that the SRST bit is zero.

s/indcates/indicates

> This bug lead to wrong baudrate because the baud rate register got
> restored before reset completed in imx_flush_buffer.
>
> Fixes: 3a0ab62f43de ("serial: imx: implement shadow registers for UCRx and UFCR")
> Signed-off-by: Stefan Agner <stefan@agner.ch>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

Re: [PATCH] serial: imx: fix cached UCR2 read on software reset

[Uwe Kleine-König]

Hello Stefan,

On Thu, Apr 19, 2018 at 11:37:23PM +0200, Stefan Agner wrote:
> On 16.04.2018 17:35, Stefan Agner wrote:
> > To reset the UART the SRST needs be cleared (low active). According
> > to the documentation the bit will remain active for 4 module clocks
> > until it is cleared (set to 1).
> > 
> > Hence the real register need to be read in case the cached register
> > indcates that the SRST bit is zero.
> > 
> > This bug lead to wrong baudrate because the baud rate register got
> > restored before reset completed in imx_flush_buffer.
> 
> Given that you reviewed my other patch rather quickly, you might have
> overlooked this one?

no I didn't, still the ping was justified. I didn't look into it at once
because I didn't feel like opening the refman.
 
> Since it is a regression, this should go into v4.17 still...

That's right,

Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

I wonder what is different on your side that made it break. I didn't see
any breakage and tested that on a handful of different machines.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH] serial: imx: fix cached UCR2 read on software reset

[Stefan Agner]

On 20.04.2018 08:03, Uwe Kleine-König wrote:
> Hello Stefan,
> 
> On Thu, Apr 19, 2018 at 11:37:23PM +0200, Stefan Agner wrote:
>> On 16.04.2018 17:35, Stefan Agner wrote:
>> > To reset the UART the SRST needs be cleared (low active). According
>> > to the documentation the bit will remain active for 4 module clocks
>> > until it is cleared (set to 1).
>> >
>> > Hence the real register need to be read in case the cached register
>> > indcates that the SRST bit is zero.
>> >
>> > This bug lead to wrong baudrate because the baud rate register got
>> > restored before reset completed in imx_flush_buffer.
>>
>> Given that you reviewed my other patch rather quickly, you might have
>> overlooked this one?
> 
> no I didn't, still the ping was justified. I didn't look into it at once
> because I didn't feel like opening the refman.
>  
>> Since it is a regression, this should go into v4.17 still...
> 
> That's right,
> 
> Reviewed-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> 
> I wonder what is different on your side that made it break. I didn't see
> any breakage and tested that on a handful of different machines.

I observed it on a i.MX 6DualLite, UART in DTE mode...

It did work on a i.MX 7Dual just fine for me too. Probably bus clock
etc. dependent...

--
Stefan

> 
> Best regards
> Uwe