[PATCH V4 0/4] cpufreq: exynos5440: support for cpufreq driver

[PATCH V4 0/4] cpufreq: exynos5440: support for cpufreq driver

[Amit Daniel Kachhap]

Submitting the V4 version of exynos5440 cpufreq driver. This patchset addresses
all the coding and design concerns raised especially by Viresh.

Changes in V4:
* Added dev_err logs instead of pr_err.
* Used the devm_ioremap_resource API.
* Implemented several coding guidelines and minor error comments from Sylwester,
  Russell and Viresh.

Changes in V3:
* Converted the driver to probe based as suggested by Viresh. This is also
  beneficial for multiplatform kernel.
* Other coding guidelines related changes.
* Moved the DT node outside cpu0 node as the driver is now a platform
  driver.

Changes in V2:
* Added OPP library support to parse DT parameters.
* Removed a hack to handle interrupts in bootup.
* Implemented other review comments from Viresh and Inder.

All these patches are dependent on Thomas Abraham common clock patches.
(http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg15860.html)
This whole patch series is based on 3.9-rc2.

Amit Daniel Kachhap (4):
  cpufreq: exynos: Adding cpufreq driver for exynos5440
  cpufreq: exynos: Remove error return even if no soc is found
  arm: exynos: Enable OPP library support for exynos5440
  dts: Add cpufreq controller node for Exynos5440 SoC

 .../bindings/cpufreq/cpufreq-exynos5440.txt        |   29 ++
 arch/arm/boot/dts/exynos5440.dtsi                  |   12 +
 arch/arm/mach-exynos/Kconfig                       |    2 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |    2 +
 drivers/cpufreq/Kconfig.arm                        |    9 +
 drivers/cpufreq/Makefile                           |    1 +
 drivers/cpufreq/exynos-cpufreq.c                   |    2 +-
 drivers/cpufreq/exynos5440-cpufreq.c               |  466 ++++++++++++++++++++
 8 files changed, 522 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt
 create mode 100644 drivers/cpufreq/exynos5440-cpufreq.c

[PATCH V4 1/4] cpufreq: exynos: Adding cpufreq driver for exynos5440

[Amit Daniel Kachhap]

This patch adds dvfs support for exynos5440 SOC. This soc has 4 cores and
they scale at same frequency. The nature of exynos5440 clock controller is
different from previous exynos controllers so not using the common exynos
cpufreq framework. The major difference being interrupt notfication for
frequency change. Also, OPP library is used for device tree parsing to get
different parameters like frequency, voltage etc. Since the opp library sorts
the frequency table in ascending order so they are again re-arranged in
descending order. This will have one-to-one mapping with the clock controller
state management logic.

Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
---
 .../bindings/cpufreq/cpufreq-exynos5440.txt        |   29 ++
 drivers/cpufreq/Kconfig.arm                        |    9 +
 drivers/cpufreq/Makefile                           |    1 +
 drivers/cpufreq/exynos5440-cpufreq.c               |  466 ++++++++++++++++++++
 4 files changed, 505 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt
 create mode 100644 drivers/cpufreq/exynos5440-cpufreq.c

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt
new file mode 100644
index 0000000..a0dbe0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt
@@ -0,0 +1,29 @@
+
+Exynos5440 cpufreq driver
+-------------------
+
+Exynos5440 SoC cpufreq driver for CPU frequency scaling.
+
+Required properties:
+- interrupts: Interrupt to know the completion of cpu frequency change.
+- operating-points: Table of frequencies and voltage CPU could be transitioned into,
+	in the decreasing order. Frequency should be in KHZ units and voltage
+	should be in microvolts.
+
+Optional properties:
+- clock-latency: Clock monitor latency in microsecond.
+
+All the required listed above must be defined under node cpufreq.
+
+Example:
+--------
+	cpufreq@160000 {
+		compatible = "samsung,exynos5440-cpufreq";
+		reg = <0x160000 0x1000>;
+		interrupts = <0 57 0>;
+		operating-points = <
+				1000000 975000
+				800000  925000>;
+		clock-latency = <100000>;
+	};
+
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 030ddf6..7ed9c4a 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -77,6 +77,15 @@ config ARM_EXYNOS5250_CPUFREQ
 	  This adds the CPUFreq driver for Samsung EXYNOS5250
 	  SoC.
 
+config ARM_EXYNOS5440_CPUFREQ
+	def_bool SOC_EXYNOS5440
+	depends on HAVE_CLK && PM_OPP && OF
+	help
+	  This adds the CPUFreq driver for Samsung EXYNOS5440
+	  SoC. The nature of exynos5440 clock controller is
+	  different than previous exynos controllers so not using
+	  the common exynos framework.
+
 config ARM_KIRKWOOD_CPUFREQ
 	def_bool ARCH_KIRKWOOD && OF
 	help
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 863fd18..c841438 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_ARM_EXYNOS_CPUFREQ)	+= exynos-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ)	+= exynos4210-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS4X12_CPUFREQ)	+= exynos4x12-cpufreq.o
 obj-$(CONFIG_ARM_EXYNOS5250_CPUFREQ)	+= exynos5250-cpufreq.o
+obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ)	+= exynos5440-cpufreq.o
 obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ)	+= kirkwood-cpufreq.o
 obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ)	+= omap-cpufreq.o
 obj-$(CONFIG_ARM_SPEAR_CPUFREQ)		+= spear-cpufreq.o
diff --git a/drivers/cpufreq/exynos5440-cpufreq.c b/drivers/cpufreq/exynos5440-cpufreq.c
new file mode 100644
index 0000000..d65d91d
--- /dev/null
+++ b/drivers/cpufreq/exynos5440-cpufreq.c
@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Amit Daniel Kachhap <amit.daniel@samsung.com>
+ *
+ * EXYNOS5440 - CPU frequency scaling support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clk.h>
+#include <linux/cpu.h>
+#include <linux/cpufreq.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/opp.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+/* Register definitions */
+#define XMU_DVFS_CTRL		0x0060
+#define XMU_PMU_P0_7		0x0064
+#define XMU_C0_3_PSTATE		0x0090
+#define XMU_P_LIMIT		0x00a0
+#define XMU_P_STATUS		0x00a4
+#define XMU_PMUEVTEN		0x00d0
+#define XMU_PMUIRQEN		0x00d4
+#define XMU_PMUIRQ		0x00d8
+
+/* PMU mask and shift definations */
+#define P_VALUE_MASK		0x7
+
+#define XMU_DVFS_CTRL_EN_SHIFT	0
+
+#define P0_7_CPUCLKDEV_SHIFT	21
+#define P0_7_CPUCLKDEV_MASK	0x7
+#define P0_7_ATBCLKDEV_SHIFT	18
+#define P0_7_ATBCLKDEV_MASK	0x7
+#define P0_7_CSCLKDEV_SHIFT	15
+#define P0_7_CSCLKDEV_MASK	0x7
+#define P0_7_CPUEMA_SHIFT	28
+#define P0_7_CPUEMA_MASK	0xf
+#define P0_7_L2EMA_SHIFT	24
+#define P0_7_L2EMA_MASK		0xf
+#define P0_7_VDD_SHIFT		8
+#define P0_7_VDD_MASK		0x7f
+#define P0_7_FREQ_SHIFT		0
+#define P0_7_FREQ_MASK		0xff
+
+#define C0_3_PSTATE_VALID_SHIFT	8
+#define C0_3_PSTATE_CURR_SHIFT	4
+#define C0_3_PSTATE_NEW_SHIFT	0
+
+#define PSTATE_CHANGED_EVTEN_SHIFT	0
+
+#define PSTATE_CHANGED_IRQEN_SHIFT	0
+
+#define PSTATE_CHANGED_SHIFT		0
+
+/* some constant values for clock divider calculation */
+#define CPU_DIV_FREQ_MAX	500
+#define CPU_DBG_FREQ_MAX	375
+#define CPU_ATB_FREQ_MAX	500
+
+#define PMIC_LOW_VOLT		0x30
+#define PMIC_HIGH_VOLT		0x28
+
+#define CPUEMA_HIGH		0x2
+#define CPUEMA_MID		0x4
+#define CPUEMA_LOW		0x7
+
+#define L2EMA_HIGH		0x1
+#define L2EMA_MID		0x3
+#define L2EMA_LOW		0x4
+
+#define DIV_TAB_MAX	2
+/* frequency unit is 20MHZ */
+#define FREQ_UNIT	20
+#define MAX_VOLTAGE	1550000 /* In micro volt */
+#define VOLTAGE_STEP	12500	/* In micro volt */
+
+#define CPUFREQ_NAME		"exynos5440_dvfs"
+#define DEF_TRANS_LATENCY	100000
+
+enum cpufreq_level_index {
+	L0, L1, L2, L3, L4,
+	L5, L6, L7, L8, L9,
+};
+#define CPUFREQ_LEVEL_END	(L7 + 1)
+
+struct exynos_dvfs_data {
+	void __iomem *base;
+	struct resource *mem;
+	int irq;
+	struct clk *cpu_clk;
+	unsigned int cur_frequency;
+	unsigned int latency;
+	struct cpufreq_frequency_table *freq_table;
+	unsigned int freq_count;
+	struct device *dev;
+	bool dvfs_enabled;
+	struct work_struct irq_work;
+};
+
+static struct exynos_dvfs_data *dvfs_info;
+static DEFINE_MUTEX(cpufreq_lock);
+static struct cpufreq_freqs freqs;
+
+static int init_div_table(void)
+{
+	struct cpufreq_frequency_table *freq_tbl = dvfs_info->freq_table;
+	unsigned int tmp, clk_div, ema_div, freq, volt_id;
+	int i = 0;
+	struct opp *opp;
+
+	for (i = 0; freq_tbl[i].frequency != CPUFREQ_TABLE_END; i++) {
+
+		opp = opp_find_freq_exact(dvfs_info->dev,
+					freq_tbl[i].frequency * 1000, true);
+		if (IS_ERR(opp)) {
+			dev_err(dvfs_info->dev,
+				"failed to find valid OPP for %u KHZ\n",
+				freq_tbl[i].frequency);
+			return PTR_ERR(opp);
+		}
+
+		freq = freq_tbl[i].frequency / 1000; /* In MHZ */
+		clk_div = ((freq / CPU_DIV_FREQ_MAX) & P0_7_CPUCLKDEV_MASK)
+					<< P0_7_CPUCLKDEV_SHIFT;
+		clk_div |= ((freq / CPU_ATB_FREQ_MAX) & P0_7_ATBCLKDEV_MASK)
+					<< P0_7_ATBCLKDEV_SHIFT;
+		clk_div |= ((freq / CPU_DBG_FREQ_MAX) & P0_7_CSCLKDEV_MASK)
+					<< P0_7_CSCLKDEV_SHIFT;
+
+		/* Calculate EMA */
+		volt_id = opp_get_voltage(opp);
+		volt_id = (MAX_VOLTAGE - volt_id) / VOLTAGE_STEP;
+		if (volt_id < PMIC_HIGH_VOLT) {
+			ema_div = (CPUEMA_HIGH << P0_7_CPUEMA_SHIFT) |
+				(L2EMA_HIGH << P0_7_L2EMA_SHIFT);
+		} else if (volt_id > PMIC_LOW_VOLT) {
+			ema_div = (CPUEMA_LOW << P0_7_CPUEMA_SHIFT) |
+				(L2EMA_LOW << P0_7_L2EMA_SHIFT);
+		} else {
+			ema_div = (CPUEMA_MID << P0_7_CPUEMA_SHIFT) |
+				(L2EMA_MID << P0_7_L2EMA_SHIFT);
+		}
+
+		tmp = (clk_div | ema_div | (volt_id << P0_7_VDD_SHIFT)
+			| ((freq / FREQ_UNIT) << P0_7_FREQ_SHIFT));
+
+		__raw_writel(tmp, dvfs_info->base + XMU_PMU_P0_7 + 4 * i);
+	}
+
+	return 0;
+}
+
+static void exynos_enable_dvfs(void)
+{
+	unsigned int tmp, i, cpu;
+	struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
+	/* Disable DVFS */
+	__raw_writel(0,	dvfs_info->base + XMU_DVFS_CTRL);
+
+	/* Enable PSTATE Change Event */
+	tmp = __raw_readl(dvfs_info->base + XMU_PMUEVTEN);
+	tmp |= (1 << PSTATE_CHANGED_EVTEN_SHIFT);
+	 __raw_writel(tmp, dvfs_info->base + XMU_PMUEVTEN);
+
+	/* Enable PSTATE Change IRQ */
+	tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQEN);
+	tmp |= (1 << PSTATE_CHANGED_IRQEN_SHIFT);
+	 __raw_writel(tmp, dvfs_info->base + XMU_PMUIRQEN);
+
+	/* Set initial performance index */
+	for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
+		if (freq_table[i].frequency == dvfs_info->cur_frequency)
+			break;
+
+	if (freq_table[i].frequency == CPUFREQ_TABLE_END) {
+		dev_crit(dvfs_info->dev, "Boot up frequency not supported\n");
+		/* Assign the highest frequency */
+		i = 0;
+		dvfs_info->cur_frequency = freq_table[i].frequency;
+	}
+
+	dev_info(dvfs_info->dev, "Setting dvfs initial frequency = %uKHZ",
+						dvfs_info->cur_frequency);
+
+	for (cpu = 0; cpu < CONFIG_NR_CPUS; cpu++) {
+		tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
+		tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
+		tmp |= (i << C0_3_PSTATE_NEW_SHIFT);
+		__raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + cpu * 4);
+	}
+
+	/* Enable DVFS */
+	__raw_writel(1 << XMU_DVFS_CTRL_EN_SHIFT,
+				dvfs_info->base + XMU_DVFS_CTRL);
+}
+
+static int exynos_verify_speed(struct cpufreq_policy *policy)
+{
+	return cpufreq_frequency_table_verify(policy,
+					      dvfs_info->freq_table);
+}
+
+static unsigned int exynos_getspeed(unsigned int cpu)
+{
+	return dvfs_info->cur_frequency;
+}
+
+static int exynos_target(struct cpufreq_policy *policy,
+			  unsigned int target_freq,
+			  unsigned int relation)
+{
+	unsigned int index, tmp;
+	int ret = 0, i;
+	struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
+
+	mutex_lock(&cpufreq_lock);
+	freqs.old = dvfs_info->cur_frequency;
+
+	if (cpufreq_frequency_table_target(policy, freq_table,
+					   target_freq, relation, &index)) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	freqs.new = freq_table[index].frequency;
+	freqs.cpu = policy->cpu;
+
+	for_each_cpu(freqs.cpu, policy->cpus)
+		cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+	/* Set the target frequency in all C0_3_PSTATE register */
+	for_each_cpu(i, policy->cpus) {
+		tmp = __raw_readl(dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
+		tmp &= ~(P_VALUE_MASK << C0_3_PSTATE_NEW_SHIFT);
+		tmp |= (index << C0_3_PSTATE_NEW_SHIFT);
+
+		__raw_writel(tmp, dvfs_info->base + XMU_C0_3_PSTATE + i * 4);
+	}
+out:
+	mutex_unlock(&cpufreq_lock);
+	return ret;
+}
+
+static void exynos_cpufreq_work(struct work_struct *work)
+{
+	unsigned int cur_pstate, index;
+	struct cpufreq_policy *policy = cpufreq_cpu_get(0); /* boot CPU */
+	struct cpufreq_frequency_table *freq_table = dvfs_info->freq_table;
+
+	/* Ensure we can access cpufreq structures */
+	if (unlikely(dvfs_info->dvfs_enabled == false))
+		goto skip_work;
+
+	mutex_lock(&cpufreq_lock);
+	freqs.old = dvfs_info->cur_frequency;
+
+	cur_pstate = __raw_readl(dvfs_info->base + XMU_P_STATUS);
+	if (cur_pstate >> C0_3_PSTATE_VALID_SHIFT & 0x1)
+		index = (cur_pstate >> C0_3_PSTATE_CURR_SHIFT) & P_VALUE_MASK;
+	else
+		index = (cur_pstate >> C0_3_PSTATE_NEW_SHIFT) & P_VALUE_MASK;
+
+	if (likely(index < dvfs_info->freq_count)) {
+		freqs.new = freq_table[index].frequency;
+		for_each_cpu(freqs.cpu, policy->cpus)
+			cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+		dvfs_info->cur_frequency = freqs.new;
+	} else {
+		dev_crit(dvfs_info->dev, "New frequency out of range\n");
+	}
+
+	cpufreq_cpu_put(policy);
+	mutex_unlock(&cpufreq_lock);
+skip_work:
+	enable_irq(dvfs_info->irq);
+}
+
+static irqreturn_t exynos_cpufreq_irq(int irq, void *id)
+{
+	unsigned int tmp;
+
+	tmp = __raw_readl(dvfs_info->base + XMU_PMUIRQ);
+	if (tmp >> PSTATE_CHANGED_SHIFT & 0x1) {
+		__raw_writel(tmp, dvfs_info->base + XMU_PMUIRQ);
+		disable_irq_nosync(irq);
+		schedule_work(&dvfs_info->irq_work);
+	}
+	return IRQ_HANDLED;
+}
+
+static void exynos_sort_descend_freq_table(void)
+{
+	struct cpufreq_frequency_table *freq_tbl = dvfs_info->freq_table;
+	int i = 0, index;
+	unsigned int tmp_freq;
+
+	/*
+	 * Freq table is already in ascending order as it is created from
+	 * OPP library, so just swap the elements to make it descending.
+	 */
+	for (i = 0; i < dvfs_info->freq_count / 2; i++) {
+		index = dvfs_info->freq_count - i - 1;
+		tmp_freq = freq_tbl[i].frequency;
+		freq_tbl[i].frequency = freq_tbl[index].frequency;
+		freq_tbl[index].frequency = tmp_freq;
+	}
+}
+
+static int exynos_cpufreq_cpu_init(struct cpufreq_policy *policy)
+{
+	policy->cur = dvfs_info->cur_frequency;
+	cpufreq_frequency_table_get_attr(dvfs_info->freq_table, policy->cpu);
+
+	/* set the transition latency value */
+	policy->cpuinfo.transition_latency = dvfs_info->latency;
+
+	cpumask_setall(policy->cpus);
+
+	return cpufreq_frequency_table_cpuinfo(policy, dvfs_info->freq_table);
+}
+
+static struct cpufreq_driver exynos_driver = {
+	.flags		= CPUFREQ_STICKY,
+	.verify		= exynos_verify_speed,
+	.target		= exynos_target,
+	.get		= exynos_getspeed,
+	.init		= exynos_cpufreq_cpu_init,
+	.name		= CPUFREQ_NAME,
+};
+
+static int exynos_cpufreq_probe(struct platform_device *pdev)
+{
+	int ret = -EINVAL;
+	struct device_node *np;
+	struct resource res;
+
+	np =  of_find_compatible_node(NULL, NULL, "samsung,exynos5440-cpufreq");
+	if (!np)
+		return -ENODEV;
+
+	dvfs_info = devm_kzalloc(&pdev->dev, sizeof(*dvfs_info), GFP_KERNEL);
+	if (!dvfs_info) {
+		ret = -ENOMEM;
+		goto err_put_node;
+	}
+
+	dvfs_info->dev = &pdev->dev;
+	dvfs_info->dev->of_node = np;
+
+	ret = of_address_to_resource(np, 0, &res);
+	if (ret)
+		goto err_put_node;
+
+	dvfs_info->base = devm_ioremap_resource(dvfs_info->dev, &res);
+	if (IS_ERR(dvfs_info->base)) {
+		ret = PTR_ERR(dvfs_info->base);
+		goto err_put_node;
+	}
+
+	dvfs_info->irq = irq_of_parse_and_map(np, 0);
+	if (dvfs_info->irq == 0) {
+		dev_err(dvfs_info->dev, "No cpufreq irq found\n");
+		ret = -ENODEV;
+		goto err_put_node;
+	}
+
+	ret = of_init_opp_table(dvfs_info->dev);
+	if (ret) {
+		dev_err(dvfs_info->dev, "failed to init OPP table: %d\n", ret);
+		goto err_put_node;
+	}
+
+	ret = opp_init_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
+	if (ret) {
+		dev_err(dvfs_info->dev,
+			"failed to init cpufreq table: %d\n", ret);
+		goto err_put_node;
+	}
+	dvfs_info->freq_count = opp_get_opp_count(dvfs_info->dev);
+	exynos_sort_descend_freq_table();
+
+	if (of_property_read_u32(np, "clock-latency", &dvfs_info->latency))
+		dvfs_info->latency = DEF_TRANS_LATENCY;
+
+	dvfs_info->cpu_clk = devm_clk_get(dvfs_info->dev, "armclk");
+	if (IS_ERR(dvfs_info->cpu_clk)) {
+		dev_err(dvfs_info->dev, "Failed to get cpu clock\n");
+		ret = PTR_ERR(dvfs_info->cpu_clk);
+		goto err_free_table;
+	}
+
+	dvfs_info->cur_frequency = clk_get_rate(dvfs_info->cpu_clk);
+	if (!dvfs_info->cur_frequency) {
+		dev_err(dvfs_info->dev, "Failed to get clock rate\n");
+		ret = -EINVAL;
+		goto err_free_table;
+	}
+	dvfs_info->cur_frequency /= 1000;
+
+	INIT_WORK(&dvfs_info->irq_work, exynos_cpufreq_work);
+	ret = devm_request_irq(dvfs_info->dev, dvfs_info->irq,
+				exynos_cpufreq_irq, IRQF_TRIGGER_NONE,
+				CPUFREQ_NAME, dvfs_info);
+	if (ret) {
+		dev_err(dvfs_info->dev, "Failed to register IRQ\n");
+		goto err_free_table;
+	}
+
+	ret = init_div_table();
+	if (ret) {
+		dev_err(dvfs_info->dev, "Failed to initialise div table\n");
+		goto err_free_table;
+	}
+
+	exynos_enable_dvfs();
+	ret = cpufreq_register_driver(&exynos_driver);
+	if (ret) {
+		dev_err(dvfs_info->dev,
+			"%s: failed to register cpufreq driver\n", __func__);
+		goto err_free_table;
+	}
+
+	of_node_put(np);
+	dvfs_info->dvfs_enabled = true;
+	return 0;
+
+err_free_table:
+	opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
+err_put_node:
+	of_node_put(np);
+	dev_err(dvfs_info->dev, "%s: failed initialization\n", __func__);
+	return ret;
+}
+
+static int exynos_cpufreq_remove(struct platform_device *pdev)
+{
+	cpufreq_unregister_driver(&exynos_driver);
+	opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
+	return 0;
+}
+
+static struct platform_driver exynos_cpufreq_platdrv = {
+	.driver = {
+		.name	= "exynos5440-cpufreq",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= exynos_cpufreq_probe,
+	.remove		= exynos_cpufreq_remove,
+};
+module_platform_driver(exynos_cpufreq_platdrv);
+
+MODULE_AUTHOR("Amit Daniel Kachhap <amit.daniel@samsung.com>");
+MODULE_DESCRIPTION("Exynos5440 cpufreq driver");
+MODULE_LICENSE("GPL");
-- 
1.7.1

[PATCH V4 2/4] cpufreq: exynos: Remove error return even if no soc is found

[Amit Daniel Kachhap]

This patch helps to have single binary for exynos5440 and previous
exynos soc's. This change is needed for adding exynos5440 cpufreq driver
which does not uses exynos-cpufreq common file and adds it own driver.

Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
---
 drivers/cpufreq/exynos-cpufreq.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/cpufreq/exynos-cpufreq.c b/drivers/cpufreq/exynos-cpufreq.c
index 78057a3..ee75997 100644
--- a/drivers/cpufreq/exynos-cpufreq.c
+++ b/drivers/cpufreq/exynos-cpufreq.c
@@ -297,7 +297,7 @@ static int __init exynos_cpufreq_init(void)
 	else if (soc_is_exynos5250())
 		ret = exynos5250_cpufreq_init(exynos_info);
 	else
-		pr_err("%s: CPU type not found\n", __func__);
+		return 0;
 
 	if (ret)
 		goto err_vdd_arm;
-- 
1.7.1

[PATCH V4 3/4] arm: exynos: Enable OPP library support for exynos5440

[Amit Daniel Kachhap]

The OPP library support is needed for exynos5440 cpu frequency
dynamic scaling driver.

Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
---
 arch/arm/mach-exynos/Kconfig |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 70f94c8..d5dde07 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -72,10 +72,12 @@ config SOC_EXYNOS5440
 	bool "SAMSUNG EXYNOS5440"
 	default y
 	depends on ARCH_EXYNOS5
+	select ARCH_HAS_OPP
 	select ARM_ARCH_TIMER
 	select AUTO_ZRELADDR
 	select PINCTRL
 	select PINCTRL_EXYNOS5440
+	select PM_OPP
 	help
 	  Enable EXYNOS5440 SoC support
 
-- 
1.7.1

[PATCH V4 4/4] dts: Add cpufreq controller node for Exynos5440 SoC

[Amit Daniel Kachhap]

Add cpufreq controller device node for Exynos5440 SoC for passing
parameters like controller base address, interrupt and cpufreq
table. This node is added outside cpu0 as this driver is now a platform
driver and a new device structure is needed.

Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
---
 arch/arm/boot/dts/exynos5440.dtsi      |   12 ++++++++++++
 arch/arm/mach-exynos/mach-exynos5-dt.c |    2 ++
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 5f3562a..4b29a5a 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -63,6 +63,18 @@
 
 	};
 
+	cpufreq@160000 {
+		compatible = "samsung,exynos5440-cpufreq";
+		reg = <0x160000 0x1000>;
+		interrupts = <0 57 0>;
+		operating-points = <
+				/* KHZ	  uV */
+				1200000 1025000
+				1000000 975000
+				800000  925000
+		>;
+	};
+
 	serial@B0000 {
 		compatible = "samsung,exynos4210-uart";
 		reg = <0xB0000 0x1000>;
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index acaeb14..0a446c4 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -145,6 +145,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
 	OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
 				"exynos4210-uart.0", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5440-cpufreq", 0x160000,
+				"exynos5440-cpufreq", NULL),
 	{},
 };
 
-- 
1.7.1

Re: [PATCH V4 1/4] cpufreq: exynos: Adding cpufreq driver for exynos5440

[Viresh Kumar]

This is what Russell told me a long time back:
"Don't use Adding, Fixing, etc words as this work is not something, which is
already done."

So your subject should have been: "cpufreq: exynos: Add cpufreq driver
for exynos5440"

Fix it if you need another version, which i believe you do :)

On Tue, Mar 12, 2013 at 5:58 PM, Amit Daniel Kachhap
<amit.daniel@samsung.com> wrote:
> This patch adds dvfs support for exynos5440 SOC. This soc has 4 cores and
> they scale at same frequency. The nature of exynos5440 clock controller is
> different from previous exynos controllers so not using the common exynos
> cpufreq framework. The major difference being interrupt notfication for

s/notfication/notification

> frequency change. Also, OPP library is used for device tree parsing to get
> different parameters like frequency, voltage etc. Since the opp library sorts
> the frequency table in ascending order so they are again re-arranged in
> descending order. This will have one-to-one mapping with the clock controller
> state management logic.
>
> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> ---
>  .../bindings/cpufreq/cpufreq-exynos5440.txt        |   29 ++
>  drivers/cpufreq/Kconfig.arm                        |    9 +
>  drivers/cpufreq/Makefile                           |    1 +
>  drivers/cpufreq/exynos5440-cpufreq.c               |  466 ++++++++++++++++++++
>  4 files changed, 505 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt
>  create mode 100644 drivers/cpufreq/exynos5440-cpufreq.c
>
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt
> new file mode 100644
> index 0000000..a0dbe0b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt
> @@ -0,0 +1,29 @@
> +
> +Exynos5440 cpufreq driver
> +-------------------
> +
> +Exynos5440 SoC cpufreq driver for CPU frequency scaling.
> +
> +Required properties:
> +- interrupts: Interrupt to know the completion of cpu frequency change.
> +- operating-points: Table of frequencies and voltage CPU could be transitioned into,
> +       in the decreasing order. Frequency should be in KHZ units and voltage

s/KHZ/KHz

> +       should be in microvolts.

probably s/microvolts/micro-volts ??

> +
> +Optional properties:
> +- clock-latency: Clock monitor latency in microsecond.
> +
> +All the required listed above must be defined under node cpufreq.
> +
> +Example:
> +--------
> +       cpufreq@160000 {
> +               compatible = "samsung,exynos5440-cpufreq";
> +               reg = <0x160000 0x1000>;
> +               interrupts = <0 57 0>;
> +               operating-points = <
> +                               1000000 975000
> +                               800000  925000>;
> +               clock-latency = <100000>;
> +       };
> +

> diff --git a/drivers/cpufreq/exynos5440-cpufreq.c b/drivers/cpufreq/exynos5440-cpufreq.c
> +static void exynos_enable_dvfs(void)
> +{

> +       /* Set initial performance index */
> +       for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
> +               if (freq_table[i].frequency == dvfs_info->cur_frequency)
> +                       break;
> +
> +       if (freq_table[i].frequency == CPUFREQ_TABLE_END) {
> +               dev_crit(dvfs_info->dev, "Boot up frequency not supported\n");
> +               /* Assign the highest frequency */
> +               i = 0;
> +               dvfs_info->cur_frequency = freq_table[i].frequency;

What about:

dvfs_info->cur_frequency = freq_table[0].frequency;

as i don't see i being used again?

> +       }

> +}

> +static int exynos_target(struct cpufreq_policy *policy,
> +                         unsigned int target_freq,
> +                         unsigned int relation)
> +{

> +       if (cpufreq_frequency_table_target(policy, freq_table,
> +                                          target_freq, relation, &index)) {
> +               ret = -EINVAL;

Use the error value returned by called functions, probably i gave this
comment last time too?

> +               goto out;
> +       }

> +}

> +static void exynos_sort_descend_freq_table(void)
> +{
> +       struct cpufreq_frequency_table *freq_tbl = dvfs_info->freq_table;
> +       int i = 0, index;
> +       unsigned int tmp_freq;
> +
> +       /*
> +        * Freq table is already in ascending order as it is created from
> +        * OPP library, so just swap the elements to make it descending.

why??

> +        */
> +       for (i = 0; i < dvfs_info->freq_count / 2; i++) {
> +               index = dvfs_info->freq_count - i - 1;
> +               tmp_freq = freq_tbl[i].frequency;
> +               freq_tbl[i].frequency = freq_tbl[index].frequency;
> +               freq_tbl[index].frequency = tmp_freq;
> +       }
> +}
> +

> +static int exynos_cpufreq_probe(struct platform_device *pdev)
> +{
> +       int ret = -EINVAL;
> +       struct device_node *np;
> +       struct resource res;
> +
> +       np =  of_find_compatible_node(NULL, NULL, "samsung,exynos5440-cpufreq");
> +       if (!np)
> +               return -ENODEV;
> +
> +       dvfs_info = devm_kzalloc(&pdev->dev, sizeof(*dvfs_info), GFP_KERNEL);
> +       if (!dvfs_info) {
> +               ret = -ENOMEM;
> +               goto err_put_node;
> +       }
> +
> +       dvfs_info->dev = &pdev->dev;
> +       dvfs_info->dev->of_node = np;
> +
> +       ret = of_address_to_resource(np, 0, &res);
> +       if (ret)
> +               goto err_put_node;
> +
> +       dvfs_info->base = devm_ioremap_resource(dvfs_info->dev, &res);
> +       if (IS_ERR(dvfs_info->base)) {
> +               ret = PTR_ERR(dvfs_info->base);
> +               goto err_put_node;
> +       }
> +
> +       dvfs_info->irq = irq_of_parse_and_map(np, 0);
> +       if (dvfs_info->irq == 0) {

maybe, if (!dvfs_info->irq) {


> +               dev_err(dvfs_info->dev, "No cpufreq irq found\n");
> +               ret = -ENODEV;
> +               goto err_put_node;
> +       }
> +
> +       ret = of_init_opp_table(dvfs_info->dev);
> +       if (ret) {
> +               dev_err(dvfs_info->dev, "failed to init OPP table: %d\n", ret);
> +               goto err_put_node;
> +       }
> +
> +       ret = opp_init_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
> +       if (ret) {
> +               dev_err(dvfs_info->dev,
> +                       "failed to init cpufreq table: %d\n", ret);
> +               goto err_put_node;
> +       }
> +       dvfs_info->freq_count = opp_get_opp_count(dvfs_info->dev);
> +       exynos_sort_descend_freq_table();
> +
> +       if (of_property_read_u32(np, "clock-latency", &dvfs_info->latency))
> +               dvfs_info->latency = DEF_TRANS_LATENCY;
> +
> +       dvfs_info->cpu_clk = devm_clk_get(dvfs_info->dev, "armclk");
> +       if (IS_ERR(dvfs_info->cpu_clk)) {
> +               dev_err(dvfs_info->dev, "Failed to get cpu clock\n");
> +               ret = PTR_ERR(dvfs_info->cpu_clk);
> +               goto err_free_table;
> +       }
> +
> +       dvfs_info->cur_frequency = clk_get_rate(dvfs_info->cpu_clk);
> +       if (!dvfs_info->cur_frequency) {
> +               dev_err(dvfs_info->dev, "Failed to get clock rate\n");
> +               ret = -EINVAL;
> +               goto err_free_table;
> +       }
> +       dvfs_info->cur_frequency /= 1000;
> +
> +       INIT_WORK(&dvfs_info->irq_work, exynos_cpufreq_work);
> +       ret = devm_request_irq(dvfs_info->dev, dvfs_info->irq,
> +                               exynos_cpufreq_irq, IRQF_TRIGGER_NONE,
> +                               CPUFREQ_NAME, dvfs_info);
> +       if (ret) {
> +               dev_err(dvfs_info->dev, "Failed to register IRQ\n");
> +               goto err_free_table;
> +       }
> +
> +       ret = init_div_table();
> +       if (ret) {
> +               dev_err(dvfs_info->dev, "Failed to initialise div table\n");
> +               goto err_free_table;
> +       }
> +
> +       exynos_enable_dvfs();
> +       ret = cpufreq_register_driver(&exynos_driver);
> +       if (ret) {
> +               dev_err(dvfs_info->dev,
> +                       "%s: failed to register cpufreq driver\n", __func__);
> +               goto err_free_table;
> +       }
> +
> +       of_node_put(np);
> +       dvfs_info->dvfs_enabled = true;
> +       return 0;
> +
> +err_free_table:
> +       opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
> +err_put_node:
> +       of_node_put(np);
> +       dev_err(dvfs_info->dev, "%s: failed initialization\n", __func__);
> +       return ret;
> +}

Re: [PATCH V4 1/4] cpufreq: exynos: Adding cpufreq driver for exynos5440

[amit kachhap]

Hi Viresh,

On Tue, Mar 12, 2013 at 4:19 PM, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> This is what Russell told me a long time back:
> "Don't use Adding, Fixing, etc words as this work is not something, which is
> already done."
>
> So your subject should have been: "cpufreq: exynos: Add cpufreq driver
> for exynos5440"
ok right.
>
> Fix it if you need another version, which i believe you do :)
yes no escape now :)
>
> On Tue, Mar 12, 2013 at 5:58 PM, Amit Daniel Kachhap
> <amit.daniel@samsung.com> wrote:
>> This patch adds dvfs support for exynos5440 SOC. This soc has 4 cores and
>> they scale at same frequency. The nature of exynos5440 clock controller is
>> different from previous exynos controllers so not using the common exynos
>> cpufreq framework. The major difference being interrupt notfication for
>
> s/notfication/notification
ok
>
>> frequency change. Also, OPP library is used for device tree parsing to get
>> different parameters like frequency, voltage etc. Since the opp library sorts
>> the frequency table in ascending order so they are again re-arranged in
>> descending order. This will have one-to-one mapping with the clock controller
>> state management logic.
>>
>> Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
>> ---
>>  .../bindings/cpufreq/cpufreq-exynos5440.txt        |   29 ++
>>  drivers/cpufreq/Kconfig.arm                        |    9 +
>>  drivers/cpufreq/Makefile                           |    1 +
>>  drivers/cpufreq/exynos5440-cpufreq.c               |  466 ++++++++++++++++++++
>>  4 files changed, 505 insertions(+), 0 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt
>>  create mode 100644 drivers/cpufreq/exynos5440-cpufreq.c
>>
>> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt
>> new file mode 100644
>> index 0000000..a0dbe0b
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-exynos5440.txt
>> @@ -0,0 +1,29 @@
>> +
>> +Exynos5440 cpufreq driver
>> +-------------------
>> +
>> +Exynos5440 SoC cpufreq driver for CPU frequency scaling.
>> +
>> +Required properties:
>> +- interrupts: Interrupt to know the completion of cpu frequency change.
>> +- operating-points: Table of frequencies and voltage CPU could be transitioned into,
>> +       in the decreasing order. Frequency should be in KHZ units and voltage
>
> s/KHZ/KHz
ok
>
>> +       should be in microvolts.
>
> probably s/microvolts/micro-volts ??
>
>> +
>> +Optional properties:
>> +- clock-latency: Clock monitor latency in microsecond.
>> +
>> +All the required listed above must be defined under node cpufreq.
>> +
>> +Example:
>> +--------
>> +       cpufreq@160000 {
>> +               compatible = "samsung,exynos5440-cpufreq";
>> +               reg = <0x160000 0x1000>;
>> +               interrupts = <0 57 0>;
>> +               operating-points = <
>> +                               1000000 975000
>> +                               800000  925000>;
>> +               clock-latency = <100000>;
>> +       };
>> +
>
>> diff --git a/drivers/cpufreq/exynos5440-cpufreq.c b/drivers/cpufreq/exynos5440-cpufreq.c
>> +static void exynos_enable_dvfs(void)
>> +{
>
>> +       /* Set initial performance index */
>> +       for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++)
>> +               if (freq_table[i].frequency == dvfs_info->cur_frequency)
>> +                       break;
>> +
>> +       if (freq_table[i].frequency == CPUFREQ_TABLE_END) {
>> +               dev_crit(dvfs_info->dev, "Boot up frequency not supported\n");
>> +               /* Assign the highest frequency */
>> +               i = 0;
>> +               dvfs_info->cur_frequency = freq_table[i].frequency;
>
> What about:
>
> dvfs_info->cur_frequency = freq_table[0].frequency;
>
> as i don't see i being used again?
No It is used below for frequency setting.
>
>> +       }
>
>> +}
>
>> +static int exynos_target(struct cpufreq_policy *policy,
>> +                         unsigned int target_freq,
>> +                         unsigned int relation)
>> +{
>
>> +       if (cpufreq_frequency_table_target(policy, freq_table,
>> +                                          target_freq, relation, &index)) {
>> +               ret = -EINVAL;
>
> Use the error value returned by called functions, probably i gave this
> comment last time too?
yes my mistake.
>
>> +               goto out;
>> +       }
>
>> +}
>
>> +static void exynos_sort_descend_freq_table(void)
>> +{
>> +       struct cpufreq_frequency_table *freq_tbl = dvfs_info->freq_table;
>> +       int i = 0, index;
>> +       unsigned int tmp_freq;
>> +
>> +       /*
>> +        * Freq table is already in ascending order as it is created from
>> +        * OPP library, so just swap the elements to make it descending.
>
> why??
I explained this requirement in the patch commit. Will explain it here again.
>
>> +        */
>> +       for (i = 0; i < dvfs_info->freq_count / 2; i++) {
>> +               index = dvfs_info->freq_count - i - 1;
>> +               tmp_freq = freq_tbl[i].frequency;
>> +               freq_tbl[i].frequency = freq_tbl[index].frequency;
>> +               freq_tbl[index].frequency = tmp_freq;
>> +       }
>> +}
>> +
>
>> +static int exynos_cpufreq_probe(struct platform_device *pdev)
>> +{
>> +       int ret = -EINVAL;
>> +       struct device_node *np;
>> +       struct resource res;
>> +
>> +       np =  of_find_compatible_node(NULL, NULL, "samsung,exynos5440-cpufreq");
>> +       if (!np)
>> +               return -ENODEV;
>> +
>> +       dvfs_info = devm_kzalloc(&pdev->dev, sizeof(*dvfs_info), GFP_KERNEL);
>> +       if (!dvfs_info) {
>> +               ret = -ENOMEM;
>> +               goto err_put_node;
>> +       }
>> +
>> +       dvfs_info->dev = &pdev->dev;
>> +       dvfs_info->dev->of_node = np;
>> +
>> +       ret = of_address_to_resource(np, 0, &res);
>> +       if (ret)
>> +               goto err_put_node;
>> +
>> +       dvfs_info->base = devm_ioremap_resource(dvfs_info->dev, &res);
>> +       if (IS_ERR(dvfs_info->base)) {
>> +               ret = PTR_ERR(dvfs_info->base);
>> +               goto err_put_node;
>> +       }
>> +
>> +       dvfs_info->irq = irq_of_parse_and_map(np, 0);
>> +       if (dvfs_info->irq == 0) {
>
> maybe, if (!dvfs_info->irq) {
ok

Thanks,
Amit Daniel
>
>
>> +               dev_err(dvfs_info->dev, "No cpufreq irq found\n");
>> +               ret = -ENODEV;
>> +               goto err_put_node;
>> +       }
>> +
>> +       ret = of_init_opp_table(dvfs_info->dev);
>> +       if (ret) {
>> +               dev_err(dvfs_info->dev, "failed to init OPP table: %d\n", ret);
>> +               goto err_put_node;
>> +       }
>> +
>> +       ret = opp_init_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
>> +       if (ret) {
>> +               dev_err(dvfs_info->dev,
>> +                       "failed to init cpufreq table: %d\n", ret);
>> +               goto err_put_node;
>> +       }
>> +       dvfs_info->freq_count = opp_get_opp_count(dvfs_info->dev);
>> +       exynos_sort_descend_freq_table();
>> +
>> +       if (of_property_read_u32(np, "clock-latency", &dvfs_info->latency))
>> +               dvfs_info->latency = DEF_TRANS_LATENCY;
>> +
>> +       dvfs_info->cpu_clk = devm_clk_get(dvfs_info->dev, "armclk");
>> +       if (IS_ERR(dvfs_info->cpu_clk)) {
>> +               dev_err(dvfs_info->dev, "Failed to get cpu clock\n");
>> +               ret = PTR_ERR(dvfs_info->cpu_clk);
>> +               goto err_free_table;
>> +       }
>> +
>> +       dvfs_info->cur_frequency = clk_get_rate(dvfs_info->cpu_clk);
>> +       if (!dvfs_info->cur_frequency) {
>> +               dev_err(dvfs_info->dev, "Failed to get clock rate\n");
>> +               ret = -EINVAL;
>> +               goto err_free_table;
>> +       }
>> +       dvfs_info->cur_frequency /= 1000;
>> +
>> +       INIT_WORK(&dvfs_info->irq_work, exynos_cpufreq_work);
>> +       ret = devm_request_irq(dvfs_info->dev, dvfs_info->irq,
>> +                               exynos_cpufreq_irq, IRQF_TRIGGER_NONE,
>> +                               CPUFREQ_NAME, dvfs_info);
>> +       if (ret) {
>> +               dev_err(dvfs_info->dev, "Failed to register IRQ\n");
>> +               goto err_free_table;
>> +       }
>> +
>> +       ret = init_div_table();
>> +       if (ret) {
>> +               dev_err(dvfs_info->dev, "Failed to initialise div table\n");
>> +               goto err_free_table;
>> +       }
>> +
>> +       exynos_enable_dvfs();
>> +       ret = cpufreq_register_driver(&exynos_driver);
>> +       if (ret) {
>> +               dev_err(dvfs_info->dev,
>> +                       "%s: failed to register cpufreq driver\n", __func__);
>> +               goto err_free_table;
>> +       }
>> +
>> +       of_node_put(np);
>> +       dvfs_info->dvfs_enabled = true;
>> +       return 0;
>> +
>> +err_free_table:
>> +       opp_free_cpufreq_table(dvfs_info->dev, &dvfs_info->freq_table);
>> +err_put_node:
>> +       of_node_put(np);
>> +       dev_err(dvfs_info->dev, "%s: failed initialization\n", __func__);
>> +       return ret;
>> +}
> --
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